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@ -25,35 +25,25 @@ |
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#include <config.h> |
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#if defined(CONFIG_CMD_NAND) |
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#include <asm/gpio.h> |
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#include <asm/io.h> |
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#include <nand.h> |
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/*
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* hardware specific access to control-lines |
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*/ |
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static void quad100hd_hwcontrol(struct mtd_info *mtd, int cmd) |
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static void quad100hd_hwcontrol(struct mtd_info *mtd, |
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int cmd, unsigned int ctrl) |
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{ |
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switch(cmd) { |
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case NAND_CTL_SETCLE: |
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gpio_write_bit(CFG_NAND_CLE, 1); |
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break; |
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case NAND_CTL_CLRCLE: |
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gpio_write_bit(CFG_NAND_CLE, 0); |
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break; |
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struct nand_chip *this = mtd->priv; |
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case NAND_CTL_SETALE: |
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gpio_write_bit(CFG_NAND_ALE, 1); |
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break; |
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case NAND_CTL_CLRALE: |
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gpio_write_bit(CFG_NAND_ALE, 0); |
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break; |
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case NAND_CTL_SETNCE: |
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gpio_write_bit(CFG_NAND_CE, 0); |
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break; |
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case NAND_CTL_CLRNCE: |
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gpio_write_bit(CFG_NAND_CE, 1); |
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break; |
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if (ctrl & NAND_CTRL_CHANGE) { |
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gpio_write_bit(CFG_NAND_CLE, !!(ctrl & NAND_CLE)); |
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gpio_write_bit(CFG_NAND_ALE, !!(ctrl & NAND_ALE)); |
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gpio_write_bit(CFG_NAND_CE, !(ctrl & NAND_NCE)); |
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} |
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if (cmd != NAND_CMD_NONE) |
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writeb(cmd, this->IO_ADDR_W); |
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} |
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static int quad100hd_nand_ready(struct mtd_info *mtd) |
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@ -67,9 +57,9 @@ static int quad100hd_nand_ready(struct mtd_info *mtd) |
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int board_nand_init(struct nand_chip *nand) |
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{ |
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/* Set address of hardware control function */ |
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nand->hwcontrol = quad100hd_hwcontrol; |
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nand->cmd_ctrl = quad100hd_hwcontrol; |
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nand->dev_ready = quad100hd_nand_ready; |
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nand->eccmode = NAND_ECC_SOFT; |
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nand->ecc.mode = NAND_ECC_SOFT; |
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/* 15 us command delay time */ |
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nand->chip_delay = 20; |
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