Add support for IBM PPC440GX. Multiple EMAC Ethernet devices, select MDI port based on enabled EMAC device. Add support for XES Inc <http://www.xes-inc.com> XPedite1000 440GX base PrPMC board.master
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@ -0,0 +1,48 @@ |
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#
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# (C) Copyright 2002-2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS = $(BOARD).o
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OBJS +=flash.o
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SOBJS = init.o
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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sinclude .depend |
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#########################################################################
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@ -0,0 +1,44 @@ |
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#
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# (C) Copyright 2002-2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# esd ADCIOP boards
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#
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#TEXT_BASE = 0xFFFE0000
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ifeq ($(ramsym),1) |
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TEXT_BASE = 0x07FD0000
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else |
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TEXT_BASE = 0xFFF80000
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endif |
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PLATFORM_CPPFLAGS += -DCONFIG_440=1
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ifeq ($(debug),1) |
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PLATFORM_CPPFLAGS += -DDEBUG
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endif |
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ifeq ($(dbcr),1) |
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PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
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endif |
@ -0,0 +1,607 @@ |
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/*
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* (C) Copyright 2002-2004 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* (C) Copyright 2002 Jun Gu <jung@artesyncp.com> |
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* Add support for Am29F016D and dynamic switch setting. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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/*
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* Modified 4/5/2001 |
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* Wait for completion of each sector erase command issued |
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* 4/5/2001 |
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* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com |
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*/ |
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/*
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* Ported to XPedite1000, 1/2 mb boot flash only |
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* Travis B. Sawyer, <travis.sawyer@sandburst.com> |
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*/ |
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#include <common.h> |
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#include <ppc4xx.h> |
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#include <asm/processor.h> |
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#undef DEBUG |
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#ifdef DEBUG |
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#define DEBUGF(x...) printf(x) |
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#else |
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#define DEBUGF(x...) |
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#endif /* DEBUG */ |
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#define BOOT_SMALL_FLASH 32 /* 00100000 */ |
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#define FLASH_ONBD_N 2 /* 00000010 */ |
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#define FLASH_SRAM_SEL 1 /* 00000001 */ |
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#define BOOT_SMALL_FLASH_VAL 4 |
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#define FLASH_ONBD_N_VAL 2 |
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#define FLASH_SRAM_SEL_VAL 1 |
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = { |
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{0xfff80000}, /* 0:000: configuraton 3 */ |
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{0xfff90000}, /* 1:001: configuraton 4 */ |
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{0xfffa0000}, /* 2:010: configuraton 7 */ |
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{0xfffb0000}, /* 3:011: configuraton 8 */ |
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{0xfffc0000}, /* 4:100: configuraton 1 */ |
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{0xfffd0000}, /* 5:101: configuraton 2 */ |
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{0xfffe0000}, /* 6:110: configuraton 5 */ |
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{0xffff0000} /* 7:111: configuraton 6 */ |
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}; |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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static ulong flash_get_size (vu_long *addr, flash_info_t *info); |
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static int write_word (flash_info_t *info, ulong dest, ulong data); |
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#ifdef CONFIG_XPEDITE1K |
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#define ADDR0 0x5555 |
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#define ADDR1 0x2aaa |
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#define FLASH_WORD_SIZE unsigned char |
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#endif |
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init (void) |
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{ |
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unsigned long total_b = 0; |
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unsigned long size_b[CFG_MAX_FLASH_BANKS]; |
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unsigned short index = 0; |
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int i; |
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DEBUGF("\n"); |
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DEBUGF("FLASH: Index: %d\n", index); |
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/* Init: no FLASHes known */ |
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for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { |
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flash_info[i].flash_id = FLASH_UNKNOWN; |
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flash_info[i].sector_count = -1; |
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flash_info[i].size = 0; |
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/* check whether the address is 0 */ |
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if (flash_addr_table[index][i] == 0) { |
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continue; |
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} |
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/* call flash_get_size() to initialize sector address */ |
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size_b[i] = flash_get_size( |
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(vu_long *)flash_addr_table[index][i], &flash_info[i]); |
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flash_info[i].size = size_b[i]; |
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if (flash_info[i].flash_id == FLASH_UNKNOWN) { |
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printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", |
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i, size_b[i], size_b[i]<<20); |
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flash_info[i].sector_count = -1; |
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flash_info[i].size = 0; |
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} |
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total_b += flash_info[i].size; |
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} |
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return total_b; |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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void flash_print_info (flash_info_t *info) |
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{ |
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int i; |
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int k; |
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int size; |
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int erased; |
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volatile unsigned long *flash; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("missing or unknown FLASH type\n"); |
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return; |
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} |
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switch (info->flash_id & FLASH_VENDMASK) { |
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case FLASH_MAN_AMD: printf ("AMD "); break; |
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case FLASH_MAN_FUJ: printf ("FUJITSU "); break; |
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case FLASH_MAN_SST: printf ("SST "); break; |
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default: printf ("Unknown Vendor "); break; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) { |
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case FLASH_AMD016: printf ("AM29F016D (16 Mbit, uniform sector size)\n"); |
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break; |
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case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n"); |
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break; |
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case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); |
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break; |
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case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); |
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break; |
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case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); |
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break; |
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case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); |
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break; |
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case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); |
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break; |
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case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); |
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break; |
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case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); |
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break; |
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case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); |
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break; |
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case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); |
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break; |
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case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); |
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break; |
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default: printf ("Unknown Chip Type\n"); |
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break; |
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} |
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printf (" Size: %ld KB in %d Sectors\n", |
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info->size >> 10, info->sector_count); |
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printf (" Sector Start Addresses:"); |
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for (i=0; i<info->sector_count; ++i) { |
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/*
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* Check if whole sector is erased |
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*/ |
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if (i != (info->sector_count-1)) |
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size = info->start[i+1] - info->start[i]; |
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else |
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size = info->start[0] + info->size - info->start[i]; |
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erased = 1; |
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flash = (volatile unsigned long *)info->start[i]; |
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size = size >> 2; /* divide by 4 for longword access */ |
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for (k=0; k<size; k++) |
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{ |
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if (*flash++ != 0xffffffff) |
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{ |
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erased = 0; |
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break; |
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} |
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} |
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if ((i % 5) == 0) |
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printf ("\n "); |
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printf (" %08lX%s%s", |
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info->start[i], |
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erased ? " E" : " ", |
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info->protect[i] ? "RO " : " " |
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); |
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} |
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printf ("\n"); |
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return; |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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/*-----------------------------------------------------------------------
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*/ |
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/*
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* The following code cannot be run from FLASH! |
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*/ |
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static ulong flash_get_size (vu_long *addr, flash_info_t *info) |
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{ |
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short i; |
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FLASH_WORD_SIZE value; |
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ulong base = (ulong)addr; |
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volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; |
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DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr ); |
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/* Write auto select command: read Manufacturer ID */ |
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udelay(10000); |
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addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; |
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udelay(1000); |
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addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; |
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udelay(1000); |
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addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; |
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udelay(1000); |
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#ifdef CONFIG_ADCIOP |
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value = addr2[2]; |
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#else |
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value = addr2[0]; |
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#endif |
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DEBUGF("FLASH MANUFACT: %x\n", value); |
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switch (value) { |
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case (FLASH_WORD_SIZE)AMD_MANUFACT: |
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info->flash_id = FLASH_MAN_AMD; |
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break; |
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case (FLASH_WORD_SIZE)FUJ_MANUFACT: |
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info->flash_id = FLASH_MAN_FUJ; |
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break; |
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case (FLASH_WORD_SIZE)SST_MANUFACT: |
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info->flash_id = FLASH_MAN_SST; |
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break; |
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case (FLASH_WORD_SIZE)STM_MANUFACT: |
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info->flash_id = FLASH_MAN_STM; |
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break; |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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info->sector_count = 0; |
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info->size = 0; |
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return (0); /* no or unknown flash */ |
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} |
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#ifdef CONFIG_ADCIOP |
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value = addr2[0]; /* device ID */ |
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debug ("\ndev_code=%x\n", value); |
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#else |
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value = addr2[1]; /* device ID */ |
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#endif |
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DEBUGF("\nFLASH DEVICEID: %x\n", value); |
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switch (value) { |
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case (FLASH_WORD_SIZE)AMD_ID_LV040B: |
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info->flash_id += FLASH_AM040; |
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info->sector_count = 8; |
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info->size = 0x00080000; /* => 512 kb */ |
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break; |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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return (0); /* => no or unknown flash */ |
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} |
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/* set up sector start address table */ |
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if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || |
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(info->flash_id == FLASH_AM040) || |
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(info->flash_id == FLASH_AMD016)) { |
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for (i = 0; i < info->sector_count; i++) |
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info->start[i] = base + (i * 0x00010000); |
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} else { |
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if (info->flash_id & FLASH_BTYPE) { |
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/* set sector offsets for bottom boot block type */ |
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info->start[0] = base + 0x00000000; |
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info->start[1] = base + 0x00004000; |
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info->start[2] = base + 0x00006000; |
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info->start[3] = base + 0x00008000; |
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for (i = 4; i < info->sector_count; i++) { |
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info->start[i] = base + (i * 0x00010000) - 0x00030000; |
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} |
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} else { |
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/* set sector offsets for top boot block type */ |
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i = info->sector_count - 1; |
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info->start[i--] = base + info->size - 0x00004000; |
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info->start[i--] = base + info->size - 0x00006000; |
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info->start[i--] = base + info->size - 0x00008000; |
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for (; i >= 0; i--) { |
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info->start[i] = base + i * 0x00010000; |
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} |
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} |
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} |
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/* check for protected sectors */ |
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for (i = 0; i < info->sector_count; i++) { |
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/* read sector protection at sector address, (A7 .. A0) = 0x02 */ |
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/* D0 = 1 if protected */ |
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#ifdef CONFIG_ADCIOP |
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addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); |
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info->protect[i] = addr2[4] & 1; |
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#else |
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addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); |
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) |
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info->protect[i] = 0; |
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else |
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info->protect[i] = addr2[2] & 1; |
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#endif |
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} |
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/*
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* Prevent writes to uninitialized FLASH. |
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*/ |
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if (info->flash_id != FLASH_UNKNOWN) { |
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#if 0 /* test-only */
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#ifdef CONFIG_ADCIOP |
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addr2 = (volatile unsigned char *)info->start[0]; |
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addr2[ADDR0] = 0xAA; |
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addr2[ADDR1] = 0x55; |
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addr2[ADDR0] = 0xF0; /* reset bank */ |
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#else |
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addr2 = (FLASH_WORD_SIZE *)info->start[0]; |
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*addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ |
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#endif |
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#else /* test-only */ |
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addr2 = (FLASH_WORD_SIZE *)info->start[0]; |
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*addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ |
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#endif /* test-only */ |
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} |
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return (info->size); |
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} |
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int wait_for_DQ7(flash_info_t *info, int sect) |
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{ |
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ulong start, now, last; |
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volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); |
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start = get_timer (0); |
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last = start; |
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while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { |
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if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { |
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printf ("Timeout\n"); |
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return -1; |
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} |
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/* show that we're waiting */ |
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if ((now - last) > 1000) { /* every second */ |
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putc ('.'); |
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last = now; |
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} |
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} |
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return 0; |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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int flash_erase (flash_info_t *info, int s_first, int s_last) |
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{ |
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volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); |
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volatile FLASH_WORD_SIZE *addr2; |
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int flag, prot, sect, l_sect; |
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int i; |
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if ((s_first < 0) || (s_first > s_last)) { |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("- missing\n"); |
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} else { |
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printf ("- no sectors to erase\n"); |
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} |
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return 1; |
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} |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("Can't erase unknown flash type - aborted\n"); |
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return 1; |
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} |
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prot = 0; |
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for (sect=s_first; sect<=s_last; ++sect) { |
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if (info->protect[sect]) { |
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prot++; |
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} |
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} |
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if (prot) { |
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printf ("- Warning: %d protected sectors will not be erased!\n", |
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prot); |
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} else { |
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printf ("\n"); |
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} |
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l_sect = -1; |
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts(); |
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/* Start erase on unprotected sectors */ |
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for (sect = s_first; sect<=s_last; sect++) { |
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if (info->protect[sect] == 0) { /* not protected */ |
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addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); |
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printf("Erasing sector %p\n", addr2); |
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|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { |
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; |
||||
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; |
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; |
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; |
||||
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; |
||||
addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ |
||||
for (i=0; i<50; i++) |
||||
udelay(1000); /* wait 1 ms */ |
||||
} else { |
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; |
||||
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; |
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; |
||||
addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; |
||||
addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; |
||||
addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ |
||||
} |
||||
l_sect = sect; |
||||
/*
|
||||
* Wait for each sector to complete, it's more |
||||
* reliable. According to AMD Spec, you must |
||||
* issue all erase commands within a specified |
||||
* timeout. This has been seen to fail, especially |
||||
* if printf()s are included (for debug)!! |
||||
*/ |
||||
wait_for_DQ7(info, sect); |
||||
} |
||||
} |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
/* wait at least 80us - let's wait 1 ms */ |
||||
udelay (1000); |
||||
|
||||
#if 0 |
||||
/*
|
||||
* We wait for the last triggered sector |
||||
*/ |
||||
if (l_sect < 0) |
||||
goto DONE; |
||||
wait_for_DQ7(info, l_sect); |
||||
|
||||
DONE: |
||||
#endif |
||||
/* reset to read mode */ |
||||
addr = (FLASH_WORD_SIZE *)info->start[0]; |
||||
addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ |
||||
|
||||
printf (" done\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
||||
{ |
||||
ulong cp, wp, data; |
||||
int i, l, rc; |
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */ |
||||
|
||||
/*
|
||||
* handle unaligned start bytes |
||||
*/ |
||||
if ((l = addr - wp) != 0) { |
||||
data = 0; |
||||
for (i=0, cp=wp; i<l; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
for (; i<4 && cnt>0; ++i) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
++cp; |
||||
} |
||||
for (; cnt==0 && i<4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
} |
||||
|
||||
/*
|
||||
* handle word aligned part |
||||
*/ |
||||
while (cnt >= 4) { |
||||
data = 0; |
||||
for (i=0; i<4; ++i) { |
||||
data = (data << 8) | *src++; |
||||
} |
||||
if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
cnt -= 4; |
||||
} |
||||
|
||||
if (cnt == 0) { |
||||
return (0); |
||||
} |
||||
|
||||
/*
|
||||
* handle unaligned tail bytes |
||||
*/ |
||||
data = 0; |
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
} |
||||
for (; i<4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
return (write_word(info, wp, data)); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int write_word (flash_info_t * info, ulong dest, ulong data) |
||||
{ |
||||
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]); |
||||
volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; |
||||
volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; |
||||
ulong start; |
||||
int i; |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ((*((volatile FLASH_WORD_SIZE *) dest) & |
||||
(FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { |
||||
return (2); |
||||
} |
||||
|
||||
for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { |
||||
int flag; |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts (); |
||||
|
||||
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; |
||||
addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; |
||||
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; |
||||
|
||||
dest2[i] = data2[i]; |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts (); |
||||
|
||||
/* data polling for D7 */ |
||||
start = get_timer (0); |
||||
while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != |
||||
(data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { |
||||
|
||||
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { |
||||
return (1); |
||||
} |
||||
} |
||||
} |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
@ -0,0 +1,96 @@ |
||||
/* |
||||
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <ppc_asm.tmpl> |
||||
#include <config.h> |
||||
|
||||
/* General */ |
||||
#define TLB_VALID 0x00000200 |
||||
|
||||
/* Supported page sizes */ |
||||
|
||||
#define SZ_1K 0x00000000 |
||||
#define SZ_4K 0x00000010 |
||||
#define SZ_16K 0x00000020 |
||||
#define SZ_64K 0x00000030 |
||||
#define SZ_256K 0x00000040 |
||||
#define SZ_1M 0x00000050 |
||||
#define SZ_16M 0x00000070 |
||||
#define SZ_256M 0x00000090 |
||||
|
||||
/* Storage attributes */ |
||||
#define SA_W 0x00000800 /* Write-through */ |
||||
#define SA_I 0x00000400 /* Caching inhibited */ |
||||
#define SA_M 0x00000200 /* Memory coherence */ |
||||
#define SA_G 0x00000100 /* Guarded */ |
||||
#define SA_E 0x00000080 /* Endian */ |
||||
|
||||
/* Access control */ |
||||
#define AC_X 0x00000024 /* Execute */ |
||||
#define AC_W 0x00000012 /* Write */ |
||||
#define AC_R 0x00000009 /* Read */ |
||||
|
||||
/* Some handy macros */ |
||||
|
||||
#define EPN(e) ((e) & 0xfffffc00) |
||||
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) |
||||
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) |
||||
#define TLB2(a) ( (a)&0x00000fbf ) |
||||
|
||||
#define tlbtab_start\ |
||||
mflr r1 ;\
|
||||
bl 0f ;
|
||||
|
||||
#define tlbtab_end\ |
||||
.long 0, 0, 0 ; \
|
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
#define tlbentry(epn,sz,rpn,erpn,attr)\ |
||||
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) |
||||
|
||||
|
||||
/************************************************************************** |
||||
* TLB TABLE |
||||
* |
||||
* This table is used by the cpu boot code to setup the initial tlb |
||||
* entries. Rather than make broad assumptions in the cpu source tree, |
||||
* this table lets each board set things up however they like. |
||||
* |
||||
* Pointer to the table is returned in r1 |
||||
* |
||||
*************************************************************************/ |
||||
|
||||
.section .bootpg,"ax" |
||||
.globl tlbtab
|
||||
|
||||
tlbtab: |
||||
tlbtab_start |
||||
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) |
||||
tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) |
||||
tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) |
||||
tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) |
||||
tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) |
||||
tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) |
||||
tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) |
||||
tlbtab_end |
@ -0,0 +1,155 @@ |
||||
/* |
||||
* (C) Copyright 2002-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
.resetvec 0xFFFFFFFC : |
||||
{ |
||||
*(.resetvec) |
||||
} = 0xffff |
||||
|
||||
.bootpg 0xFFFFF000 : |
||||
{ |
||||
cpu/ppc4xx/start.o (.bootpg) |
||||
} = 0xffff |
||||
|
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/ppc4xx/start.o (.text) |
||||
board/xpedite1k/init.o (.text) |
||||
cpu/ppc4xx/kgdb.o (.text) |
||||
cpu/ppc4xx/traps.o (.text) |
||||
cpu/ppc4xx/interrupts.o (.text) |
||||
cpu/ppc4xx/serial.o (.text) |
||||
cpu/ppc4xx/cpu_init.o (.text) |
||||
cpu/ppc4xx/speed.o (.text) |
||||
cpu/ppc4xx/405gp_enet.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
lib_ppc/extable.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
|
||||
/* . = env_offset;*/ |
||||
/* common/environment.o(.text)*/ |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -0,0 +1,144 @@ |
||||
/* |
||||
* (C) Copyright 2002-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/ppc4xx/start.o (.text) |
||||
board/xpedite1k/init.o (.text) |
||||
cpu/ppc4xx/kgdb.o (.text) |
||||
cpu/ppc4xx/traps.o (.text) |
||||
cpu/ppc4xx/interrupts.o (.text) |
||||
cpu/ppc4xx/serial.o (.text) |
||||
cpu/ppc4xx/cpu_init.o (.text) |
||||
cpu/ppc4xx/speed.o (.text) |
||||
cpu/ppc4xx/405gp_enet.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
lib_ppc/extable.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
|
||||
/* common/environment.o(.text) */ |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -0,0 +1,358 @@ |
||||
/*
|
||||
* Copyright (C) 2003 Travis B. Sawyer <travis.sawyer@sandburst.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
|
||||
#include <common.h> |
||||
#include <asm/processor.h> |
||||
#include <spd_sdram.h> |
||||
#include <i2c.h> |
||||
|
||||
#define BOOT_SMALL_FLASH 32 /* 00100000 */ |
||||
#define FLASH_ONBD_N 2 /* 00000010 */ |
||||
#define FLASH_SRAM_SEL 1 /* 00000001 */ |
||||
|
||||
long int fixed_sdram (void); |
||||
|
||||
int board_pre_init (void) |
||||
{ |
||||
unsigned long sdrreg; |
||||
/* TBS: Setup the GPIO access for the user LEDs */ |
||||
mfsdr(sdr_pfc0, sdrreg); |
||||
mtsdr(sdr_pfc0, (sdrreg & ~0x00000100) | 0x00000E00); |
||||
out32(CFG_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3)); |
||||
LED0_OFF(); |
||||
LED1_OFF(); |
||||
LED2_OFF(); |
||||
LED3_OFF(); |
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the external bus controller/chip selects |
||||
*-------------------------------------------------------------------*/ |
||||
|
||||
/* set the bus controller */ |
||||
mtebc (pb0ap, 0x04055200); /* FLASH/SRAM */ |
||||
mtebc (pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */ |
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the interrupt controller polarities, triggers, etc. |
||||
*-------------------------------------------------------------------*/ |
||||
mtdcr (uic0sr, 0xffffffff); /* clear all */ |
||||
mtdcr (uic0er, 0x00000000); /* disable all */ |
||||
mtdcr (uic0cr, 0x00000003); /* SMI & UIC1 crit are critical */ |
||||
mtdcr (uic0pr, 0xfffffe00); /* per ref-board manual */ |
||||
mtdcr (uic0tr, 0x01c00000); /* per ref-board manual */ |
||||
mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ |
||||
mtdcr (uic0sr, 0xffffffff); /* clear all */ |
||||
|
||||
mtdcr (uic1sr, 0xffffffff); /* clear all */ |
||||
mtdcr (uic1er, 0x00000000); /* disable all */ |
||||
mtdcr (uic1cr, 0x00000000); /* all non-critical */ |
||||
mtdcr (uic1pr, 0xffffc0ff); /* per ref-board manual */ |
||||
mtdcr (uic1tr, 0x00ff8000); /* per ref-board manual */ |
||||
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ |
||||
mtdcr (uic1sr, 0xffffffff); /* clear all */ |
||||
|
||||
mtdcr (uic2sr, 0xffffffff); /* clear all */ |
||||
mtdcr (uic2er, 0x00000000); /* disable all */ |
||||
mtdcr (uic2cr, 0x00000000); /* all non-critical */ |
||||
mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */ |
||||
mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */ |
||||
mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ |
||||
mtdcr (uic2sr, 0xffffffff); /* clear all */ |
||||
|
||||
mtdcr (uicb0sr, 0xfc000000); /* clear all */ |
||||
mtdcr (uicb0er, 0x00000000); /* disable all */ |
||||
mtdcr (uicb0cr, 0x00000000); /* all non-critical */ |
||||
mtdcr (uicb0pr, 0xfc000000); /* */ |
||||
mtdcr (uicb0tr, 0x00000000); /* */ |
||||
mtdcr (uicb0vr, 0x00000001); /* */ |
||||
|
||||
LED0_ON(); |
||||
|
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int checkboard (void) |
||||
{ |
||||
sys_info_t sysinfo; |
||||
get_sys_info (&sysinfo); |
||||
|
||||
printf ("Board: XES XPedite1000 440GX\n"); |
||||
printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000); |
||||
printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); |
||||
printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000); |
||||
printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000); |
||||
printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
|
||||
long int initdram (int board_type) |
||||
{ |
||||
long dram_size = 0; |
||||
|
||||
#if defined(CONFIG_SPD_EEPROM) |
||||
dram_size = spd_sdram (0); |
||||
#else |
||||
dram_size = fixed_sdram (); |
||||
#endif |
||||
return dram_size; |
||||
} |
||||
|
||||
|
||||
#if defined(CFG_DRAM_TEST) |
||||
int testdram (void) |
||||
{ |
||||
uint *pstart = (uint *) 0x00000000; |
||||
uint *pend = (uint *) 0x08000000; |
||||
uint *p; |
||||
|
||||
for (p = pstart; p < pend; p++) |
||||
*p = 0xaaaaaaaa; |
||||
|
||||
for (p = pstart; p < pend; p++) { |
||||
if (*p != 0xaaaaaaaa) { |
||||
printf ("SDRAM test fails at: %08x\n", (uint) p); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
for (p = pstart; p < pend; p++) |
||||
*p = 0x55555555; |
||||
|
||||
for (p = pstart; p < pend; p++) { |
||||
if (*p != 0x55555555) { |
||||
printf ("SDRAM test fails at: %08x\n", (uint) p); |
||||
return 1; |
||||
} |
||||
} |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
/*************************************************************************
|
||||
* fixed sdram init -- doesn't use serial presence detect. |
||||
* |
||||
* Assumes: 128 MB, non-ECC, non-registered |
||||
* PLB @ 133 MHz |
||||
* |
||||
************************************************************************/ |
||||
long int fixed_sdram (void) |
||||
{ |
||||
uint reg; |
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup some default |
||||
*------------------------------------------------------------------*/ |
||||
mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */ |
||||
mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ |
||||
mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ |
||||
mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ |
||||
mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ |
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup for board-specific specific mem |
||||
*------------------------------------------------------------------*/ |
||||
/*
|
||||
* Following for CAS Latency = 2.5 @ 133 MHz PLB |
||||
*/ |
||||
mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ |
||||
mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ |
||||
/* RA=10 RD=3 */ |
||||
mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ |
||||
mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ |
||||
mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ |
||||
udelay (400); /* Delay 200 usecs (min) */ |
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Enable the controller, then wait for DCEN to complete |
||||
*------------------------------------------------------------------*/ |
||||
mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ |
||||
for (;;) { |
||||
mfsdram (mem_mcsts, reg); |
||||
if (reg & 0x80000000) |
||||
break; |
||||
} |
||||
|
||||
return (128 * 1024 * 1024); /* 128 MB */ |
||||
} |
||||
#endif /* !defined(CONFIG_SPD_EEPROM) */ |
||||
|
||||
|
||||
/*************************************************************************
|
||||
* pci_pre_init |
||||
* |
||||
* This routine is called just prior to registering the hose and gives |
||||
* the board the opportunity to check things. Returning a value of zero |
||||
* indicates that things are bad & PCI initialization should be aborted. |
||||
* |
||||
* Different boards may wish to customize the pci controller structure |
||||
* (add regions, override default access routines, etc) or perform |
||||
* certain pre-initialization actions. |
||||
* |
||||
************************************************************************/ |
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) |
||||
int pci_pre_init(struct pci_controller * hose ) |
||||
{ |
||||
unsigned long strap; |
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* TBS: |
||||
* The xpedite1k is a PrPMC board, however for our purposes it is the host |
||||
*--------------------------------------------------------------------------*/ |
||||
strap = mfdcr(cpc0_strp1); |
||||
if( (strap & 0x00100000) == 0 ){ |
||||
printf("PCI: CPC0_STRP1[PAE] not set.\n"); |
||||
return 0; |
||||
} |
||||
|
||||
return 1; |
||||
} |
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ |
||||
|
||||
/*************************************************************************
|
||||
* pci_target_init |
||||
* |
||||
* The bootstrap configuration provides default settings for the pci |
||||
* inbound map (PIM). But the bootstrap config choices are limited and |
||||
* may not be sufficient for a given board. |
||||
* |
||||
************************************************************************/ |
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) |
||||
void pci_target_init(struct pci_controller * hose ) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Disable everything |
||||
*--------------------------------------------------------------------------*/ |
||||
out32r( PCIX0_PIM0SA, 0 ); /* disable */ |
||||
out32r( PCIX0_PIM1SA, 0 ); /* disable */ |
||||
out32r( PCIX0_PIM2SA, 0 ); /* disable */ |
||||
out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ |
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping |
||||
* options to not support sizes such as 128/256 MB. |
||||
*--------------------------------------------------------------------------*/ |
||||
out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); |
||||
out32r( PCIX0_PIM0LAH, 0 ); |
||||
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); |
||||
|
||||
out32r( PCIX0_BAR0, 0 ); |
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Program the board's subsystem id/vendor id |
||||
*--------------------------------------------------------------------------*/ |
||||
out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); |
||||
out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); |
||||
|
||||
out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); |
||||
} |
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ |
||||
|
||||
|
||||
/*************************************************************************
|
||||
* is_pci_host |
||||
* |
||||
* This routine is called to determine if a pci scan should be |
||||
* performed. With various hardware environments (especially cPCI and |
||||
* PPMC) it's insufficient to depend on the state of the arbiter enable |
||||
* bit in the strap register, or generic host/adapter assumptions. |
||||
* |
||||
* Rather than hard-code a bad assumption in the general 440 code, the |
||||
* 440 pci code requires the board to decide at runtime. |
||||
* |
||||
* Return 0 for adapter mode, non-zero for host (monarch) mode. |
||||
* |
||||
* |
||||
************************************************************************/ |
||||
#if defined(CONFIG_PCI) |
||||
int is_pci_host(struct pci_controller *hose) |
||||
{ |
||||
/* The ebony board is always configured as host. */ |
||||
/* TBS: The xpedite1k is not necessarily the host, however for our purposes, it is. */ |
||||
return(1); |
||||
} |
||||
#endif /* defined(CONFIG_PCI) */ |
||||
|
||||
#ifdef CONFIG_POST |
||||
/*
|
||||
* Returns 1 if keys pressed to start the power-on long-running tests |
||||
* Called from board_init_f(). |
||||
*/ |
||||
int post_hotkeys_pressed(void) |
||||
{ |
||||
|
||||
return (ctrlc()); |
||||
} |
||||
|
||||
void post_word_store (ulong a) |
||||
{ |
||||
volatile ulong *save_addr = |
||||
(volatile ulong *)(CFG_POST_WORD_ADDR); |
||||
|
||||
*save_addr = a; |
||||
} |
||||
|
||||
ulong post_word_load (void) |
||||
{ |
||||
volatile ulong *save_addr = |
||||
(volatile ulong *)(CFG_POST_WORD_ADDR); |
||||
|
||||
return *save_addr; |
||||
} |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* board_get_enetaddr -- Read the MAC Addresses in the I2C EEPROM |
||||
*----------------------------------------------------------------------------- |
||||
*/ |
||||
static int enetaddr_num = 0; |
||||
void board_get_enetaddr (uchar * enet) |
||||
{ |
||||
int i; |
||||
unsigned char buff[0x100], *cp; |
||||
|
||||
/* Initialize I2C */ |
||||
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); |
||||
|
||||
/* Read 256 bytes in EEPROM */ |
||||
i2c_read (0x50, 0, 1, buff, 0x100); |
||||
|
||||
if (enetaddr_num == 0) { |
||||
cp = &buff[0xF4]; |
||||
enetaddr_num = 1; |
||||
} |
||||
else |
||||
cp = &buff[0xFA]; |
||||
|
||||
for (i = 0; i < 6; i++,cp++) |
||||
enet[i] = *cp; |
||||
|
||||
printf ("MAC address = %02x:%02x:%02x:%02x:%02x:%02x\n", |
||||
enet[0], enet[1], enet[2], enet[3], enet[4], enet[5]); |
||||
|
||||
} |
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,259 @@ |
||||
/*-----------------------------------------------------------------------------+
|
||||
| |
||||
| This source code has been made available to you by IBM on an AS-IS |
||||
| basis. Anyone receiving this source is licensed under IBM |
||||
| copyrights to use it in any way he or she deems fit, including |
||||
| copying it, modifying it, compiling it, and redistributing it either |
||||
| with or without modifications. No license under IBM patents or |
||||
| patent applications is to be implied by the copyright license. |
||||
| |
||||
| Any user of this software should understand that IBM cannot provide |
||||
| technical support for this software and will not be responsible for |
||||
| any consequences resulting from the use of this software. |
||||
| |
||||
| Any person who transfers this source code or any derivative work |
||||
| must include the IBM copyright notice, this paragraph, and the |
||||
| preceding two paragraphs in the transferred software. |
||||
| |
||||
| COPYRIGHT I B M CORPORATION 1995 |
||||
| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M |
||||
+-----------------------------------------------------------------------------*/ |
||||
/*-----------------------------------------------------------------------------+
|
||||
| |
||||
| File Name: miiphy.c |
||||
| |
||||
| Function: This module has utilities for accessing the MII PHY through |
||||
| the EMAC3 macro. |
||||
| |
||||
| Author: Mark Wisner |
||||
| |
||||
| Change Activity- |
||||
| |
||||
| Date Description of Change BY |
||||
| --------- --------------------- --- |
||||
| 05-May-99 Created MKW |
||||
| 01-Jul-99 Changed clock setting of sta_reg from 66Mhz to 50Mhz to |
||||
| better match OPB speed. Also modified delay times. JWB |
||||
| 29-Jul-99 Added Full duplex support MKW |
||||
| 24-Aug-99 Removed printf from dp83843_duplex() JWB |
||||
| 19-Jul-00 Ported to esd cpci405 sr |
||||
| 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS |
||||
| <travis.sawyer@sandburst.com> |
||||
| |
||||
+-----------------------------------------------------------------------------*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/processor.h> |
||||
#include <ppc_asm.tmpl> |
||||
#include <commproc.h> |
||||
#include <440gx_enet.h> |
||||
#include <405_mal.h> |
||||
#include <miiphy.h> |
||||
|
||||
#if defined(CONFIG_440) && defined(CONFIG_NET_MULTI) |
||||
|
||||
|
||||
/***********************************************************/ |
||||
/* Dump out to the screen PHY regs */ |
||||
/***********************************************************/ |
||||
|
||||
void miiphy_dump (unsigned char addr) |
||||
{ |
||||
unsigned long i; |
||||
unsigned short data; |
||||
|
||||
|
||||
for (i = 0; i < 0x1A; i++) { |
||||
if (miiphy_read (addr, i, &data)) { |
||||
printf ("read error for reg %lx\n", i); |
||||
return; |
||||
} |
||||
printf ("Phy reg %lx ==> %4x\n", i, data); |
||||
|
||||
/* jump to the next set of regs */ |
||||
if (i == 0x07) |
||||
i = 0x0f; |
||||
|
||||
} /* end for loop */ |
||||
} /* end dump */ |
||||
|
||||
|
||||
/***********************************************************/ |
||||
/* (Re)start autonegotiation */ |
||||
/***********************************************************/ |
||||
int phy_setup_aneg (unsigned char addr) |
||||
{ |
||||
unsigned short ctl, adv; |
||||
|
||||
/* Setup standard advertise */ |
||||
miiphy_read (addr, PHY_ANAR, &adv); |
||||
adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 | |
||||
PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD | |
||||
PHY_ANLPAR_10); |
||||
miiphy_write (addr, PHY_ANAR, adv); |
||||
|
||||
/* Start/Restart aneg */ |
||||
miiphy_read (addr, PHY_BMCR, &ctl); |
||||
ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); |
||||
miiphy_write (addr, PHY_BMCR, ctl); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
|
||||
/***********************************************************/ |
||||
/* read a phy reg and return the value with a rc */ |
||||
/***********************************************************/ |
||||
unsigned int miiphy_getemac_offset (void) |
||||
{ |
||||
unsigned long zmii; |
||||
unsigned long eoffset; |
||||
|
||||
/* Need to find out which mdi port we're using */ |
||||
zmii = in32 (ZMII_FER); |
||||
|
||||
if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) { |
||||
/* using port 0 */ |
||||
eoffset = 0; |
||||
} else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1))) { |
||||
/* using port 1 */ |
||||
eoffset = 0x100; |
||||
} else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2))) { |
||||
/* using port 2 */ |
||||
eoffset = 0x400; |
||||
} else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3))) { |
||||
/* using port 3 */ |
||||
eoffset = 0x600; |
||||
} else { |
||||
/* None of the mdi ports are enabled! */ |
||||
/* enable port 0 */ |
||||
zmii |= ZMII_FER_MDI << ZMII_FER_V (0); |
||||
out32 (ZMII_FER, zmii); |
||||
eoffset = 0; |
||||
/* need to soft reset port 0 */ |
||||
zmii = in32 (EMAC_M0); |
||||
zmii |= EMAC_M0_SRST; |
||||
out32 (EMAC_M0, zmii); |
||||
} |
||||
|
||||
return (eoffset); |
||||
|
||||
} |
||||
|
||||
|
||||
int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value) |
||||
{ |
||||
unsigned long sta_reg; /* STA scratch area */ |
||||
unsigned long i; |
||||
unsigned long emac_reg; |
||||
|
||||
|
||||
emac_reg = miiphy_getemac_offset (); |
||||
/* see if it is ready for 1000 nsec */ |
||||
i = 0; |
||||
|
||||
/* see if it is ready for sec */ |
||||
while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) { |
||||
udelay (7); |
||||
if (i > 5) { |
||||
#if 0 |
||||
printf ("read err 1\n"); |
||||
#endif |
||||
return -1; |
||||
} |
||||
i++; |
||||
} |
||||
sta_reg = reg; /* reg address */ |
||||
/* set clock (50Mhz) and read flags */ |
||||
#if defined(CONFIG_440_GX) |
||||
sta_reg |= EMAC_STACR_READ; |
||||
#else |
||||
sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ; |
||||
#endif |
||||
|
||||
#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440_GX) |
||||
sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; |
||||
#endif |
||||
sta_reg = sta_reg | (addr << 5); /* Phy address */ |
||||
|
||||
out32 (EMAC_STACR + emac_reg, sta_reg); |
||||
#if 0 /* test-only */
|
||||
printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ |
||||
#endif |
||||
|
||||
sta_reg = in32 (EMAC_STACR + emac_reg); |
||||
i = 0; |
||||
while ((sta_reg & EMAC_STACR_OC) == 0) { |
||||
udelay (7); |
||||
if (i > 5) { |
||||
return -1; |
||||
} |
||||
i++; |
||||
sta_reg = in32 (EMAC_STACR + emac_reg); |
||||
} |
||||
if ((sta_reg & EMAC_STACR_PHYE) != 0) { |
||||
return -1; |
||||
} |
||||
|
||||
*value = *(short *) (&sta_reg); |
||||
return 0; |
||||
|
||||
|
||||
} /* phy_read */ |
||||
|
||||
|
||||
/***********************************************************/ |
||||
/* write a phy reg and return the value with a rc */ |
||||
/***********************************************************/ |
||||
|
||||
int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value) |
||||
{ |
||||
unsigned long sta_reg; /* STA scratch area */ |
||||
unsigned long i; |
||||
unsigned long emac_reg; |
||||
|
||||
emac_reg = miiphy_getemac_offset (); |
||||
/* see if it is ready for 1000 nsec */ |
||||
i = 0; |
||||
|
||||
while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == 0) { |
||||
if (i > 5) |
||||
return -1; |
||||
udelay (7); |
||||
i++; |
||||
} |
||||
sta_reg = 0; |
||||
sta_reg = reg; /* reg address */ |
||||
/* set clock (50Mhz) and read flags */ |
||||
#if defined(CONFIG_440_GX) |
||||
sta_reg |= EMAC_STACR_WRITE; |
||||
#else |
||||
sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ; |
||||
#endif |
||||
|
||||
#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440_GX) |
||||
sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */ |
||||
#endif |
||||
sta_reg = sta_reg | ((unsigned long) addr << 5); /* Phy address */ |
||||
memcpy (&sta_reg, &value, 2); /* put in data */ |
||||
|
||||
out32 (EMAC_STACR + emac_reg, sta_reg); |
||||
|
||||
/* wait for completion */ |
||||
i = 0; |
||||
sta_reg = in32 (EMAC_STACR + emac_reg); |
||||
while ((sta_reg & EMAC_STACR_OC) == 0) { |
||||
udelay (7); |
||||
if (i > 5) |
||||
return -1; |
||||
i++; |
||||
sta_reg = in32 (EMAC_STACR + emac_reg); |
||||
} |
||||
|
||||
if ((sta_reg & EMAC_STACR_PHYE) != 0) |
||||
return -1; |
||||
return 0; |
||||
|
||||
} /* phy_write */ |
||||
|
||||
#endif /* CONFIG_405GP */ |
@ -0,0 +1,82 @@ |
||||
XES XPedite1000 Board |
||||
|
||||
Last Update: December 29, 2003 |
||||
======================================================================= |
||||
|
||||
This file contains some handy info regarding U-Boot and the XES |
||||
XPedite1000 PPC440GX PrPMC board. See the README.ppc440 for additional |
||||
information. |
||||
|
||||
|
||||
SWITCH SETTINGS & JUMPERS |
||||
========================== |
||||
|
||||
Jumpers selected for AMD29LV040B flash part as the boot flash. |
||||
|
||||
|
||||
I2C Strap EEPROM & Environment Settings |
||||
======================================= |
||||
|
||||
The XPedite1000 uses a single I2C eeprom for the 440 strappings and for |
||||
the environment variables. The first page (256 bytes) contains the |
||||
strappings and the 2 EMAC HW Ethernet addresses. Be careful not to |
||||
change the 1st page of the EEPROM! Unpopulated jumper J560 can get you |
||||
out of trouble as it disables the strapping read from EEPROM. |
||||
|
||||
I2C iprobe |
||||
===================== |
||||
|
||||
The i2c utilities work and have been tested on Rev B. of the 440GX. See |
||||
README.ebony for more information about i2c probing with the 440. |
||||
|
||||
|
||||
GETTING OUT OF I2C TROUBLE |
||||
=========================== |
||||
|
||||
(Direct quote from README.ebony) |
||||
If you're like me ... you may have screwed up your bootstrap serial |
||||
eeprom ... or worse, your SPD eeprom when experimenting with the |
||||
i2c commands. If so, here are some ideas on how to get out of |
||||
trouble: |
||||
|
||||
Serial bootstrap eeprom corruption: |
||||
----------------------------------- |
||||
Power down the board and set the following straps: |
||||
|
||||
J560 - closed |
||||
|
||||
This will select the default sys0 and sys1 settings (the serial |
||||
eeproms are not used). Then power up the board and fix the serial |
||||
eeprom using the imm command. Here are the values I currently |
||||
use: |
||||
|
||||
=> imd 50 0 10 |
||||
|
||||
0000: 85 7d 42 06 07 80 11 00 00 00 00 00 00 00 00 00 .}B............. |
||||
|
||||
Once you have the eeproms set correctly change the |
||||
J560 straps as you desire. |
||||
|
||||
|
||||
PPC440GX Ethernet EMACs |
||||
======================= |
||||
|
||||
The XES XPedite1000 uses emac 2 & 3 and ignores emac 0 & 1. PHYs are connected |
||||
only to emac 2 & 3. The HW Ethernet addresses are read from the i2c eeprom and |
||||
placed in the bd info structure for enet2addr and enet3addr. The ethernet driver |
||||
senses that enetaddr and enet1addr are 0's and does not use them. |
||||
|
||||
As of this writing gigabit ethernet and the TCPIP acceleration hardware is not |
||||
supported. |
||||
|
||||
|
||||
Flash Support |
||||
============= |
||||
|
||||
As of this writing, there is support for the 1/2mb boot flash only. User flash |
||||
is not yet supported. |
||||
|
||||
|
||||
Regards, |
||||
--Travis |
||||
<travis.sawyer@sandburst.com> |
@ -0,0 +1,440 @@ |
||||
/*----------------------------------------------------------------------------+
|
||||
| |
||||
| This source code has been made available to you by IBM on an AS-IS |
||||
| basis. Anyone receiving this source is licensed under IBM |
||||
| copyrights to use it in any way he or she deems fit, including |
||||
| copying it, modifying it, compiling it, and redistributing it either |
||||
| with or without modifications. No license under IBM patents or |
||||
| patent applications is to be implied by the copyright license. |
||||
| |
||||
| Any user of this software should understand that IBM cannot provide |
||||
| technical support for this software and will not be responsible for |
||||
| any consequences resulting from the use of this software. |
||||
| |
||||
| Any person who transfers this source code or any derivative work |
||||
| must include the IBM copyright notice, this paragraph, and the |
||||
| preceding two paragraphs in the transferred software. |
||||
| |
||||
| COPYRIGHT I B M CORPORATION 1999 |
||||
| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M |
||||
+----------------------------------------------------------------------------*/ |
||||
/*----------------------------------------------------------------------------+
|
||||
| |
||||
| File Name: enetemac.h |
||||
| |
||||
| Function: Header file for the EMAC3 macro on the 405GP. |
||||
| |
||||
| Author: Mark Wisner |
||||
| |
||||
| Change Activity- |
||||
| |
||||
| Date Description of Change BY |
||||
| --------- --------------------- --- |
||||
| 29-Apr-99 Created MKW |
||||
| |
||||
+----------------------------------------------------------------------------*/ |
||||
/*----------------------------------------------------------------------------+
|
||||
| 19-Nov-03 Travis Sawyer, Sandburst Corporation, tsawyer@sandburst.com |
||||
| ported to handle 440GP and 440GX multiple EMACs |
||||
+----------------------------------------------------------------------------*/ |
||||
|
||||
#ifndef _emacgx_enet_h_ |
||||
#define _emacgx_enet_h_ |
||||
|
||||
#if defined(CONFIG_440) |
||||
#include <net.h> |
||||
#include "405_mal.h" |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------+
|
||||
| General enternet defines. 802 frames are not supported. |
||||
+-----------------------------------------------------------------------------*/ |
||||
#define ENET_ADDR_LENGTH 6 |
||||
#define ENET_ARPTYPE 0x806 |
||||
#define ARP_REQUEST 1 |
||||
#define ARP_REPLY 2 |
||||
#define ENET_IPTYPE 0x800 |
||||
#define ARP_CACHE_SIZE 5 |
||||
|
||||
#define NUM_TX_BUFF 1 |
||||
#define NUM_RX_BUFF PKTBUFSRX |
||||
|
||||
struct enet_frame { |
||||
unsigned char dest_addr[ENET_ADDR_LENGTH]; |
||||
unsigned char source_addr[ENET_ADDR_LENGTH]; |
||||
unsigned short type; |
||||
unsigned char enet_data[1]; |
||||
}; |
||||
|
||||
struct arp_entry { |
||||
unsigned long inet_address; |
||||
unsigned char mac_address[ENET_ADDR_LENGTH]; |
||||
unsigned long valid; |
||||
unsigned long sec; |
||||
unsigned long nsec; |
||||
}; |
||||
|
||||
|
||||
/* Statistic Areas */ |
||||
#define MAX_ERR_LOG 10 |
||||
|
||||
typedef struct emac_stats_st{ /* Statistic Block */ |
||||
int data_len_err; |
||||
int rx_frames; |
||||
int rx; |
||||
int rx_prot_err; |
||||
int int_err; |
||||
int pkts_tx; |
||||
int pkts_rx; |
||||
int pkts_handled; |
||||
short tx_err_log[MAX_ERR_LOG]; |
||||
short rx_err_log[MAX_ERR_LOG]; |
||||
} EMAC_STATS_ST, *EMAC_STATS_PST; |
||||
|
||||
/* Structure containing variables used by the shared code (440gx_enet.c) */ |
||||
typedef struct emac_440gx_hw_st { |
||||
uint32_t hw_addr; /* EMAC offset */ |
||||
uint32_t tah_addr; /* TAH offset */ |
||||
uint32_t phy_id; |
||||
uint32_t phy_addr; |
||||
uint32_t original_fc; |
||||
uint32_t txcw; |
||||
uint32_t autoneg_failed; |
||||
uint32_t emac_ier; |
||||
volatile mal_desc_t *tx; |
||||
volatile mal_desc_t *rx; |
||||
bd_t *bis; /* for eth_init upon mal error */ |
||||
mal_desc_t *alloc_tx_buf; |
||||
mal_desc_t *alloc_rx_buf; |
||||
char *txbuf_ptr; |
||||
uint16_t devnum; |
||||
int get_link_status; |
||||
int tbi_compatibility_en; |
||||
int tbi_compatibility_on; |
||||
int fc_send_xon; |
||||
int report_tx_early; |
||||
int first_init; |
||||
int tx_err_index; |
||||
int rx_err_index; |
||||
int rx_slot; /* MAL Receive Slot */ |
||||
int rx_i_index; /* Receive Interrupt Queue Index */ |
||||
int rx_u_index; /* Receive User Queue Index */ |
||||
int tx_slot; /* MAL Transmit Slot */ |
||||
int tx_i_index; /* Transmit Interrupt Queue Index */ |
||||
int tx_u_index; /* Transmit User Queue Index */ |
||||
int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */ |
||||
int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */ |
||||
int is_receiving; /* sync with eth interrupt */ |
||||
int print_speed; /* print speed message upon start */ |
||||
EMAC_STATS_ST stats; |
||||
} EMAC_440GX_HW_ST, *EMAC_440GX_HW_PST; |
||||
|
||||
|
||||
#if defined(CONFIG_440_GX) |
||||
#define EMAC_NUM_DEV 4 |
||||
#elif defined(CONFIG_440) && !defined(CONFIG_440_GX) |
||||
#define EMAC_NUM_DEV 2 |
||||
#else |
||||
#warning Bad configuration |
||||
#endif |
||||
|
||||
|
||||
/*ZMII Bridge Register addresses */ |
||||
#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780) |
||||
#define ZMII_FER (ZMII_BASE) |
||||
#define ZMII_SSR (ZMII_BASE + 4) |
||||
#define ZMII_SMIISR (ZMII_BASE + 8) |
||||
|
||||
#define ZMII_RMII 0x22000000 |
||||
#define ZMII_MDI0 0x80000000 |
||||
|
||||
/* ZMII FER Register Bit Definitions */ |
||||
#define ZMII_FER_MDI (0x8) |
||||
#define ZMII_FER_SMII (0x4) |
||||
#define ZMII_FER_RMII (0x2) |
||||
#define ZMII_FER_MII (0x1) |
||||
|
||||
#define ZMII_FER_RSVD11 (0x00200000) |
||||
#define ZMII_FER_RSVD10 (0x00100000) |
||||
#define ZMII_FER_RSVD14_31 (0x0003FFFF) |
||||
|
||||
#define ZMII_FER_V(__x) (((3 - __x) * 4) + 16) |
||||
|
||||
|
||||
/* ZMII Speed Selection Register Bit Definitions */ |
||||
#define ZMII_SSR_SCI (0x4) |
||||
#define ZMII_SSR_FSS (0x2) |
||||
#define ZMII_SSR_SP (0x1) |
||||
#define ZMII_SSR_RSVD16_31 (0x0000FFFF) |
||||
|
||||
#define ZMII_SSR_V(__x) (((3 - __x) * 4) + 16) |
||||
|
||||
|
||||
/* ZMII SMII Status Register Bit Definitions */ |
||||
#define ZMII_SMIISR_E1 (0x80) |
||||
#define ZMII_SMIISR_EC (0x40) |
||||
#define ZMII_SMIISR_EN (0x20) |
||||
#define ZMII_SMIISR_EJ (0x10) |
||||
#define ZMII_SMIISR_EL (0x08) |
||||
#define ZMII_SMIISR_ED (0x04) |
||||
#define ZMII_SMIISR_ES (0x02) |
||||
#define ZMII_SMIISR_EF (0x01) |
||||
|
||||
#define ZMII_SMIISR_V(__x) ((3 - __x) * 8) |
||||
|
||||
/* RGMII Register Addresses */ |
||||
#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x0790) |
||||
#define RGMII_FER (RGMII_BASE + 0x00) |
||||
#define RGMII_SSR (RGMII_BASE + 0x04) |
||||
|
||||
/* RGMII Function Enable (FER) Register Bit Definitions */ |
||||
/* Note: for EMAC 2 and 3 only, 440GX only */ |
||||
#define RGMII_FER_DIS (0x00) |
||||
#define RGMII_FER_RTBI (0x04) |
||||
#define RGMII_FER_RGMII (0x05) |
||||
#define RGMII_FER_TBI (0x06) |
||||
#define RGMII_FER_GMII (0x07) |
||||
|
||||
#define RGMII_FER_V(__x) ((__x - 2) * 4) |
||||
|
||||
/* RGMII Speed Selection Register Bit Definitions */ |
||||
#define RGMII_SSR_SP_10MBPS (0x00) |
||||
#define RGMII_SSR_SP_100MBPS (0x02) |
||||
#define RGMII_SSR_SP_1000MBPS (0x04) |
||||
|
||||
#define RGMII_SSR_V(__x) ((__x -2) * 8) |
||||
|
||||
|
||||
/*---------------------------------------------------------------------------+
|
||||
| TCP/IP Acceleration Hardware (TAH) 440GX Only |
||||
+---------------------------------------------------------------------------*/ |
||||
#if defined(CONFIG_440_GX) |
||||
#define TAH_BASE (CFG_PERIPHERAL_BASE + 0x0B50) |
||||
#define TAH_REVID (TAH_BASE + 0x0) /* Revision ID (RO)*/ |
||||
#define TAH_MR (TAH_BASE + 0x10) /* Mode Register (R/W) */ |
||||
#define TAH_SSR0 (TAH_BASE + 0x14) /* Segment Size Reg 0 (R/W) */ |
||||
#define TAH_SSR1 (TAH_BASE + 0x18) /* Segment Size Reg 1 (R/W) */ |
||||
#define TAH_SSR2 (TAH_BASE + 0x1C) /* Segment Size Reg 2 (R/W) */ |
||||
#define TAH_SSR3 (TAH_BASE + 0x20) /* Segment Size Reg 3 (R/W) */ |
||||
#define TAH_SSR4 (TAH_BASE + 0x24) /* Segment Size Reg 4 (R/W) */ |
||||
#define TAH_SSR5 (TAH_BASE + 0x28) /* Segment Size Reg 5 (R/W) */ |
||||
#define TAH_TSR (TAH_BASE + 0x2C) /* Transmit Status Register (RO) */ |
||||
|
||||
|
||||
/* TAH Revision */ |
||||
#define TAH_REV_RN_M (0x000FFF00) /* Revision Number */ |
||||
#define TAH_REV_BN_M (0x000000FF) /* Branch Revision Number */ |
||||
|
||||
#define TAH_REV_RN_V (8) |
||||
#define TAH_REV_BN_V (0) |
||||
|
||||
/* TAH Mode Register */ |
||||
#define TAH_MR_CVR (0x80000000) /* Checksum verification on RX */ |
||||
#define TAH_MR_SR (0x40000000) /* Software reset */ |
||||
#define TAH_MR_ST (0x3F000000) /* Send Threshold */ |
||||
#define TAH_MR_TFS (0x00E00000) /* Transmit FIFO size */ |
||||
#define TAH_MR_DTFP (0x00100000) /* Disable TX FIFO parity */ |
||||
#define TAH_MR_DIG (0x00080000) /* Disable interrupt generation */ |
||||
#define TAH_MR_RSVD (0x0007FFFF) /* Reserved */ |
||||
|
||||
#define TAH_MR_ST_V (20) |
||||
#define TAH_MR_TFS_V (17) |
||||
|
||||
#define TAH_MR_TFS_2K (0x1) /* Transmit FIFO size 2Kbyte */ |
||||
#define TAH_MR_TFS_4K (0x2) /* Transmit FIFO size 4Kbyte */ |
||||
#define TAH_MR_TFS_6K (0x3) /* Transmit FIFO size 6Kbyte */ |
||||
#define TAH_MR_TFS_8K (0x4) /* Transmit FIFO size 8Kbyte */ |
||||
#define TAH_MR_TFS_10K (0x5) /* Transmit FIFO size 10Kbyte (max)*/ |
||||
|
||||
|
||||
/* TAH Segment Size Registers 0:5 */ |
||||
#define TAH_SSR_RSVD0 (0xC0000000) /* Reserved */ |
||||
#define TAH_SSR_SS (0x3FFE0000) /* Segment size in multiples of 2 */ |
||||
#define TAH_SSR_RSVD1 (0x0001FFFF) /* Reserved */ |
||||
|
||||
/* TAH Transmit Status Register */ |
||||
#define TAH_TSR_TFTS (0x80000000) /* Transmit FIFO too small */ |
||||
#define TAH_TSR_UH (0x40000000) /* Unrecognized header */ |
||||
#define TAH_TSR_NIPF (0x20000000) /* Not IPv4 */ |
||||
#define TAH_TSR_IPOP (0x10000000) /* IP option present */ |
||||
#define TAH_TSR_NISF (0x08000000) /* No IEEE SNAP format */ |
||||
#define TAH_TSR_ILTS (0x04000000) /* IP length too short */ |
||||
#define TAH_TSR_IPFP (0x02000000) /* IP fragment present */ |
||||
#define TAH_TSR_UP (0x01000000) /* Unsupported protocol */ |
||||
#define TAH_TSR_TFP (0x00800000) /* TCP flags present */ |
||||
#define TAH_TSR_SUDP (0x00400000) /* Segmentation for UDP */ |
||||
#define TAH_TSR_DLM (0x00200000) /* Data length mismatch */ |
||||
#define TAH_TSR_SIEEE (0x00100000) /* Segmentation for IEEE */ |
||||
#define TAH_TSR_TFPE (0x00080000) /* Transmit FIFO parity error */ |
||||
#define TAH_TSR_SSTS (0x00040000) /* Segment size too small */ |
||||
#define TAH_TSR_RSVD (0x0003FFFF) /* Reserved */ |
||||
#endif /* CONFIG_440_GX */ |
||||
|
||||
|
||||
/* Ethernet MAC Regsiter Addresses */ |
||||
#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800) |
||||
|
||||
#define EMAC_M0 (EMAC_BASE) |
||||
#define EMAC_M1 (EMAC_BASE + 4) |
||||
#define EMAC_TXM0 (EMAC_BASE + 8) |
||||
#define EMAC_TXM1 (EMAC_BASE + 12) |
||||
#define EMAC_RXM (EMAC_BASE + 16) |
||||
#define EMAC_ISR (EMAC_BASE + 20) |
||||
#define EMAC_IER (EMAC_BASE + 24) |
||||
#define EMAC_IAH (EMAC_BASE + 28) |
||||
#define EMAC_IAL (EMAC_BASE + 32) |
||||
#define EMAC_VLAN_TPID_REG (EMAC_BASE + 36) |
||||
#define EMAC_VLAN_TCI_REG (EMAC_BASE + 40) |
||||
#define EMAC_PAUSE_TIME_REG (EMAC_BASE + 44) |
||||
#define EMAC_IND_HASH_1 (EMAC_BASE + 48) |
||||
#define EMAC_IND_HASH_2 (EMAC_BASE + 52) |
||||
#define EMAC_IND_HASH_3 (EMAC_BASE + 56) |
||||
#define EMAC_IND_HASH_4 (EMAC_BASE + 60) |
||||
#define EMAC_GRP_HASH_1 (EMAC_BASE + 64) |
||||
#define EMAC_GRP_HASH_2 (EMAC_BASE + 68) |
||||
#define EMAC_GRP_HASH_3 (EMAC_BASE + 72) |
||||
#define EMAC_GRP_HASH_4 (EMAC_BASE + 76) |
||||
#define EMAC_LST_SRC_LOW (EMAC_BASE + 80) |
||||
#define EMAC_LST_SRC_HI (EMAC_BASE + 84) |
||||
#define EMAC_I_FRAME_GAP_REG (EMAC_BASE + 88) |
||||
#define EMAC_STACR (EMAC_BASE + 92) |
||||
#define EMAC_TRTR (EMAC_BASE + 96) |
||||
#define EMAC_RX_HI_LO_WMARK (EMAC_BASE + 100) |
||||
|
||||
/* bit definitions */ |
||||
/* MODE REG 0 */ |
||||
#define EMAC_M0_RXI (0x80000000) |
||||
#define EMAC_M0_TXI (0x40000000) |
||||
#define EMAC_M0_SRST (0x20000000) |
||||
#define EMAC_M0_TXE (0x10000000) |
||||
#define EMAC_M0_RXE (0x08000000) |
||||
#define EMAC_M0_WKE (0x04000000) |
||||
|
||||
/* MODE Reg 1 */ |
||||
#define EMAC_M1_FDE (0x80000000) |
||||
#define EMAC_M1_ILE (0x40000000) |
||||
#define EMAC_M1_VLE (0x20000000) |
||||
#define EMAC_M1_EIFC (0x10000000) |
||||
#define EMAC_M1_APP (0x08000000) |
||||
#define EMAC_M1_RSVD (0x06000000) |
||||
#define EMAC_M1_IST (0x01000000) |
||||
#define EMAC_M1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */ |
||||
#define EMAC_M1_MF_100MBPS (0x00400000) |
||||
#define EMAC_M1_RFS_16K (0x00280000) /* ~4k for 512 byte */ |
||||
#define EMAC_M1_RFS_8K (0x00200000) /* ~4k for 512 byte */ |
||||
#define EMAC_M1_RFS_4K (0x00180000) /* ~4k for 512 byte */ |
||||
#define EMAC_M1_RFS_2K (0x00100000) |
||||
#define EMAC_M1_RFS_1K (0x00080000) |
||||
#define EMAC_M1_TX_FIFO_16K (0x00050000) /* 0's for 512 byte */ |
||||
#define EMAC_M1_TX_FIFO_8K (0x00040000) |
||||
#define EMAC_M1_TX_FIFO_4K (0x00030000) |
||||
#define EMAC_M1_TX_FIFO_2K (0x00020000) |
||||
#define EMAC_M1_TX_FIFO_1K (0x00010000) |
||||
#define EMAC_M1_TR_MULTI (0x00008000) /* 0'x for single packet */ |
||||
#define EMAC_M1_MWSW (0x00007000) |
||||
#define EMAC_M1_JUMBO_ENABLE (0x00000800) |
||||
#define EMAC_M1_IPPA (0x000007c0) |
||||
#define EMAC_M1_OBCI_GT100 (0x00000020) |
||||
#define EMAC_M1_OBCI_100 (0x00000018) |
||||
#define EMAC_M1_OBCI_83 (0x00000010) |
||||
#define EMAC_M1_OBCI_66 (0x00000008) |
||||
#define EMAC_M1_RSVD1 (0x00000007) |
||||
/* Transmit Mode Register 0 */ |
||||
#define EMAC_TXM0_GNP0 (0x80000000) |
||||
#define EMAC_TXM0_GNP1 (0x40000000) |
||||
#define EMAC_TXM0_GNPD (0x20000000) |
||||
#define EMAC_TXM0_FC (0x10000000) |
||||
|
||||
/* Receive Mode Register */ |
||||
#define EMAC_RMR_SP (0x80000000) |
||||
#define EMAC_RMR_SFCS (0x40000000) |
||||
#define EMAC_RMR_ARRP (0x20000000) |
||||
#define EMAC_RMR_ARP (0x10000000) |
||||
#define EMAC_RMR_AROP (0x08000000) |
||||
#define EMAC_RMR_ARPI (0x04000000) |
||||
#define EMAC_RMR_PPP (0x02000000) |
||||
#define EMAC_RMR_PME (0x01000000) |
||||
#define EMAC_RMR_PMME (0x00800000) |
||||
#define EMAC_RMR_IAE (0x00400000) |
||||
#define EMAC_RMR_MIAE (0x00200000) |
||||
#define EMAC_RMR_BAE (0x00100000) |
||||
#define EMAC_RMR_MAE (0x00080000) |
||||
|
||||
/* Interrupt Status & enable Regs */ |
||||
#define EMAC_ISR_OVR (0x02000000) |
||||
#define EMAC_ISR_PP (0x01000000) |
||||
#define EMAC_ISR_BP (0x00800000) |
||||
#define EMAC_ISR_RP (0x00400000) |
||||
#define EMAC_ISR_SE (0x00200000) |
||||
#define EMAC_ISR_SYE (0x00100000) |
||||
#define EMAC_ISR_BFCS (0x00080000) |
||||
#define EMAC_ISR_PTLE (0x00040000) |
||||
#define EMAC_ISR_ORE (0x00020000) |
||||
#define EMAC_ISR_IRE (0x00010000) |
||||
#define EMAC_ISR_DBDM (0x00000200) |
||||
#define EMAC_ISR_DB0 (0x00000100) |
||||
#define EMAC_ISR_SE0 (0x00000080) |
||||
#define EMAC_ISR_TE0 (0x00000040) |
||||
#define EMAC_ISR_DB1 (0x00000020) |
||||
#define EMAC_ISR_SE1 (0x00000010) |
||||
#define EMAC_ISR_TE1 (0x00000008) |
||||
#define EMAC_ISR_MOS (0x00000002) |
||||
#define EMAC_ISR_MOF (0x00000001) |
||||
|
||||
|
||||
/* STA CONTROL REG */ |
||||
#define EMAC_STACR_OC (0x00008000) |
||||
#define EMAC_STACR_PHYE (0x00004000) |
||||
#define EMAC_STACR_WRITE (0x00002000) |
||||
#define EMAC_STACR_READ (0x00001000) |
||||
#define EMAC_STACR_CLK_83MHZ (0x00000800) /* 0's for 50Mhz */ |
||||
#define EMAC_STACR_CLK_66MHZ (0x00000400) |
||||
#define EMAC_STACR_CLK_100MHZ (0x00000C00) |
||||
|
||||
/* Transmit Request Threshold Register */ |
||||
#define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */ |
||||
#define EMAC_TRTR_192 (0x10000000) |
||||
#define EMAC_TRTR_128 (0x01000000) |
||||
|
||||
/* the follwing defines are for the MadMAL status and control registers. */ |
||||
/* For bits 0..5 look at the mal.h file */ |
||||
#define EMAC_TX_CTRL_GFCS (0x0200) |
||||
#define EMAC_TX_CTRL_GP (0x0100) |
||||
#define EMAC_TX_CTRL_ISA (0x0080) |
||||
#define EMAC_TX_CTRL_RSA (0x0040) |
||||
#define EMAC_TX_CTRL_IVT (0x0020) |
||||
#define EMAC_TX_CTRL_RVT (0x0010) |
||||
|
||||
#define EMAC_TX_CTRL_DEFAULT (EMAC_TX_CTRL_GFCS |EMAC_TX_CTRL_GP) |
||||
|
||||
#define EMAC_TX_ST_BFCS (0x0200) |
||||
#define EMAC_TX_ST_BPP (0x0100) |
||||
#define EMAC_TX_ST_LCS (0x0080) |
||||
#define EMAC_TX_ST_ED (0x0040) |
||||
#define EMAC_TX_ST_EC (0x0020) |
||||
#define EMAC_TX_ST_LC (0x0010) |
||||
#define EMAC_TX_ST_MC (0x0008) |
||||
#define EMAC_TX_ST_SC (0x0004) |
||||
#define EMAC_TX_ST_UR (0x0002) |
||||
#define EMAC_TX_ST_SQE (0x0001) |
||||
|
||||
#define EMAC_TX_ST_DEFAULT (0x03F3) |
||||
|
||||
|
||||
/* madmal receive status / Control bits */ |
||||
|
||||
#define EMAC_RX_ST_OE (0x0200) |
||||
#define EMAC_RX_ST_PP (0x0100) |
||||
#define EMAC_RX_ST_BP (0x0080) |
||||
#define EMAC_RX_ST_RP (0x0040) |
||||
#define EMAC_RX_ST_SE (0x0020) |
||||
#define EMAC_RX_ST_AE (0x0010) |
||||
#define EMAC_RX_ST_BFCS (0x0008) |
||||
#define EMAC_RX_ST_PTL (0x0004) |
||||
#define EMAC_RX_ST_ORE (0x0002) |
||||
#define EMAC_RX_ST_IRE (0x0001) |
||||
/* all the errors we care about */ |
||||
#define EMAC_RX_ERRORS (0x03FF) |
||||
|
||||
#endif /* CONFIG_440 */ |
||||
#endif /* _enetLib_h_ */ |
@ -0,0 +1,266 @@ |
||||
/*
|
||||
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/************************************************************************
|
||||
* config for XPedite1000 from XES Inc. |
||||
* Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com> |
||||
* (C) Copyright 2003 Sandburst Corporation |
||||
* board/config_EBONY.h - configuration for IBM 440GP Ref (Ebony) |
||||
***********************************************************************/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_XPEDITE1K 1 /* Board is XPedite 1000 */ |
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */ |
||||
#define CONFIG_440 1 |
||||
#define CONFIG_440_GX 1 /* 440 GX */ |
||||
#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */ |
||||
#undef CFG_DRAM_TEST /* Disable-takes long time! */ |
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
||||
|
||||
|
||||
/* POST support */ |
||||
#define CONFIG_POST (CFG_POST_RTC | \ |
||||
CFG_POST_I2C) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the |
||||
* actual resources get mapped (not physical addresses) |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ |
||||
#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */ |
||||
|
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE /* start of monitor */ |
||||
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ |
||||
#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ |
||||
#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ |
||||
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ |
||||
|
||||
#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) |
||||
#define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700) |
||||
|
||||
#define USR_LED0 0x00000080 |
||||
#define USR_LED1 0x00000100 |
||||
#define USR_LED2 0x00000200 |
||||
#define USR_LED3 0x00000400 |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
extern unsigned long in32(unsigned int); |
||||
extern void out32(unsigned int, unsigned long); |
||||
|
||||
#define LED0_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED0)) |
||||
#define LED1_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED1)) |
||||
#define LED2_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED2)) |
||||
#define LED3_ON() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) & ~USR_LED3)) |
||||
|
||||
#define LED0_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED0)) |
||||
#define LED1_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED1)) |
||||
#define LED2_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED2)) |
||||
#define LED3_OFF() out32(CFG_GPIO_BASE, (in32(CFG_GPIO_BASE) | USR_LED3)) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer (placed in internal SRAM) |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ |
||||
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
||||
|
||||
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) |
||||
#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR |
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port |
||||
*----------------------------------------------------------------------*/ |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#define CONFIG_BAUDRATE 9600 |
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM/RTC |
||||
* |
||||
* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. |
||||
* The DS1743 code assumes this condition (i.e. -- it assumes the base |
||||
* address for the RTC registers is: |
||||
* |
||||
* CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE |
||||
* |
||||
*----------------------------------------------------------------------*/ |
||||
/* TBS: Xpedite 1000 has STMicro M41T00 via IIC */ |
||||
#define CONFIG_RTC_M41T11 1 |
||||
#define CFG_I2C_RTC_ADDR 0x68 |
||||
#define CFG_M41T11_BASE_YEAR 2000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ |
||||
#define CFG_MAX_FLASH_SECT 8 /* sectors per device */ |
||||
|
||||
#undef CFG_FLASH_CHECKSUM |
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ |
||||
#define SPD_EEPROM_ADDRESS {0x54} /* SPD i2c spd addresses */ |
||||
#define CONFIG_VERY_BIG_RAM 1 |
||||
/*-----------------------------------------------------------------------
|
||||
* I2C |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7f |
||||
#define CFG_I2C_NOPROBES {0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x69} /* Don't probe these addrs */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment |
||||
*----------------------------------------------------------------------*/ |
||||
#define CFG_ENV_IS_IN_EEPROM 1 |
||||
#define CFG_ENV_SIZE 0x100 /* Size of Environment vars */ |
||||
#define CFG_ENV_OFFSET 0x100 |
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* this is actually the second page of the eeprom */ |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 |
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 3 |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 |
||||
|
||||
#define CONFIG_BOOTARGS "root=/dev/hda1 " |
||||
#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */ |
||||
#define CONFIG_BOOTDELAY -1 /* disable autoboot */ |
||||
#define CONFIG_BAUDRATE 9600 |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_PHY_ADDR 0 /* PHY address phy0 not populated */ |
||||
#define CONFIG_PHY1_ADDR 1 /* PHY address phy1 not populated */ |
||||
#define CONFIG_PHY2_ADDR 4 /* PHY address phy2 */ |
||||
#define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */ |
||||
#define CONFIG_NET_MULTI 1 |
||||
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_BEDBUG | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_DIAG | \
|
||||
CFG_CMD_FAT ) |
||||
|
||||
/* CFG_CMD_DHCP | \ */ |
||||
/* CFG_CMD_KGDB | \ */ |
||||
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
/* General PCI */ |
||||
#define CONFIG_PCI /* include pci support */ |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ |
||||
|
||||
/* Board-specific PCI */ |
||||
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ |
||||
#define CFG_PCI_TARGET_INIT /* let board init pci target */ |
||||
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ |
||||
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_DCACHE_SIZE 8192 /* For IBM 440GX CPUs */ |
||||
#define CFG_CACHELINE_SIZE 32 /* ... */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
#endif /* __CONFIG_H */ |
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