Add xhci driver support for all FSL socs Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>master
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/*
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* Copyright 2015 Freescale Semiconductor, Inc. |
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* |
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* FSL USB HOST xHCI Controller |
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* |
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* Author: Ramneek Mehresh<ramneek.mehresh@freescale.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <usb.h> |
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#include <asm-generic/errno.h> |
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#include <asm/arch-ls102xa/immap_ls102xa.h> |
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#include <linux/compat.h> |
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#include <linux/usb/xhci-fsl.h> |
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#include <linux/usb/dwc3.h> |
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#include "xhci.h" |
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/* Declare global data pointer */ |
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DECLARE_GLOBAL_DATA_PTR; |
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static struct fsl_xhci fsl_xhci; |
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unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR; |
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__weak int __board_usb_init(int index, enum usb_init_type init) |
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{ |
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return 0; |
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} |
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void usb_phy_reset(struct dwc3 *dwc3_reg) |
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{ |
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/* Assert USB3 PHY reset */ |
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setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); |
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/* Assert USB2 PHY reset */ |
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setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); |
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mdelay(200); |
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/* Clear USB3 PHY reset */ |
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clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); |
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/* Clear USB2 PHY reset */ |
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clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); |
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} |
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static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci) |
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{ |
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int ret = 0; |
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ret = dwc3_core_init(fsl_xhci->dwc3_reg); |
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if (ret) { |
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debug("%s:failed to initialize core\n", __func__); |
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return ret; |
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} |
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/* We are hard-coding DWC3 core to Host Mode */ |
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dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); |
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return ret; |
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} |
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static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci) |
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{ |
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/*
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* Currently fsl socs do not support PHY shutdown from |
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* sw. But this support may be added in future socs. |
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*/ |
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return 0; |
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} |
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int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) |
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{ |
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struct fsl_xhci *ctx = &fsl_xhci; |
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int ret = 0; |
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ctx->hcd = (struct xhci_hccr *)ctr_addr[index]; |
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ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); |
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ret = board_usb_init(index, USB_INIT_HOST); |
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if (ret != 0) { |
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puts("Failed to initialize board for USB\n"); |
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return ret; |
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} |
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ret = fsl_xhci_core_init(ctx); |
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if (ret < 0) { |
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puts("Failed to initialize xhci\n"); |
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return ret; |
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} |
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*hccr = (struct xhci_hccr *)ctx->hcd; |
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*hcor = (struct xhci_hcor *)((uint32_t) *hccr |
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+ HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); |
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debug("fsl-xhci: init hccr %x and hcor %x hc_length %d\n", |
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(uint32_t)*hccr, (uint32_t)*hcor, |
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(uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); |
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return ret; |
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} |
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void xhci_hcd_stop(int index) |
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{ |
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struct fsl_xhci *ctx = &fsl_xhci; |
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fsl_xhci_core_exit(ctx); |
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} |
@ -0,0 +1,54 @@ |
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/*
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* Copyright 2015 Freescale Semiconductor, Inc. |
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* |
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* FSL USB HOST xHCI Controller |
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* |
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* Author: Ramneek Mehresh<ramneek.mehresh@freescale.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _ASM_ARCH_XHCI_FSL_H_ |
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#define _ASM_ARCH_XHCI_FSL_H_ |
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/* Default to the FSL XHCI defines */ |
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#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000 |
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#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC |
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#define USB3_PHY_PARTIAL_RX_POWERON BIT(6) |
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#define USB3_PHY_RX_POWERON BIT(14) |
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#define USB3_PHY_TX_POWERON BIT(15) |
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#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON) |
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#define USB3_PWRCTL_CLK_CMD_SHIFT 14 |
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#define USB3_PWRCTL_CLK_FREQ_SHIFT 22 |
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/* USBOTGSS_WRAPPER definitions */ |
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#define USBOTGSS_WRAPRESET BIT(17) |
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#define USBOTGSS_DMADISABLE BIT(16) |
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#define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4) |
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#define USBOTGSS_STANDBYMODE_SMRT BIT(5) |
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#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4) |
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#define USBOTGSS_IDLEMODE_NOIDLE BIT(2) |
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#define USBOTGSS_IDLEMODE_SMRT BIT(3) |
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#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2) |
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/* USBOTGSS_IRQENABLE_SET_0 bit */ |
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#define USBOTGSS_COREIRQ_EN BIT(1) |
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/* USBOTGSS_IRQENABLE_SET_1 bits */ |
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#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1) |
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#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3) |
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#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4) |
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#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5) |
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#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8) |
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#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11) |
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#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12) |
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#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13) |
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#define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16) |
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#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17) |
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struct fsl_xhci { |
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struct xhci_hccr *hcd; |
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struct dwc3 *dwc3_reg; |
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}; |
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#endif /* _ASM_ARCH_XHCI_FSL_H_ */ |
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