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/*
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* (C) Copyright 2001 |
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* Josh Huber, Mission Critical Linux, Inc. <huber@mclx.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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/*
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* 74xx_7xx.h |
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* |
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* 74xx/7xx specific definitions |
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*/ |
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#ifndef __MPC74XX_H__ |
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#define __MPC74XX_H__ |
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|
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/*----------------------------------------------------------------
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* Exception offsets (PowerPC standard) |
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*/ |
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#define EXC_OFF_SYS_RESET 0x0100 /* default system reset offset */ |
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|
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/*----------------------------------------------------------------
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* l2cr values |
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*/ |
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#define l2cr 1017 |
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#define L2CR_L2E 0x80000000 /* bit 0 - enable */ |
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#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */ |
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#define L2CR_L2SIZ_2M 0x00000000 /* bits 2-3 - 2MB, MPC7400 only! */ |
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#define L2CR_L2SIZ_1M 0x30000000 /* ... 1MB */ |
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#define L2CR_L2SIZ_HM 0x20000000 /* ... 512K */ |
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#define L2CR_L2SIZ_QM 0x10000000 /* ... 256k */ |
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#define L2CR_L2CLK_1 0x02000000 /* bits 4-6 clock ratio div 1 */ |
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#define L2CR_L2CLK_1_5 0x04000000 /* bits 4-6 clock ratio div 1.5 */ |
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#define L2CR_L2CLK_2 0x08000000 /* bits 4-6 clock ratio div 2 */ |
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#define L2CR_L2CLK_2_5 0x0a000000 /* bits 4-6 clock ratio div 2.5 */ |
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#define L2CR_L2CLK_3 0x0c000000 /* bits 4-6 clock ratio div 3 */ |
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#define L2CR_L2CLK_3_5 0x06000000 /* bits 4-6 clock ratio div 3.5 */ |
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#define L2CR_L2CLK_4 0x0e000000 /* bits 4-6 clock ratio div 4 */ |
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#define L2CR_L2RAM_BURST 0x01000000 /* bits 7-8 - burst SRAM */ |
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#define L2CR_DO 0x00400000 /* bit 9 - enable caching of instr. in L2 */ |
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#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */ |
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#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */ |
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#define L2CR_L2WT 0x00080000 /* bit 12 - l2 write-through */ |
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#define L2CR_TS 0x00040000 /* bit 13 - test support on */ |
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#define L2CR_TS_OFF -L2CR_TS /* bit 13 - test support off */ |
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#define L2CR_L2OH_5 0x00000000 /* bits 14-15 - output hold time = short */ |
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#define L2CR_L2OH_1 0x00010000 /* bits 14-15 - output hold time = medium */ |
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#define L2CR_L2OH_INV 0x00020000 /* bits 14-15 - output hold time = long */ |
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#define L2CR_L2IP 0x00000001 /* global invalidate in progress */ |
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/*----------------------------------------------------------------
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* BAT settings. Look in config_<BOARD>.h for the actual setup |
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*/ |
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#define BATU_BL_128K 0x00000000 |
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#define BATU_BL_256K 0x00000004 |
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#define BATU_BL_512K 0x0000000c |
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#define BATU_BL_1M 0x0000001c |
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#define BATU_BL_2M 0x0000003c |
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#define BATU_BL_4M 0x0000007c |
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#define BATU_BL_8M 0x000000fc |
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#define BATU_BL_16M 0x000001fc |
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#define BATU_BL_32M 0x000003fc |
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#define BATU_BL_64M 0x000007fc |
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#define BATU_BL_128M 0x00000ffc |
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#define BATU_BL_256M 0x00001ffc |
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#define BATU_VS 0x00000002 |
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#define BATU_VP 0x00000001 |
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#define BATU_INVALID 0x00000000 |
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#define BATL_WRITETHROUGH 0x00000040 |
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#define BATL_CACHEINHIBIT 0x00000020 |
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#define BATL_MEMCOHERENCE 0x00000010 |
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#define BATL_GUARDEDSTORAGE 0x00000008 |
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#define BATL_NO_ACCESS 0x00000000 |
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#define BATL_PP_MSK 0x00000003 |
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#define BATL_PP_00 0x00000000 /* No access */ |
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#define BATL_PP_01 0x00000001 /* Read-only */ |
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#define BATL_PP_10 0x00000002 /* Read-write */ |
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#define BATL_PP_11 0x00000003 |
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#define BATL_PP_NO_ACCESS BATL_PP_00 |
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#define BATL_PP_RO BATL_PP_01 |
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#define BATL_PP_RW BATL_PP_10 |
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#ifndef __ASSEMBLY__ |
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/* cpu ids we detect */ |
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typedef enum __cpu_t { |
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CPU_740, CPU_750, |
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CPU_740P, CPU_750P, |
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CPU_745, CPU_755, |
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CPU_750CX, |
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CPU_7400, |
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CPU_7410, |
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CPU_7450, |
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CPU_UNKNOWN} cpu_t; |
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extern cpu_t get_cpu_type(void); |
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#define l1icache_enable icache_enable |
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void l2cache_enable(void); |
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void l1dcache_enable(void); |
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static __inline__ unsigned long get_msr (void) |
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{ |
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unsigned long msr; |
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asm volatile("mfmsr %0" : "=r" (msr) :); |
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return msr; |
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} |
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static __inline__ void set_msr (unsigned long msr) |
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{ |
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asm volatile("mtmsr %0" : : "r" (msr)); |
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} |
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static __inline__ unsigned long get_hid0 (void) |
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{ |
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unsigned long hid0; |
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asm volatile("mfspr %0, 1008" : "=r" (hid0) :); |
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return hid0; |
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} |
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static __inline__ unsigned long get_hid1 (void) |
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{ |
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unsigned long hid1; |
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asm volatile("mfspr %0, 1009" : "=r" (hid1) :); |
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return hid1; |
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} |
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static __inline__ void set_hid0 (unsigned long hid0) |
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{ |
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asm volatile("mtspr 1008, %0" : : "r" (hid0)); |
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} |
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static __inline__ void set_hid1 (unsigned long hid1) |
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{ |
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asm volatile("mtspr 1009, %0" : : "r" (hid1)); |
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} |
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#endif /* __ASSEMBLY__ */ |
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#endif /* __MPC74XX_H__ */ |
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