From 55429a0323c8b39618b0005a7b8e496c5f8da997 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 5 Apr 2010 02:28:14 +0200 Subject: [PATCH 1/4] PXA: PXAMMC: Drop different delays for PXA27X In case the delays were set to 10000, the MMC card on PXA27X boards (and PXA3xx boards) didn't initialize on first try. Increasing the delays and leaving just those for PXA25x and 26x (that is 200000) fixes this problem. Signed-off-by: Marek Vasut --- drivers/mmc/pxa_mmc.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/mmc/pxa_mmc.c b/drivers/mmc/pxa_mmc.c index 8225235..b155541 100644 --- a/drivers/mmc/pxa_mmc.c +++ b/drivers/mmc/pxa_mmc.c @@ -584,11 +584,7 @@ mmc_legacy_init(int verbose) debug("Detected SD card\n"); break; } -#ifdef CONFIG_PXA27X - udelay(10000); -#else udelay(200000); -#endif } if (retries <= 0 || !(IF_TYPE_SD == mmc_dev.if_type)) { @@ -598,11 +594,7 @@ mmc_legacy_init(int verbose) retries = 10; while (retries-- && resp && !(resp[0] & 0x80000000)) { -#ifdef CONFIG_PXA27X - udelay(10000); -#else udelay(200000); -#endif resp = mmc_cmd(MMC_CMD_SEND_OP_COND, 0x00ff, 0x8000, MMC_CMDAT_R3); From 43c15d3dd570be97d44944cade99ab03e6d5491e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 14 Oct 2009 00:25:33 +0200 Subject: [PATCH 2/4] PXA: PXAMMC: Add Monahans support This patch enables PXAMCI support on PXA3xx CPUs. This patch only enables MMC1 though, MMC2 and PXA31x MMC3 will need further patch to be operational. Signed-off-by: Marek Vasut --- drivers/mmc/pxa_mmc.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/pxa_mmc.c b/drivers/mmc/pxa_mmc.c index b155541..8776903 100644 --- a/drivers/mmc/pxa_mmc.c +++ b/drivers/mmc/pxa_mmc.c @@ -126,7 +126,7 @@ mmc_block_read(uchar * dst, ulong src, ulong len) MMC_I_MASK = ~MMC_I_MASK_RXFIFO_RD_REQ; while (len) { if (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ) { -#ifdef CONFIG_PXA27X +#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) int i; for (i = min(len, 32); i; i--) { *dst++ = *((volatile uchar *)&MMC_RXFIFO); @@ -558,8 +558,11 @@ mmc_legacy_init(int verbose) set_GPIO_mode(GPIO6_MMCCLK_MD); set_GPIO_mode(GPIO8_MMCCS0_MD); #endif +#ifdef CONFIG_CPU_MONAHANS /* pxa3xx */ + CKENA |= CKENA_12_MMC0 | CKENA_13_MMC1; +#else /* pxa2xx */ CKEN |= CKEN12_MMC; /* enable MMC unit clock */ - +#endif MMC_CLKRT = MMC_CLKRT_0_3125MHZ; MMC_RESTO = MMC_RES_TO_MAX; MMC_SPI = MMC_SPI_DISABLE; @@ -624,7 +627,7 @@ mmc_legacy_init(int verbose) MMC_CLKRT = 0; /* 20 MHz */ resp = mmc_cmd(MMC_CMD_SELECT_CARD, rca, 0, MMC_CMDAT_R1); -#ifdef CONFIG_PXA27X +#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) if (IF_TYPE_SD == mmc_dev.if_type) { resp = mmc_cmd(MMC_CMD_APP_CMD, rca, 0, MMC_CMDAT_R1); resp = mmc_cmd(SD_CMD_APP_SET_BUS_WIDTH, 0, 2, MMC_CMDAT_R1); From 52dc45e5a3e60251329096400da5a9bb6a12ccbf Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 16 Apr 2010 22:25:14 +0200 Subject: [PATCH 3/4] PXA: Add UP2OCR register bit definitions This register is used on PXA to control the USB Port2 operation (USB Port2 is the host port). Signed-off-by: Marek Vasut --- arch/arm/include/asm/arch-pxa/pxa-regs.h | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h index a25d4c5..7cd7a14 100644 --- a/arch/arm/include/asm/arch-pxa/pxa-regs.h +++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h @@ -992,10 +992,6 @@ typedef void (*ExcpHndlr) (void) ; #define UHCHIE __REG(0x4C000068) #define UHCHIT __REG(0x4C00006C) -#if defined(CONFIG_CPU_MONAHANS) -#define UP2OCR __REG(0x40600020) -#endif - #define UHCHR_FSBIR (1<<0) #define UHCHR_FHR (1<<1) #define UHCHR_CGR (1<<2) @@ -1015,6 +1011,24 @@ typedef void (*ExcpHndlr) (void) ; #define UHCHIE_HBAIE (1<<8) #define UHCHIE_RWIE (1<<7) +#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) +#define UP2OCR __REG(0x40600020) +#endif + +#define UP2OCR_HXOE (1<<17) +#define UP2OCR_HXS (1<<16) +#define UP2OCR_IDON (1<<10) +#define UP2OCR_EXSUS (1<<9) +#define UP2OCR_EXSP (1<<8) +#define UP2OCR_DMSTATE (1<<7) +#define UP2OCR_VPM (1<<6) +#define UP2OCR_DPSTATE (1<<5) +#define UP2OCR_DPPUE (1<<4) +#define UP2OCR_DMPDE (1<<3) +#define UP2OCR_DPPDE (1<<2) +#define UP2OCR_CPVPE (1<<1) +#define UP2OCR_CPVEN (1<<0) + #endif /* From bb596e84ebd6e43d862b13755419b8a3e01b4f51 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 17 Apr 2010 00:35:52 +0200 Subject: [PATCH 4/4] PXA: Add missing MDREFR bits Signed-off-by: Marek Vasut --- arch/arm/include/asm/arch-pxa/pxa-regs.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h index 7cd7a14..cd7b7f9 100644 --- a/arch/arm/include/asm/arch-pxa/pxa-regs.h +++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h @@ -2421,6 +2421,9 @@ typedef void (*ExcpHndlr) (void) ; #define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */ #define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ +#define MDREFR_ALTREFA (1 << 31) /* Exiting Alternate Bus Master Mode Refresh Control */ +#define MDREFR_ALTREFB (1 << 30) /* Entering Alternate Bus Master Mode Refresh Control */ +#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */ #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ #define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */