Tom Rini
10 years ago
commit
bc80109b11
@ -0,0 +1,305 @@ |
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/*
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* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#define pr_fmt(fmt) "tegra-xusb-padctl: " fmt |
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#include <common.h> |
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#include <errno.h> |
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#include "xusb-padctl-common.h" |
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#include <asm/arch/clock.h> |
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int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy) |
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{ |
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if (phy && phy->ops && phy->ops->prepare) |
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return phy->ops->prepare(phy); |
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return phy ? -ENOSYS : -EINVAL; |
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} |
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int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy) |
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{ |
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if (phy && phy->ops && phy->ops->enable) |
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return phy->ops->enable(phy); |
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return phy ? -ENOSYS : -EINVAL; |
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} |
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int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy) |
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{ |
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if (phy && phy->ops && phy->ops->disable) |
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return phy->ops->disable(phy); |
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return phy ? -ENOSYS : -EINVAL; |
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} |
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int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy) |
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{ |
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if (phy && phy->ops && phy->ops->unprepare) |
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return phy->ops->unprepare(phy); |
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return phy ? -ENOSYS : -EINVAL; |
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} |
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struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type) |
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{ |
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struct tegra_xusb_phy *phy; |
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int i; |
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for (i = 0; i < padctl.socdata->num_phys; i++) { |
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phy = &padctl.socdata->phys[i]; |
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if (phy->type != type) |
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continue; |
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return phy; |
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} |
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return NULL; |
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} |
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static const struct tegra_xusb_padctl_lane * |
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tegra_xusb_padctl_find_lane(struct tegra_xusb_padctl *padctl, const char *name) |
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{ |
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unsigned int i; |
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for (i = 0; i < padctl->socdata->num_lanes; i++) |
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if (strcmp(name, padctl->socdata->lanes[i].name) == 0) |
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return &padctl->socdata->lanes[i]; |
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return NULL; |
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} |
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static int |
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tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl, |
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struct tegra_xusb_padctl_group *group, |
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const void *fdt, int node) |
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{ |
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unsigned int i; |
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int len, err; |
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group->name = fdt_get_name(fdt, node, &len); |
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len = fdt_count_strings(fdt, node, "nvidia,lanes"); |
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if (len < 0) { |
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error("failed to parse \"nvidia,lanes\" property"); |
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return -EINVAL; |
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} |
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group->num_pins = len; |
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for (i = 0; i < group->num_pins; i++) { |
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err = fdt_get_string_index(fdt, node, "nvidia,lanes", i, |
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&group->pins[i]); |
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if (err < 0) { |
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error("failed to read string from \"nvidia,lanes\" property"); |
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return -EINVAL; |
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} |
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} |
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group->num_pins = len; |
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err = fdt_get_string(fdt, node, "nvidia,function", &group->func); |
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if (err < 0) { |
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error("failed to parse \"nvidia,func\" property"); |
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return -EINVAL; |
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} |
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group->iddq = fdtdec_get_int(fdt, node, "nvidia,iddq", -1); |
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return 0; |
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} |
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static int tegra_xusb_padctl_find_function(struct tegra_xusb_padctl *padctl, |
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const char *name) |
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{ |
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unsigned int i; |
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for (i = 0; i < padctl->socdata->num_functions; i++) |
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if (strcmp(name, padctl->socdata->functions[i]) == 0) |
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return i; |
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return -ENOENT; |
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} |
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static int |
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tegra_xusb_padctl_lane_find_function(struct tegra_xusb_padctl *padctl, |
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const struct tegra_xusb_padctl_lane *lane, |
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const char *name) |
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{ |
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unsigned int i; |
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int func; |
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func = tegra_xusb_padctl_find_function(padctl, name); |
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if (func < 0) |
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return func; |
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for (i = 0; i < lane->num_funcs; i++) |
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if (lane->funcs[i] == func) |
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return i; |
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return -ENOENT; |
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} |
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static int |
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tegra_xusb_padctl_group_apply(struct tegra_xusb_padctl *padctl, |
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const struct tegra_xusb_padctl_group *group) |
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{ |
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unsigned int i; |
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for (i = 0; i < group->num_pins; i++) { |
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const struct tegra_xusb_padctl_lane *lane; |
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unsigned int func; |
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u32 value; |
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lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]); |
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if (!lane) { |
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error("no lane for pin %s", group->pins[i]); |
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continue; |
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} |
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func = tegra_xusb_padctl_lane_find_function(padctl, lane, |
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group->func); |
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if (func < 0) { |
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error("function %s invalid for lane %s: %d", |
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group->func, lane->name, func); |
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continue; |
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} |
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value = padctl_readl(padctl, lane->offset); |
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/* set pin function */ |
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value &= ~(lane->mask << lane->shift); |
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value |= func << lane->shift; |
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/*
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* Set IDDQ if supported on the lane and specified in the |
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* configuration. |
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*/ |
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if (lane->iddq > 0 && group->iddq >= 0) { |
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if (group->iddq != 0) |
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value &= ~(1 << lane->iddq); |
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else |
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value |= 1 << lane->iddq; |
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} |
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padctl_writel(padctl, value, lane->offset); |
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} |
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return 0; |
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} |
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static int |
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tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl, |
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struct tegra_xusb_padctl_config *config) |
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{ |
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unsigned int i; |
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for (i = 0; i < config->num_groups; i++) { |
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const struct tegra_xusb_padctl_group *group; |
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int err; |
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group = &config->groups[i]; |
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err = tegra_xusb_padctl_group_apply(padctl, group); |
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if (err < 0) { |
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error("failed to apply group %s: %d", |
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group->name, err); |
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continue; |
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} |
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} |
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return 0; |
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} |
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static int |
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tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl, |
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struct tegra_xusb_padctl_config *config, |
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const void *fdt, int node) |
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{ |
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int subnode; |
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config->name = fdt_get_name(fdt, node, NULL); |
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fdt_for_each_subnode(fdt, subnode, node) { |
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struct tegra_xusb_padctl_group *group; |
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int err; |
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group = &config->groups[config->num_groups]; |
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err = tegra_xusb_padctl_group_parse_dt(padctl, group, fdt, |
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subnode); |
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if (err < 0) { |
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error("failed to parse group %s", group->name); |
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return err; |
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} |
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config->num_groups++; |
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} |
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return 0; |
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} |
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static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl, |
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const void *fdt, int node) |
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{ |
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int subnode, err; |
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err = fdt_get_resource(fdt, node, "reg", 0, &padctl->regs); |
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if (err < 0) { |
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error("registers not found"); |
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return err; |
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} |
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fdt_for_each_subnode(fdt, subnode, node) { |
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struct tegra_xusb_padctl_config *config = &padctl->config; |
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err = tegra_xusb_padctl_config_parse_dt(padctl, config, fdt, |
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subnode); |
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if (err < 0) { |
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error("failed to parse entry %s: %d", |
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config->name, err); |
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continue; |
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} |
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} |
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return 0; |
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} |
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struct tegra_xusb_padctl padctl; |
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int tegra_xusb_process_nodes(const void *fdt, int nodes[], unsigned int count, |
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const struct tegra_xusb_padctl_soc *socdata) |
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{ |
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unsigned int i; |
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int err; |
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for (i = 0; i < count; i++) { |
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if (!fdtdec_get_is_enabled(fdt, nodes[i])) |
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continue; |
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padctl.socdata = socdata; |
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err = tegra_xusb_padctl_parse_dt(&padctl, fdt, nodes[i]); |
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if (err < 0) { |
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error("failed to parse DT: %d", err); |
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continue; |
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} |
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/* deassert XUSB padctl reset */ |
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reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0); |
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err = tegra_xusb_padctl_config_apply(&padctl, &padctl.config); |
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if (err < 0) { |
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error("failed to apply pinmux: %d", err); |
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continue; |
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} |
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/* only a single instance is supported */ |
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break; |
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} |
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return 0; |
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} |
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@ -0,0 +1,101 @@ |
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/*
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* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#ifndef _TEGRA_XUSB_PADCTL_COMMON_H_ |
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#define _TEGRA_XUSB_PADCTL_COMMON_H_ |
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#include <common.h> |
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#include <fdtdec.h> |
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#include <asm/io.h> |
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#include <asm/arch-tegra/xusb-padctl.h> |
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struct tegra_xusb_padctl_lane { |
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const char *name; |
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unsigned int offset; |
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unsigned int shift; |
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unsigned int mask; |
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unsigned int iddq; |
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const unsigned int *funcs; |
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unsigned int num_funcs; |
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}; |
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struct tegra_xusb_phy_ops { |
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int (*prepare)(struct tegra_xusb_phy *phy); |
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int (*enable)(struct tegra_xusb_phy *phy); |
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int (*disable)(struct tegra_xusb_phy *phy); |
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int (*unprepare)(struct tegra_xusb_phy *phy); |
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}; |
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struct tegra_xusb_phy { |
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unsigned int type; |
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const struct tegra_xusb_phy_ops *ops; |
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struct tegra_xusb_padctl *padctl; |
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}; |
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struct tegra_xusb_padctl_pin { |
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const struct tegra_xusb_padctl_lane *lane; |
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unsigned int func; |
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int iddq; |
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}; |
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#define MAX_GROUPS 5 |
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#define MAX_PINS 7 |
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struct tegra_xusb_padctl_group { |
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const char *name; |
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const char *pins[MAX_PINS]; |
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unsigned int num_pins; |
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const char *func; |
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int iddq; |
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}; |
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struct tegra_xusb_padctl_soc { |
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const struct tegra_xusb_padctl_lane *lanes; |
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unsigned int num_lanes; |
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const char *const *functions; |
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unsigned int num_functions; |
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struct tegra_xusb_phy *phys; |
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unsigned int num_phys; |
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}; |
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struct tegra_xusb_padctl_config { |
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const char *name; |
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struct tegra_xusb_padctl_group groups[MAX_GROUPS]; |
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unsigned int num_groups; |
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}; |
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struct tegra_xusb_padctl { |
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const struct tegra_xusb_padctl_soc *socdata; |
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struct tegra_xusb_padctl_config config; |
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struct fdt_resource regs; |
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unsigned int enable; |
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}; |
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extern struct tegra_xusb_padctl padctl; |
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static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl, |
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unsigned long offset) |
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{ |
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return readl(padctl->regs.start + offset); |
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} |
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static inline void padctl_writel(struct tegra_xusb_padctl *padctl, |
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u32 value, unsigned long offset) |
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{ |
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writel(value, padctl->regs.start + offset); |
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} |
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int tegra_xusb_process_nodes(const void *fdt, int nodes[], unsigned int count, |
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const struct tegra_xusb_padctl_soc *socdata); |
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#endif |
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@ -0,0 +1,417 @@ |
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/*
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* NVIDIA Tegra210 QSPI controller driver |
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* |
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* (C) Copyright 2015 NVIDIA Corporation <www.nvidia.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <asm/io.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch-tegra/clk_rst.h> |
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#include <spi.h> |
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#include <fdtdec.h> |
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#include "tegra_spi.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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/* COMMAND1 */ |
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#define QSPI_CMD1_GO BIT(31) |
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#define QSPI_CMD1_M_S BIT(30) |
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#define QSPI_CMD1_MODE_MASK GENMASK(1,0) |
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#define QSPI_CMD1_MODE_SHIFT 28 |
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#define QSPI_CMD1_CS_SEL_MASK GENMASK(1,0) |
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#define QSPI_CMD1_CS_SEL_SHIFT 26 |
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#define QSPI_CMD1_CS_POL_INACTIVE0 BIT(22) |
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#define QSPI_CMD1_CS_SW_HW BIT(21) |
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#define QSPI_CMD1_CS_SW_VAL BIT(20) |
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#define QSPI_CMD1_IDLE_SDA_MASK GENMASK(1,0) |
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#define QSPI_CMD1_IDLE_SDA_SHIFT 18 |
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#define QSPI_CMD1_BIDIR BIT(17) |
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#define QSPI_CMD1_LSBI_FE BIT(16) |
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#define QSPI_CMD1_LSBY_FE BIT(15) |
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#define QSPI_CMD1_BOTH_EN_BIT BIT(14) |
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#define QSPI_CMD1_BOTH_EN_BYTE BIT(13) |
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#define QSPI_CMD1_RX_EN BIT(12) |
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#define QSPI_CMD1_TX_EN BIT(11) |
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#define QSPI_CMD1_PACKED BIT(5) |
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#define QSPI_CMD1_BITLEN_MASK GENMASK(4,0) |
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#define QSPI_CMD1_BITLEN_SHIFT 0 |
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/* COMMAND2 */ |
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#define QSPI_CMD2_TX_CLK_TAP_DELAY BIT(6) |
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#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11,6) |
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#define QSPI_CMD2_RX_CLK_TAP_DELAY BIT(0) |
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#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5,0) |
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/* TRANSFER STATUS */ |
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#define QSPI_XFER_STS_RDY BIT(30) |
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/* FIFO STATUS */ |
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#define QSPI_FIFO_STS_CS_INACTIVE BIT(31) |
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#define QSPI_FIFO_STS_FRAME_END BIT(30) |
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#define QSPI_FIFO_STS_RX_FIFO_FLUSH BIT(15) |
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#define QSPI_FIFO_STS_TX_FIFO_FLUSH BIT(14) |
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#define QSPI_FIFO_STS_ERR BIT(8) |
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#define QSPI_FIFO_STS_TX_FIFO_OVF BIT(7) |
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#define QSPI_FIFO_STS_TX_FIFO_UNR BIT(6) |
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#define QSPI_FIFO_STS_RX_FIFO_OVF BIT(5) |
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#define QSPI_FIFO_STS_RX_FIFO_UNR BIT(4) |
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#define QSPI_FIFO_STS_TX_FIFO_FULL BIT(3) |
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#define QSPI_FIFO_STS_TX_FIFO_EMPTY BIT(2) |
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#define QSPI_FIFO_STS_RX_FIFO_FULL BIT(1) |
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#define QSPI_FIFO_STS_RX_FIFO_EMPTY BIT(0) |
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#define QSPI_TIMEOUT 1000 |
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struct qspi_regs { |
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u32 command1; /* 000:QSPI_COMMAND1 register */ |
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u32 command2; /* 004:QSPI_COMMAND2 register */ |
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u32 timing1; /* 008:QSPI_CS_TIM1 register */ |
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u32 timing2; /* 00c:QSPI_CS_TIM2 register */ |
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u32 xfer_status;/* 010:QSPI_TRANS_STATUS register */ |
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u32 fifo_status;/* 014:QSPI_FIFO_STATUS register */ |
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u32 tx_data; /* 018:QSPI_TX_DATA register */ |
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u32 rx_data; /* 01c:QSPI_RX_DATA register */ |
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u32 dma_ctl; /* 020:QSPI_DMA_CTL register */ |
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u32 dma_blk; /* 024:QSPI_DMA_BLK register */ |
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u32 rsvd[56]; /* 028-107 reserved */ |
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u32 tx_fifo; /* 108:QSPI_FIFO1 register */ |
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u32 rsvd2[31]; /* 10c-187 reserved */ |
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u32 rx_fifo; /* 188:QSPI_FIFO2 register */ |
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u32 spare_ctl; /* 18c:QSPI_SPARE_CTRL register */ |
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}; |
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struct tegra210_qspi_priv { |
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struct qspi_regs *regs; |
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unsigned int freq; |
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unsigned int mode; |
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int periph_id; |
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int valid; |
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int last_transaction_us; |
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}; |
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static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus) |
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{ |
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struct tegra_spi_platdata *plat = bus->platdata; |
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const void *blob = gd->fdt_blob; |
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int node = bus->of_offset; |
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plat->base = dev_get_addr(bus); |
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plat->periph_id = clock_decode_periph_id(blob, node); |
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if (plat->periph_id == PERIPH_ID_NONE) { |
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debug("%s: could not decode periph id %d\n", __func__, |
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plat->periph_id); |
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return -FDT_ERR_NOTFOUND; |
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} |
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/* Use 500KHz as a suitable default */ |
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plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", |
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500000); |
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plat->deactivate_delay_us = fdtdec_get_int(blob, node, |
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"spi-deactivate-delay", 0); |
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debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", |
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__func__, plat->base, plat->periph_id, plat->frequency, |
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plat->deactivate_delay_us); |
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return 0; |
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} |
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static int tegra210_qspi_probe(struct udevice *bus) |
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{ |
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struct tegra_spi_platdata *plat = dev_get_platdata(bus); |
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struct tegra210_qspi_priv *priv = dev_get_priv(bus); |
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priv->regs = (struct qspi_regs *)plat->base; |
||||
|
||||
priv->last_transaction_us = timer_get_us(); |
||||
priv->freq = plat->frequency; |
||||
priv->periph_id = plat->periph_id; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int tegra210_qspi_claim_bus(struct udevice *bus) |
||||
{ |
||||
struct tegra210_qspi_priv *priv = dev_get_priv(bus); |
||||
struct qspi_regs *regs = priv->regs; |
||||
|
||||
/* Change SPI clock to correct frequency, PLLP_OUT0 source */ |
||||
clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq); |
||||
|
||||
debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status)); |
||||
|
||||
/* Set master mode and sw controlled CS */ |
||||
setbits_le32(®s->command1, QSPI_CMD1_M_S | QSPI_CMD1_CS_SW_HW | |
||||
(priv->mode << QSPI_CMD1_MODE_SHIFT)); |
||||
debug("%s: COMMAND1 = %08x\n", __func__, readl(®s->command1)); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/**
|
||||
* Activate the CS by driving it LOW |
||||
* |
||||
* @param slave Pointer to spi_slave to which controller has to |
||||
* communicate with |
||||
*/ |
||||
static void spi_cs_activate(struct udevice *dev) |
||||
{ |
||||
struct udevice *bus = dev->parent; |
||||
struct tegra_spi_platdata *pdata = dev_get_platdata(bus); |
||||
struct tegra210_qspi_priv *priv = dev_get_priv(bus); |
||||
|
||||
/* If it's too soon to do another transaction, wait */ |
||||
if (pdata->deactivate_delay_us && |
||||
priv->last_transaction_us) { |
||||
ulong delay_us; /* The delay completed so far */ |
||||
delay_us = timer_get_us() - priv->last_transaction_us; |
||||
if (delay_us < pdata->deactivate_delay_us) |
||||
udelay(pdata->deactivate_delay_us - delay_us); |
||||
} |
||||
|
||||
clrbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL); |
||||
} |
||||
|
||||
/**
|
||||
* Deactivate the CS by driving it HIGH |
||||
* |
||||
* @param slave Pointer to spi_slave to which controller has to |
||||
* communicate with |
||||
*/ |
||||
static void spi_cs_deactivate(struct udevice *dev) |
||||
{ |
||||
struct udevice *bus = dev->parent; |
||||
struct tegra_spi_platdata *pdata = dev_get_platdata(bus); |
||||
struct tegra210_qspi_priv *priv = dev_get_priv(bus); |
||||
|
||||
setbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL); |
||||
|
||||
/* Remember time of this transaction so we can honour the bus delay */ |
||||
if (pdata->deactivate_delay_us) |
||||
priv->last_transaction_us = timer_get_us(); |
||||
|
||||
debug("Deactivate CS, bus '%s'\n", bus->name); |
||||
} |
||||
|
||||
static int tegra210_qspi_xfer(struct udevice *dev, unsigned int bitlen, |
||||
const void *data_out, void *data_in, |
||||
unsigned long flags) |
||||
{ |
||||
struct udevice *bus = dev->parent; |
||||
struct tegra210_qspi_priv *priv = dev_get_priv(bus); |
||||
struct qspi_regs *regs = priv->regs; |
||||
u32 reg, tmpdout, tmpdin = 0; |
||||
const u8 *dout = data_out; |
||||
u8 *din = data_in; |
||||
int num_bytes, tm, ret; |
||||
|
||||
debug("%s: slave %u:%u dout %p din %p bitlen %u\n", |
||||
__func__, bus->seq, spi_chip_select(dev), dout, din, bitlen); |
||||
if (bitlen % 8) |
||||
return -1; |
||||
num_bytes = bitlen / 8; |
||||
|
||||
ret = 0; |
||||
|
||||
/* clear all error status bits */ |
||||
reg = readl(®s->fifo_status); |
||||
writel(reg, ®s->fifo_status); |
||||
|
||||
/* flush RX/TX FIFOs */ |
||||
setbits_le32(®s->fifo_status, |
||||
(QSPI_FIFO_STS_RX_FIFO_FLUSH | |
||||
QSPI_FIFO_STS_TX_FIFO_FLUSH)); |
||||
|
||||
tm = QSPI_TIMEOUT; |
||||
while ((tm && readl(®s->fifo_status) & |
||||
(QSPI_FIFO_STS_RX_FIFO_FLUSH | |
||||
QSPI_FIFO_STS_TX_FIFO_FLUSH))) { |
||||
tm--; |
||||
udelay(1); |
||||
} |
||||
|
||||
if (!tm) { |
||||
printf("%s: timeout during QSPI FIFO flush!\n", |
||||
__func__); |
||||
return -1; |
||||
} |
||||
|
||||
/*
|
||||
* Notes: |
||||
* 1. don't set LSBY_FE, so no need to swap bytes from/to TX/RX FIFOs; |
||||
* 2. don't set RX_EN and TX_EN yet. |
||||
* (SW needs to make sure that while programming the blk_size, |
||||
* tx_en and rx_en bits must be zero) |
||||
* [TODO] I (Yen Lin) have problems when both RX/TX EN bits are set |
||||
* i.e., both dout and din are not NULL. |
||||
*/ |
||||
clrsetbits_le32(®s->command1, |
||||
(QSPI_CMD1_LSBI_FE | QSPI_CMD1_LSBY_FE | |
||||
QSPI_CMD1_RX_EN | QSPI_CMD1_TX_EN), |
||||
(spi_chip_select(dev) << QSPI_CMD1_CS_SEL_SHIFT)); |
||||
|
||||
/* set xfer size to 1 block (32 bits) */ |
||||
writel(0, ®s->dma_blk); |
||||
|
||||
if (flags & SPI_XFER_BEGIN) |
||||
spi_cs_activate(dev); |
||||
|
||||
/* handle data in 32-bit chunks */ |
||||
while (num_bytes > 0) { |
||||
int bytes; |
||||
|
||||
tmpdout = 0; |
||||
bytes = (num_bytes > 4) ? 4 : num_bytes; |
||||
|
||||
if (dout != NULL) { |
||||
memcpy((void *)&tmpdout, (void *)dout, bytes); |
||||
dout += bytes; |
||||
num_bytes -= bytes; |
||||
writel(tmpdout, ®s->tx_fifo); |
||||
setbits_le32(®s->command1, QSPI_CMD1_TX_EN); |
||||
} |
||||
|
||||
if (din != NULL) |
||||
setbits_le32(®s->command1, QSPI_CMD1_RX_EN); |
||||
|
||||
/* clear ready bit */ |
||||
setbits_le32(®s->xfer_status, QSPI_XFER_STS_RDY); |
||||
|
||||
clrsetbits_le32(®s->command1, |
||||
QSPI_CMD1_BITLEN_MASK << QSPI_CMD1_BITLEN_SHIFT, |
||||
(bytes * 8 - 1) << QSPI_CMD1_BITLEN_SHIFT); |
||||
|
||||
/* Need to stabilize other reg bits before GO bit set.
|
||||
* As per the TRM: |
||||
* "For successful operation at various freq combinations, |
||||
* a minimum of 4-5 spi_clk cycle delay might be required |
||||
* before enabling the PIO or DMA bits. The worst case delay |
||||
* calculation can be done considering slowest qspi_clk as |
||||
* 1MHz. Based on that 1us delay should be enough before |
||||
* enabling PIO or DMA." Padded another 1us for safety. |
||||
*/ |
||||
udelay(2); |
||||
setbits_le32(®s->command1, QSPI_CMD1_GO); |
||||
udelay(1); |
||||
|
||||
/*
|
||||
* Wait for SPI transmit FIFO to empty, or to time out. |
||||
* The RX FIFO status will be read and cleared last |
||||
*/ |
||||
for (tm = 0; tm < QSPI_TIMEOUT; ++tm) { |
||||
u32 fifo_status, xfer_status; |
||||
|
||||
xfer_status = readl(®s->xfer_status); |
||||
if (!(xfer_status & QSPI_XFER_STS_RDY)) |
||||
continue; |
||||
|
||||
fifo_status = readl(®s->fifo_status); |
||||
if (fifo_status & QSPI_FIFO_STS_ERR) { |
||||
debug("%s: got a fifo error: ", __func__); |
||||
if (fifo_status & QSPI_FIFO_STS_TX_FIFO_OVF) |
||||
debug("tx FIFO overflow "); |
||||
if (fifo_status & QSPI_FIFO_STS_TX_FIFO_UNR) |
||||
debug("tx FIFO underrun "); |
||||
if (fifo_status & QSPI_FIFO_STS_RX_FIFO_OVF) |
||||
debug("rx FIFO overflow "); |
||||
if (fifo_status & QSPI_FIFO_STS_RX_FIFO_UNR) |
||||
debug("rx FIFO underrun "); |
||||
if (fifo_status & QSPI_FIFO_STS_TX_FIFO_FULL) |
||||
debug("tx FIFO full "); |
||||
if (fifo_status & QSPI_FIFO_STS_TX_FIFO_EMPTY) |
||||
debug("tx FIFO empty "); |
||||
if (fifo_status & QSPI_FIFO_STS_RX_FIFO_FULL) |
||||
debug("rx FIFO full "); |
||||
if (fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY) |
||||
debug("rx FIFO empty "); |
||||
debug("\n"); |
||||
break; |
||||
} |
||||
|
||||
if (!(fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY)) { |
||||
tmpdin = readl(®s->rx_fifo); |
||||
if (din != NULL) { |
||||
memcpy(din, &tmpdin, bytes); |
||||
din += bytes; |
||||
num_bytes -= bytes; |
||||
} |
||||
} |
||||
break; |
||||
} |
||||
|
||||
if (tm >= QSPI_TIMEOUT) |
||||
ret = tm; |
||||
|
||||
/* clear ACK RDY, etc. bits */ |
||||
writel(readl(®s->fifo_status), ®s->fifo_status); |
||||
} |
||||
|
||||
if (flags & SPI_XFER_END) |
||||
spi_cs_deactivate(dev); |
||||
|
||||
debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n", |
||||
__func__, tmpdin, readl(®s->fifo_status)); |
||||
|
||||
if (ret) { |
||||
printf("%s: timeout during SPI transfer, tm %d\n", |
||||
__func__, ret); |
||||
return -1; |
||||
} |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static int tegra210_qspi_set_speed(struct udevice *bus, uint speed) |
||||
{ |
||||
struct tegra_spi_platdata *plat = bus->platdata; |
||||
struct tegra210_qspi_priv *priv = dev_get_priv(bus); |
||||
|
||||
if (speed > plat->frequency) |
||||
speed = plat->frequency; |
||||
priv->freq = speed; |
||||
debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int tegra210_qspi_set_mode(struct udevice *bus, uint mode) |
||||
{ |
||||
struct tegra210_qspi_priv *priv = dev_get_priv(bus); |
||||
|
||||
priv->mode = mode; |
||||
debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct dm_spi_ops tegra210_qspi_ops = { |
||||
.claim_bus = tegra210_qspi_claim_bus, |
||||
.xfer = tegra210_qspi_xfer, |
||||
.set_speed = tegra210_qspi_set_speed, |
||||
.set_mode = tegra210_qspi_set_mode, |
||||
/*
|
||||
* cs_info is not needed, since we require all chip selects to be |
||||
* in the device tree explicitly |
||||
*/ |
||||
}; |
||||
|
||||
static const struct udevice_id tegra210_qspi_ids[] = { |
||||
{ .compatible = "nvidia,tegra210-qspi" }, |
||||
{ } |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(tegra210_qspi) = { |
||||
.name = "tegra210-qspi", |
||||
.id = UCLASS_SPI, |
||||
.of_match = tegra210_qspi_ids, |
||||
.ops = &tegra210_qspi_ops, |
||||
.ofdata_to_platdata = tegra210_qspi_ofdata_to_platdata, |
||||
.platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata), |
||||
.priv_auto_alloc_size = sizeof(struct tegra210_qspi_priv), |
||||
.per_child_auto_alloc_size = sizeof(struct spi_slave), |
||||
.probe = tegra210_qspi_probe, |
||||
}; |
||||
Loading…
Reference in new issue