@ -5,13 +5,13 @@
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
* Copyright 2004 - 2010 Analog Devices Inc .
* Copyright 2004 - 2011 Analog Devices Inc .
* Licensed under the ADI BSD license .
* https : //docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
* - Revision J , 06 / 03 / 2010 ; ADSP - BF542 / BF544 / BF547 / BF548 / BF549 Blackfin Processor Anomaly List
* - Revision K , 05 / 23 / 2011 ; ADSP - BF542 / BF544 / BF547 / BF548 / BF549 Blackfin Processor Anomaly List
*/
# ifndef _MACH_ANOMALY_H_
@ -31,111 +31,37 @@
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
# define ANOMALY_05000122 (1)
/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
# define ANOMALY_05000220 (1 )
# define ANOMALY_05000220 (__SILICON_REVISION__ < 4 )
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
# define ANOMALY_05000245 (1)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
# define ANOMALY_05000265 (1)
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
# define ANOMALY_05000272 (1)
/* False Hardware Error Exception when ISR Context Is Not Restored */
# define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
# define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
# define ANOMALY_05000310 (1)
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
# define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
/* TWI Slave Boot Mode Is Not Functional */
# define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
/* FIFO Boot Mode Not Functional */
# define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
# define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
/* Incorrect Access of OTP_STATUS During otp_write() Function */
# define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
/* Synchronous Burst Flash Boot Mode Is Not Functional */
# define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
/* Host DMA Boot Modes Are Not Functional */
# define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
# define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
/* Inadequate Rotary Debounce Logic Duration */
# define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
# define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
# define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
# define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
# define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
# define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
/* USB Calibration Value Is Not Initialized */
# define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
/* USB Calibration Value to use */
# define ANOMALY_05000346_value 0x5411
/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
# define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
/* Data Lost when Core Reads SDH Data FIFO */
# define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
/* PLL Status Register Is Inaccurate */
# define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
# define ANOMALY_05000353 (__SILICON_REVISION__ < 2)
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
# define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
# define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
/*
* Note : anomaly sheet says this is fixed with bf54x - 0.2 + , but testing
* shows that the fix itself does not cover all cases .
*/
# define ANOMALY_05000353 (1)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
# define ANOMALY_05000357 (1)
/* External Memory Read Access Hangs Core With PLL Bypass */
# define ANOMALY_05000360 (1)
/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
# define ANOMALY_05000365 (1)
/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
# define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
/* Addressing Conflict between Boot ROM and Asynchronous Memory */
# define ANOMALY_05000369 (1)
/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
# define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
# define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
# define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
# define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
# define ANOMALY_05000379 (1)
/* 8-Bit NAND Flash Boot Mode Not Functional */
# define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
/* Boot from OTP Memory Not Functional */
# define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
/* bfrom_SysControl() Firmware Routine Not Functional */
# define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
/* Programmable Preboot Settings Not Functional */
# define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
/* CRC32 Checksum Support Not Functional */
# define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
/* Reset Vector Must Not Be in SDRAM Memory Space */
# define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
/* Changed Meaning of BCODE Field in SYSCR Register */
# define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
# define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
# define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
# define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
/* Log Buffer Not Functional */
# define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
/* Hook Routine Not Functional */
# define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
/* Header Indirect Bit Not Functional */
# define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
# define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
/* Lockbox SESR Disallows Certain User Interrupts */
# define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
@ -157,7 +83,7 @@
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
# define ANOMALY_05000416 (1)
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
# define ANOMALY_05000425 (1 )
# define ANOMALY_05000425 (__SILICON_REVISION__ < 4 )
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
# define ANOMALY_05000426 (1)
/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
@ -170,8 +96,6 @@
# define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
# define ANOMALY_05000434 (1)
/* OTP Write Accesses Not Supported */
# define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
# define ANOMALY_05000443 (1)
/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
@ -182,34 +106,32 @@
# define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
# define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
/* USB DMA Mode 1 Short Packet Data Corruption */
/* USB DMA Short Packet Data Corruption */
# define ANOMALY_05000450 (1)
/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
# define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
# define ANOMALY_05000456 (1)
/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
# define ANOMALY_05000457 (1)
/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
# define ANOMALY_05000460 (1 )
# define ANOMALY_05000460 (__SILICON_REVISION__ < 4 )
/* False Hardware Error when RETI Points to Invalid Memory */
# define ANOMALY_05000461 (1)
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
# define ANOMALY_05000462 (1 )
# define ANOMALY_05000462 (__SILICON_REVISION__ < 4 )
/* USB DMA RX Data Corruption */
# define ANOMALY_05000463 (1 )
# define ANOMALY_05000463 (__SILICON_REVISION__ < 4 )
/* USB TX DMA Hang */
# define ANOMALY_05000464 (1 )
/* USB Rx DMA h ang */
# define ANOMALY_05000464 (__SILICON_REVISION__ < 4 )
/* USB Rx DMA H ang */
# define ANOMALY_05000465 (1)
/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
# define ANOMALY_05000466 (1 )
/* Possible RX data corruption when control & data EP FIFOs are accessed via the c ore */
# define ANOMALY_05000467 (1 )
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
# define ANOMALY_05000466 (__SILICON_REVISION__ < 4 )
/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the C ore */
# define ANOMALY_05000467 (__SILICON_REVISION__ < 4 )
/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
# define ANOMALY_05000473 (1)
/* Access to DDR-SDRAM causes system hang under certain PLL/VR s ettings */
# define ANOMALY_05000474 (1 )
/* Access to DDR SDRAM Causes System Hang with Certain PLL S ettings */
# define ANOMALY_05000474 (__SILICON_REVISION__ < 4 )
/* TESTSET Instruction Cannot Be Interrupted */
# define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
@ -219,9 +141,111 @@
/* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */
# define ANOMALY_05000484 (__SILICON_REVISION__ < 3)
/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
# define ANOMALY_05000485 (__SILICON_REVISION__ >= 2)
/* IFLUSH sucks at life */
# define ANOMALY_05000485 (__SILICON_REVISION__ > 1 && __SILICON_REVISION__ < 4)
/* PLL May Latch Incorrect Values Coming Out of Reset */
# define ANOMALY_05000489 (1)
/* SPI Master Boot Can Fail Under Certain Conditions */
# define ANOMALY_05000490 (1)
/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
# define ANOMALY_05000491 (1)
/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
# define ANOMALY_05000494 (1)
/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
# define ANOMALY_05000498 (1)
/* Nand Flash Controller Hangs When the AMC Requests the Async Pins During the last 16 Bytes of a Page Write Operation. */
# define ANOMALY_05000500 (1)
/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
# define ANOMALY_05000501 (1)
/* Async Memory Writes May Be Skipped When Using Odd Clock Ratios */
# define ANOMALY_05000502 (1)
/*
* These anomalies have been " phased " out of analog . com anomaly sheets and are
* here to show running on older silicon just isn ' t feasible .
*/
/* False Hardware Error when ISR Context Is Not Restored */
# define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
# define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
# define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
/* TWI Slave Boot Mode Is Not Functional */
# define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
# define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
/* Incorrect Access of OTP_STATUS During otp_write() Function */
# define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
/* Synchronous Burst Flash Boot Mode Is Not Functional */
# define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
/* Host DMA Boot Modes Are Not Functional */
# define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
# define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
/* Inadequate Rotary Debounce Logic Duration */
# define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
# define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
# define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
# define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
# define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
# define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
/* USB Calibration Value Is Not Initialized */
# define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
/* USB Calibration Value to use */
# define ANOMALY_05000346_value 0x5411
/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
# define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
/* Data Lost when Core Reads SDH Data FIFO */
# define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
/* PLL Status Register Is Inaccurate */
# define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
# define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
# define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
# define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
# define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
# define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
/* 8-Bit NAND Flash Boot Mode Not Functional */
# define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
/* Boot from OTP Memory Not Functional */
# define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
/* bfrom_SysControl() Firmware Routine Not Functional */
# define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
/* Programmable Preboot Settings Not Functional */
# define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
/* CRC32 Checksum Support Not Functional */
# define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
/* Reset Vector Must Not Be in SDRAM Memory Space */
# define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
/* Changed Meaning of BCODE Field in SYSCR Register */
# define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
# define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
# define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
# define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
/* Log Buffer Not Functional */
# define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
/* Hook Routine Not Functional */
# define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
/* Header Indirect Bit Not Functional */
# define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
# define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
/* OTP Write Accesses Not Supported */
# define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
# define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
/* Anomalies that don't exist on this proc */
# define ANOMALY_05000099 (0)
@ -274,5 +298,6 @@
# define ANOMALY_05000435 (0)
# define ANOMALY_05000440 (0)
# define ANOMALY_05000475 (0)
# define ANOMALY_05000480 (0)
# endif
Mike Frysinger
14 years ago