This platform has been marked as orphaned since September 2013, remove. Signed-off-by: Tom Rini <trini@konsulko.com>lime2-spi
Tom Rini
6 years ago
committed by
Stefano Babic
parent
ebca6013c0
commit
bcca8aa9ee
@ -1,12 +0,0 @@ |
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if TARGET_IMX31_PHYCORE || TARGET_IMX31_PHYCORE_EET |
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config SYS_BOARD |
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default "imx31_phycore" |
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config SYS_SOC |
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default "mx31" |
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config SYS_CONFIG_NAME |
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default "imx31_phycore" |
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endif |
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@ -1,11 +0,0 @@ |
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IMX31_PHYCORE BOARD |
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#M: - |
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S: Maintained |
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F: board/imx31_phycore/ |
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F: include/configs/imx31_phycore.h |
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F: configs/imx31_phycore_defconfig |
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IMX31_PHYCORE_EET BOARD |
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#M: (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de> |
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S: Orphan (since 2013-09) |
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F: configs/imx31_phycore_eet_defconfig |
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@ -1,9 +0,0 @@ |
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := imx31_phycore.o
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obj-y += lowlevel_init.o
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@ -1,154 +0,0 @@ |
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/*
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* |
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <s6e63d6.h> |
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#include <netdev.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/imx-regs.h> |
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#include <asm/mach-types.h> |
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#include <asm/arch/sys_proto.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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int dram_init(void) |
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{ |
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/* dram_init must store complete ramsize in gd->ram_size */ |
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, |
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PHYS_SDRAM_1_SIZE); |
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return 0; |
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} |
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int board_init(void) |
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{ |
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gd->bd->bi_arch_number = MACH_TYPE_PCM037; /* board id for linux */ |
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gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */ |
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return 0; |
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} |
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int board_early_init_f(void) |
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{ |
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/* CS0: Nor Flash */ |
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static const struct mxc_weimcs cs0 = { |
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ |
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3), |
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ |
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CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1), |
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ |
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CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0) |
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}; |
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|
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/* CS1: Network Controller */ |
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static const struct mxc_weimcs cs1 = { |
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ |
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 31, 0, 0, 6), |
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ |
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CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1), |
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ |
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CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0) |
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}; |
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|
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/* CS4: SRAM */ |
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static const struct mxc_weimcs cs4 = { |
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/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ |
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CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3), |
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/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ |
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CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1), |
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/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ |
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CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0) |
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}; |
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mxc_setup_weimcs(0, &cs0); |
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mxc_setup_weimcs(1, &cs1); |
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mxc_setup_weimcs(4, &cs4); |
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/* setup pins for UART1 */ |
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mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); |
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mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); |
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mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); |
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mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); |
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/* setup pins for I2C2 (for EEPROM, RTC) */ |
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mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL); |
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mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA); |
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return 0; |
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} |
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#ifdef CONFIG_BOARD_LATE_INIT |
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int board_late_init(void) |
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{ |
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#ifdef CONFIG_S6E63D6 |
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struct s6e63d6 data = { |
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/*
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* See comment in mxc_spi.c::decode_cs() for .cs field format. |
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* We use GPIO 57 as a chipselect for the S6E63D6 and chipselect |
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* 2 of the SPI controller #1, since it is unused. |
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*/ |
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.cs = 2 | (57 << 8), |
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.bus = 0, |
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.id = 0, |
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}; |
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int ret; |
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/* SPI1 */ |
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mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK); |
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mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B); |
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mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI); |
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mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO); |
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mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B); |
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mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B); |
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mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B); |
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/* start SPI1 clock */ |
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__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2); |
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/* GPIO 57 */ |
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/* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */ |
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mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO)); |
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/* SPI1 CS2 is free */ |
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ret = s6e63d6_init(&data); |
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if (ret) |
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return ret; |
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/*
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* This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC |
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* OLED display connected to a S6E63D6 SPI display controller in the |
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* 18 bit RGB mode |
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*/ |
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s6e63d6_index(&data, 2); |
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s6e63d6_param(&data, 0x0182); |
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s6e63d6_index(&data, 3); |
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s6e63d6_param(&data, 0x8130); |
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s6e63d6_index(&data, 0x10); |
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s6e63d6_param(&data, 0x0000); |
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s6e63d6_index(&data, 5); |
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s6e63d6_param(&data, 0x0001); |
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s6e63d6_index(&data, 0x22); |
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#endif |
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return 0; |
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} |
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#endif |
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int checkboard (void) |
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{ |
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printf("Board: Phytec phyCore i.MX31\n"); |
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return 0; |
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} |
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int board_eth_init(bd_t *bis) |
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{ |
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int rc = 0; |
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#ifdef CONFIG_SMC911X |
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); |
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#endif |
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return rc; |
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} |
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@ -1,88 +0,0 @@ |
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/* |
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* |
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <asm/arch/imx-regs.h> |
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.macro REG reg, val |
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ldr r2, =\reg |
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ldr r3, =\val |
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str r3, [r2] |
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.endm |
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.macro REG8 reg, val |
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ldr r2, =\reg |
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ldr r3, =\val |
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strb r3, [r2] |
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.endm |
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.macro DELAY loops |
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ldr r2, =\loops |
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1: |
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subs r2, r2, #1 |
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nop |
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bcs 1b |
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.endm |
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.globl lowlevel_init
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lowlevel_init: |
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REG IPU_CONF, IPU_CONF_DI_EN |
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REG CCM_CCMR, 0x074B0BF5 |
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DELAY 0x40000 |
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REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE |
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REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS |
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REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0) |
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REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd) |
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REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1) |
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REG 0x43FAC26C, 0 /* SDCLK */ |
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REG 0x43FAC270, 0 /* CAS */ |
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REG 0x43FAC274, 0 /* RAS */ |
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REG 0x43FAC27C, 0x1000 /* CS2 (CSD0) */ |
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REG 0x43FAC284, 0 /* DQM3 */ |
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REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */ |
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REG 0x43FAC28C, 0 |
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REG 0x43FAC290, 0 |
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REG 0x43FAC294, 0 |
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REG 0x43FAC298, 0 |
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REG 0x43FAC29C, 0 |
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REG 0x43FAC2A0, 0 |
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REG 0x43FAC2A4, 0 |
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REG 0x43FAC2A8, 0 |
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REG 0x43FAC2AC, 0 |
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REG 0x43FAC2B0, 0 |
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REG 0x43FAC2B4, 0 |
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REG 0x43FAC2B8, 0 |
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REG 0x43FAC2BC, 0 |
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REG 0x43FAC2C0, 0 |
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REG 0x43FAC2C4, 0 |
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REG 0x43FAC2C8, 0 |
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REG 0x43FAC2CC, 0 |
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REG 0x43FAC2D0, 0 |
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REG 0x43FAC2D4, 0 |
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REG 0x43FAC2D8, 0 |
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REG 0x43FAC2DC, 0 |
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REG 0xB8001010, 0x00000004 |
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REG 0xB8001004, 0x006ac73a |
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REG 0xB8001000, 0x92100000 |
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REG 0x80000f00, 0x12344321 |
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REG 0xB8001000, 0xa2100000 |
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REG 0x80000000, 0x12344321 |
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REG 0x80000000, 0x12344321 |
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REG 0xB8001000, 0xb2100000 |
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REG8 0x80000033, 0xda |
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REG8 0x81000000, 0xff |
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REG 0xB8001000, 0x82226080 |
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REG 0x80000000, 0xDEADBEEF |
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REG 0xB8001010, 0x0000000c |
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mov pc, lr |
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@ -1,19 +0,0 @@ |
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CONFIG_ARM=y |
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CONFIG_TARGET_IMX31_PHYCORE=y |
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CONFIG_SYS_TEXT_BASE=0xA0000000 |
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CONFIG_BOOTDELAY=3 |
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# CONFIG_AUTO_COMPLETE is not set |
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CONFIG_SYS_PROMPT="uboot> " |
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CONFIG_CMD_IMLS=y |
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CONFIG_CMD_EEPROM=y |
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CONFIG_CMD_I2C=y |
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# CONFIG_CMD_SETEXPR is not set |
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CONFIG_CMD_PING=y |
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CONFIG_MTDPARTS_DEFAULT="mtdparts=physmap-flash.0:128k(uboot)ro,1536k(kernel),-(root)" |
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CONFIG_ENV_IS_IN_EEPROM=y |
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# CONFIG_MMC is not set |
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CONFIG_MTD_NOR_FLASH=y |
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CONFIG_NETDEVICES=y |
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CONFIG_SMC911X=y |
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CONFIG_SMC911X_BASE=0xa8000000 |
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CONFIG_SMC911X_32_BIT=y |
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@ -1,25 +0,0 @@ |
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CONFIG_ARM=y |
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CONFIG_TARGET_IMX31_PHYCORE_EET=y |
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CONFIG_SYS_TEXT_BASE=0xA0000000 |
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CONFIG_BOOTDELAY=3 |
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# CONFIG_CONSOLE_MUX is not set |
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CONFIG_SYS_CONSOLE_IS_IN_ENV=y |
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# CONFIG_AUTO_COMPLETE is not set |
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CONFIG_CMD_IMLS=y |
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CONFIG_CMD_EEPROM=y |
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CONFIG_CMD_I2C=y |
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CONFIG_CMD_SPI=y |
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# CONFIG_CMD_SETEXPR is not set |
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CONFIG_CMD_PING=y |
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CONFIG_CMD_BMP=y |
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CONFIG_MTDPARTS_DEFAULT="mtdparts=physmap-flash.0:128k(uboot)ro,1536k(kernel),-(root)" |
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CONFIG_ENV_IS_IN_EEPROM=y |
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CONFIG_MXC_GPIO=y |
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# CONFIG_MMC is not set |
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CONFIG_MTD_NOR_FLASH=y |
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CONFIG_NETDEVICES=y |
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CONFIG_SMC911X=y |
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CONFIG_SMC911X_BASE=0xa8000000 |
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CONFIG_SMC911X_32_BIT=y |
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CONFIG_MXC_SPI=y |
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CONFIG_VIDEO=y |
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@ -1,60 +0,0 @@ |
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/*
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* Copyright (C) 2009 |
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* Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <spi.h> |
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#include <s6e63d6.h> |
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/*
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* Each transfer is performed as: |
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* 1. chip-select active |
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* 2. send 8-bit start code |
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* 3. send 16-bit data |
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* 4. chip-select inactive |
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*/ |
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static int send_word(struct s6e63d6 *data, u8 rs, u16 word) |
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{ |
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/*
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* The start byte looks like (binary): |
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* 01110<ID><RS><R/W> |
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* RS is 0 for index or 1 for data, and R/W is 0 for write. |
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*/ |
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u32 buf8 = 0x70 | data->id | (rs & 2); |
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u32 buf16 = cpu_to_le16(word); |
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u32 buf_in; |
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int err; |
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err = spi_xfer(data->slave, 8, &buf8, &buf_in, SPI_XFER_BEGIN); |
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if (err) |
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return err; |
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return spi_xfer(data->slave, 16, &buf16, &buf_in, SPI_XFER_END); |
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} |
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/* Index and param differ in Register Select bit */ |
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int s6e63d6_index(struct s6e63d6 *data, u8 idx) |
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{ |
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return send_word(data, 0, idx); |
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} |
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int s6e63d6_param(struct s6e63d6 *data, u16 param) |
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{ |
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return send_word(data, 2, param); |
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} |
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int s6e63d6_init(struct s6e63d6 *data) |
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{ |
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if (data->id != 0 && data->id != 4) { |
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printf("s6e63d6: invalid ID %u\n", data->id); |
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return 1; |
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} |
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data->slave = spi_setup_slave(data->bus, data->cs, 100000, SPI_MODE_3); |
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if (!data->slave) |
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return 1; |
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return 0; |
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} |
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@ -1,156 +0,0 @@ |
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/*
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* (C) Copyright 2004 |
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* Texas Instruments. |
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* Richard Woodruff <r-woodruff2@ti.com> |
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* Kshitij Gupta <kshitij@ti.com> |
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* |
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* Configuration settings for the phyCORE-i.MX31 board. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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#include <asm/arch/imx-regs.h> |
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/* High Level Configuration Options */ |
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#define CONFIG_MX31 /* This is a mx31 */ |
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#define CONFIG_MX31_CLK32 32000 |
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
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#define CONFIG_SETUP_MEMORY_TAGS |
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#define CONFIG_INITRD_TAG |
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/*
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* Size of malloc() pool |
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*/ |
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024) |
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/*
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* Hardware drivers |
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*/ |
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#define CONFIG_SYS_I2C |
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#define CONFIG_SYS_I2C_MXC |
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ |
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#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
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#define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET |
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#define CONFIG_MXC_UART |
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#define CONFIG_MXC_UART_BASE UART1_BASE |
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/* allow to overwrite serial and ethaddr */ |
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#define CONFIG_ENV_OVERWRITE |
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#define CONFIG_CONS_INDEX 1 |
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/***********************************************************
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* Command definition |
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***********************************************************/ |
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#define CONFIG_NETMASK 255.255.255.0 |
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#define CONFIG_IPADDR 192.168.23.168 |
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#define CONFIG_SERVERIP 192.168.23.2 |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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"bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
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"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
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"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
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"bootargs_flash=setenv bootargs $(bootargs) " \
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"root=/dev/mtdblock2 rootfstype=jffs2\0" \
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"bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0" \
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"bootcmd=run bootcmd_net\0" \
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"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;" \
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"tftpboot 0x80000000 $(uimage);bootm\0" \
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"bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;" \
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"bootm 0x80000000\0" \
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"unlock=yes\0" \
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"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
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"prg_uboot=tftpboot 0x80000000 $(uboot);" \
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"protect off 0xa0000000 +0x20000;" \
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"erase 0xa0000000 +0x20000;" \
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"cp.b 0x80000000 0xa0000000 $(filesize)\0" \
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"prg_kernel=tftpboot 0x80000000 $(uimage);" \
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"erase 0xa0040000 +0x180000;" \
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"cp.b 0x80000000 0xa0040000 $(filesize)\0" \
|
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"prg_jffs2=tftpboot 0x80000000 $(jffs2);" \
|
||||
"erase 0xa01c0000 0xa1ffffff;" \
|
||||
"cp.b 0x80000000 0xa01c0000 $(filesize)\0" \
|
||||
"videomode=video=ctfb:x:240,y:320,depth:16,mode:0," \
|
||||
"pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1," \
|
||||
"sync:1241513985,vmode:0\0" |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x10000 |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0 /* default load address */ |
||||
|
||||
/*
|
||||
* Physical Memory Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM_1 0x80000000 |
||||
#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
||||
GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
||||
CONFIG_SYS_GBL_DATA_OFFSET) |
||||
|
||||
/*
|
||||
* FLASH and environment organization |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_BASE 0xa0000000 |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max # of sectors/chip */ |
||||
/* Monitor at beginning of flash */ |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
||||
|
||||
#define CONFIG_ENV_OFFSET 0x00 /* env. starts here */ |
||||
#define CONFIG_ENV_SIZE 4096 |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */ |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10 ms delay */ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* byte addr. lenght */ |
||||
|
||||
/*
|
||||
* CFI FLASH driver setup |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ |
||||
#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/mtd/cfi_flash.c */ |
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */ |
||||
#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */ |
||||
|
||||
/*
|
||||
* Timeout for Flash Erase and Flash Write |
||||
* timeout values are in ticks |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) |
||||
|
||||
/*
|
||||
* JFFS2 partitions |
||||
*/ |
||||
#define CONFIG_JFFS2_DEV "nor0" |
||||
|
||||
/* EET platform additions */ |
||||
#ifdef CONFIG_TARGET_IMX31_PHYCORE_EET |
||||
#define CONFIG_HARD_SPI |
||||
|
||||
#define CONFIG_S6E63D6 |
||||
|
||||
#define CONFIG_VIDEO_MX3 |
||||
#define CONFIG_VIDEO_LOGO |
||||
#define CONFIG_SPLASH_SCREEN |
||||
#define CONFIG_BMP_16BPP |
||||
#endif |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -1,21 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2009 |
||||
* Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#ifndef _S6E63D6_H_ |
||||
#define _S6E63D6_H_ |
||||
|
||||
struct s6e63d6 { |
||||
unsigned int bus; |
||||
unsigned int cs; |
||||
unsigned int id; |
||||
struct spi_slave *slave; |
||||
}; |
||||
|
||||
extern int s6e63d6_init(struct s6e63d6 *data); |
||||
extern int s6e63d6_index(struct s6e63d6 *data, u8 idx); |
||||
extern int s6e63d6_param(struct s6e63d6 *data, u16 param); |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue