Add initial support for the R8A7795 and R8A7796 based ULCB board. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>master
Marek Vasut
7 years ago
committed by
Nobuhiro Iwamatsu
parent
c65e46dab0
commit
bd39050cb2
@ -0,0 +1,15 @@ |
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if TARGET_ULCB |
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config SYS_SOC |
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default "rmobile" |
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config SYS_BOARD |
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default "ulcb" |
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config SYS_VENDOR |
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default "renesas" |
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config SYS_CONFIG_NAME |
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default "ulcb" |
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endif |
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@ -0,0 +1,7 @@ |
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ULCB BOARD |
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M: Marek Vasut <marek.vasut+renesas@gmail.com> |
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S: Maintained |
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F: board/renesas/ulcb/ |
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F: include/configs/ulcb.h |
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F: configs/r8a7795_ulcb_defconfig |
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F: configs/r8a7796_ulcb_defconfig |
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@ -0,0 +1,9 @@ |
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#
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# board/renesas/ulcb/Makefile
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#
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# Copyright (C) 2017 Renesas Electronics Corporation
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := ulcb.o cpld.o ../rcar-common/common.o
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@ -0,0 +1,167 @@ |
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/*
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* ULCB board CPLD access support |
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* |
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* Copyright (C) 2017 Renesas Electronics Corporation |
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* Copyright (C) 2017 Cogent Embedded, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <spi.h> |
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#include <asm/io.h> |
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#include <asm/gpio.h> |
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#define SCLK GPIO_GP_6_8 |
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#define SSTBZ GPIO_GP_2_3 |
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#define MOSI GPIO_GP_6_7 |
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#define MISO GPIO_GP_6_10 |
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#define CPLD_ADDR_MODE 0x00 /* RW */ |
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#define CPLD_ADDR_MUX 0x02 /* RW */ |
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#define CPLD_ADDR_DIPSW6 0x08 /* R */ |
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#define CPLD_ADDR_RESET 0x80 /* RW */ |
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#define CPLD_ADDR_VERSION 0xFF /* R */ |
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static int cpld_initialized; |
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int spi_cs_is_valid(unsigned int bus, unsigned int cs) |
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{ |
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/* Always valid */ |
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return 1; |
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} |
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void spi_cs_activate(struct spi_slave *slave) |
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{ |
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/* Always active */ |
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} |
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void spi_cs_deactivate(struct spi_slave *slave) |
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{ |
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/* Always active */ |
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} |
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void ulcb_softspi_sda(int set) |
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{ |
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gpio_set_value(MOSI, set); |
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} |
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void ulcb_softspi_scl(int set) |
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{ |
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gpio_set_value(SCLK, set); |
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} |
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unsigned char ulcb_softspi_read(void) |
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{ |
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return !!gpio_get_value(MISO); |
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} |
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static void cpld_rw(u8 write) |
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{ |
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gpio_set_value(MOSI, write); |
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gpio_set_value(SSTBZ, 0); |
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gpio_set_value(SCLK, 1); |
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gpio_set_value(SCLK, 0); |
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gpio_set_value(SSTBZ, 1); |
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} |
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static u32 cpld_read(u8 addr) |
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{ |
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u32 data = 0; |
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spi_xfer(NULL, 8, &addr, NULL, SPI_XFER_BEGIN | SPI_XFER_END); |
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cpld_rw(0); |
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spi_xfer(NULL, 32, NULL, &data, SPI_XFER_BEGIN | SPI_XFER_END); |
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return swab32(data); |
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} |
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static void cpld_write(u8 addr, u32 data) |
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{ |
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data = swab32(data); |
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spi_xfer(NULL, 32, &data, NULL, SPI_XFER_BEGIN | SPI_XFER_END); |
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spi_xfer(NULL, 8, NULL, &addr, SPI_XFER_BEGIN | SPI_XFER_END); |
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cpld_rw(1); |
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} |
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static void cpld_init(void) |
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{ |
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if (cpld_initialized) |
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return; |
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/* PULL-UP on MISO line */ |
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setbits_le32(PFC_PUEN5, PUEN_SSI_SDATA4); |
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gpio_request(SCLK, NULL); |
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gpio_request(SSTBZ, NULL); |
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gpio_request(MOSI, NULL); |
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gpio_request(MISO, NULL); |
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gpio_direction_output(SCLK, 0); |
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gpio_direction_output(SSTBZ, 1); |
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gpio_direction_output(MOSI, 0); |
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gpio_direction_input(MISO); |
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/* Dummy read */ |
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cpld_read(CPLD_ADDR_VERSION); |
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cpld_initialized = 1; |
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} |
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static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
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{ |
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u32 addr, val; |
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cpld_init(); |
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if (argc == 2 && strcmp(argv[1], "info") == 0) { |
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printf("CPLD version:\t\t\t0x%08x\n", |
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cpld_read(CPLD_ADDR_VERSION)); |
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printf("H3 Mode setting (MD0..28):\t0x%08x\n", |
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cpld_read(CPLD_ADDR_MODE)); |
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printf("Multiplexer settings:\t\t0x%08x\n", |
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cpld_read(CPLD_ADDR_MUX)); |
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printf("DIPSW (SW6):\t\t\t0x%08x\n", |
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cpld_read(CPLD_ADDR_DIPSW6)); |
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return 0; |
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} |
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if (argc < 3) |
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return CMD_RET_USAGE; |
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addr = simple_strtoul(argv[2], NULL, 16); |
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if (!(addr == CPLD_ADDR_VERSION || addr == CPLD_ADDR_MODE || |
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addr == CPLD_ADDR_MUX || addr == CPLD_ADDR_DIPSW6 || |
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addr == CPLD_ADDR_RESET)) { |
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printf("Invalid CPLD register address\n"); |
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return CMD_RET_USAGE; |
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} |
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if (argc == 3 && strcmp(argv[1], "read") == 0) { |
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printf("0x%x\n", cpld_read(addr)); |
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} else if (argc == 4 && strcmp(argv[1], "write") == 0) { |
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val = simple_strtoul(argv[3], NULL, 16); |
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cpld_write(addr, val); |
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} |
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return 0; |
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} |
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U_BOOT_CMD( |
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cpld, 4, 1, do_cpld, |
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"CPLD access", |
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"info\n" |
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"cpld read addr\n" |
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"cpld write addr val\n" |
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); |
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void reset_cpu(ulong addr) |
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{ |
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cpld_init(); |
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cpld_write(CPLD_ADDR_RESET, 1); |
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} |
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@ -0,0 +1,257 @@ |
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/*
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* board/renesas/ulcb/ulcb.c |
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* This file is ULCB board support. |
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* |
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* Copyright (C) 2017 Renesas Electronics Corporation |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <malloc.h> |
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#include <netdev.h> |
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#include <dm.h> |
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#include <dm/platform_data/serial_sh.h> |
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#include <asm/processor.h> |
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#include <asm/mach-types.h> |
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#include <asm/io.h> |
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#include <linux/errno.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/gpio.h> |
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#include <asm/arch/gpio.h> |
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#include <asm/arch/rmobile.h> |
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#include <asm/arch/rcar-mstp.h> |
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#include <asm/arch/sh_sdhi.h> |
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#include <i2c.h> |
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#include <mmc.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define CPGWPCR 0xE6150904 |
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#define CPGWPR 0xE615090C |
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#define CLK2MHZ(clk) (clk / 1000 / 1000) |
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void s_init(void) |
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{ |
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struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; |
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struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; |
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/* Watchdog init */ |
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writel(0xA5A5A500, &rwdt->rwtcsra); |
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writel(0xA5A5A500, &swdt->swtcsra); |
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writel(0xA5A50000, CPGWPCR); |
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writel(0xFFFFFFFF, CPGWPR); |
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} |
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#define GSX_MSTP112 BIT(12) /* 3DG */ |
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#define TMU0_MSTP125 BIT(25) /* secure */ |
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#define TMU1_MSTP124 BIT(24) /* non-secure */ |
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#define SCIF2_MSTP310 BIT(10) /* SCIF2 */ |
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#define ETHERAVB_MSTP812 BIT(12) |
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#define DVFS_MSTP926 BIT(26) |
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#define SD0_MSTP314 BIT(14) |
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#define SD1_MSTP313 BIT(13) |
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#define SD2_MSTP312 BIT(12) /* either MMC0 */ |
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#define SD0CKCR 0xE6150074 |
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#define SD1CKCR 0xE6150078 |
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#define SD2CKCR 0xE6150268 |
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#define SD3CKCR 0xE615026C |
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int board_early_init_f(void) |
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{ |
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/* TMU0,1 */ /* which use ? */ |
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mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124); |
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/* SCIF2 */ |
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mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310); |
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/* EHTERAVB */ |
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mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812); |
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/* eMMC */ |
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mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312); |
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/* SDHI0 */ |
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mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314); |
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writel(0, SD0CKCR); |
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writel(0, SD1CKCR); |
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writel(0, SD2CKCR); |
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writel(0, SD3CKCR); |
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#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) |
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/* DVFS for reset */ |
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mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926); |
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#endif |
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return 0; |
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} |
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/* SYSC */ |
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/* R/- 32 Power status register 2(3DG) */ |
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#define SYSC_PWRSR2 0xE6180100 |
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/* -/W 32 Power resume control register 2 (3DG) */ |
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#define SYSC_PWRONCR2 0xE618010C |
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int board_init(void) |
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{ |
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; |
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/* Init PFC controller */ |
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#if defined(CONFIG_R8A7795) |
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r8a7795_pinmux_init(); |
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#elif defined(CONFIG_R8A7796) |
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r8a7796_pinmux_init(); |
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#endif |
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/* USB1 pull-up */ |
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setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); |
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#ifdef CONFIG_RAVB |
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/* EtherAVB Enable */ |
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/* GPSR2 */ |
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gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL); |
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gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL); |
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gpio_request(GPIO_GFN_AVB_LINK, NULL); |
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gpio_request(GPIO_GFN_AVB_PHY_INT, NULL); |
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gpio_request(GPIO_GFN_AVB_MAGIC, NULL); |
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gpio_request(GPIO_GFN_AVB_MDC, NULL); |
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/* IPSR0 */ |
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gpio_request(GPIO_IFN_AVB_MDC, NULL); |
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gpio_request(GPIO_IFN_AVB_MAGIC, NULL); |
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gpio_request(GPIO_IFN_AVB_PHY_INT, NULL); |
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gpio_request(GPIO_IFN_AVB_LINK, NULL); |
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gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL); |
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gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL); |
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/* IPSR1 */ |
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gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL); |
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/* IPSR2 */ |
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gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL); |
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/* IPSR3 */ |
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gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL); |
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/* AVB_PHY_RST */ |
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gpio_request(GPIO_GP_2_10, NULL); |
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gpio_direction_output(GPIO_GP_2_10, 0); |
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mdelay(20); |
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gpio_set_value(GPIO_GP_2_10, 1); |
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udelay(1); |
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#endif |
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return 0; |
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} |
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static struct eth_pdata salvator_x_ravb_platdata = { |
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.iobase = 0xE6800000, |
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.phy_interface = 0, |
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.max_speed = 1000, |
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}; |
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U_BOOT_DEVICE(salvator_x_ravb) = { |
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.name = "ravb", |
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.platdata = &salvator_x_ravb_platdata, |
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}; |
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#ifdef CONFIG_SH_SDHI |
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int board_mmc_init(bd_t *bis) |
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{ |
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int ret = -ENODEV; |
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/* SDHI0 */ |
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gpio_request(GPIO_GFN_SD0_DAT0, NULL); |
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gpio_request(GPIO_GFN_SD0_DAT1, NULL); |
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gpio_request(GPIO_GFN_SD0_DAT2, NULL); |
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gpio_request(GPIO_GFN_SD0_DAT3, NULL); |
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gpio_request(GPIO_GFN_SD0_CLK, NULL); |
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gpio_request(GPIO_GFN_SD0_CMD, NULL); |
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gpio_request(GPIO_GFN_SD0_CD, NULL); |
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gpio_request(GPIO_GFN_SD0_WP, NULL); |
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gpio_request(GPIO_GP_5_2, NULL); |
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gpio_request(GPIO_GP_5_1, NULL); |
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gpio_direction_output(GPIO_GP_5_2, 1); /* power on */ |
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gpio_direction_output(GPIO_GP_5_1, 1); /* 1: 3.3V, 0: 1.8V */ |
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ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, |
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SH_SDHI_QUIRK_64BIT_BUF); |
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if (ret) |
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return ret; |
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/* SDHI1/SDHI2 eMMC */ |
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gpio_request(GPIO_GFN_SD1_DAT0, NULL); |
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gpio_request(GPIO_GFN_SD1_DAT1, NULL); |
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gpio_request(GPIO_GFN_SD1_DAT2, NULL); |
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gpio_request(GPIO_GFN_SD1_DAT3, NULL); |
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gpio_request(GPIO_GFN_SD2_DAT0, NULL); |
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gpio_request(GPIO_GFN_SD2_DAT1, NULL); |
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gpio_request(GPIO_GFN_SD2_DAT2, NULL); |
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gpio_request(GPIO_GFN_SD2_DAT3, NULL); |
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gpio_request(GPIO_GFN_SD2_CLK, NULL); |
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#if defined(CONFIG_R8A7795) |
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gpio_request(GPIO_GFN_SD2_CMD, NULL); |
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#elif defined(CONFIG_R8A7796) |
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gpio_request(GPIO_FN_SD2_CMD, NULL); |
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#else |
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#error Only R8A7795 and R87796 is supported |
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#endif |
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gpio_request(GPIO_GP_5_3, NULL); |
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gpio_request(GPIO_GP_5_9, NULL); |
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gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */ |
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gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */ |
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ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 1, |
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SH_SDHI_QUIRK_64BIT_BUF); |
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return ret; |
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} |
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#endif |
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int dram_init(void) |
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{ |
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gd->ram_size = PHYS_SDRAM_1_SIZE; |
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#if (CONFIG_NR_DRAM_BANKS >= 2) |
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gd->ram_size += PHYS_SDRAM_2_SIZE; |
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#endif |
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#if (CONFIG_NR_DRAM_BANKS >= 3) |
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gd->ram_size += PHYS_SDRAM_3_SIZE; |
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#endif |
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#if (CONFIG_NR_DRAM_BANKS >= 4) |
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gd->ram_size += PHYS_SDRAM_4_SIZE; |
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#endif |
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return 0; |
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} |
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int dram_init_banksize(void) |
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{ |
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
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#if (CONFIG_NR_DRAM_BANKS >= 2) |
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2; |
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; |
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#endif |
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#if (CONFIG_NR_DRAM_BANKS >= 3) |
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gd->bd->bi_dram[2].start = PHYS_SDRAM_3; |
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gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; |
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#endif |
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#if (CONFIG_NR_DRAM_BANKS >= 4) |
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gd->bd->bi_dram[3].start = PHYS_SDRAM_4; |
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gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; |
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#endif |
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return 0; |
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} |
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const struct rmobile_sysinfo sysinfo = { |
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CONFIG_RCAR_BOARD_STRING |
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}; |
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static const struct sh_serial_platdata serial_platdata = { |
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.base = SCIF2_BASE, |
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.type = PORT_SCIF, |
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.clk = CONFIG_SH_SCIF_CLK_FREQ, |
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.clk_mode = INT_CLK, |
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}; |
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U_BOOT_DEVICE(salvator_x_scif2) = { |
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.name = "serial_sh", |
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.platdata = &serial_platdata, |
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}; |
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@ -0,0 +1,21 @@ |
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CONFIG_ARM=y |
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CONFIG_ARCH_RMOBILE=y |
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CONFIG_SYS_MALLOC_F_LEN=0x2000 |
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CONFIG_RCAR_GEN3=y |
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CONFIG_TARGET_ULCB=y |
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CONFIG_DEFAULT_FDT_FILE="r8a7795-h3ulcb.dtb" |
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CONFIG_VERSION_VARIABLE=y |
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CONFIG_CMD_BOOTZ=y |
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# CONFIG_CMD_IMLS is not set |
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CONFIG_CMD_MMC=y |
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CONFIG_CMD_USB=y |
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CONFIG_CMD_DHCP=y |
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CONFIG_CMD_MII=y |
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CONFIG_CMD_PING=y |
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CONFIG_SH_SDHI=y |
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CONFIG_DM_ETH=y |
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CONFIG_RENESAS_RAVB=y |
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CONFIG_USB=y |
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CONFIG_USB_EHCI_HCD=y |
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CONFIG_USB_STORAGE=y |
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CONFIG_OF_LIBFDT=y |
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@ -0,0 +1,22 @@ |
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CONFIG_ARM=y |
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CONFIG_ARCH_RMOBILE=y |
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CONFIG_SYS_MALLOC_F_LEN=0x2000 |
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CONFIG_RCAR_GEN3=y |
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CONFIG_R8A7796=y |
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CONFIG_TARGET_ULCB=y |
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CONFIG_DEFAULT_FDT_FILE="r8a7796-m3ulcb.dtb" |
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CONFIG_VERSION_VARIABLE=y |
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CONFIG_CMD_BOOTZ=y |
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# CONFIG_CMD_IMLS is not set |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_USB=y |
||||
CONFIG_CMD_DHCP=y |
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CONFIG_CMD_MII=y |
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CONFIG_CMD_PING=y |
||||
CONFIG_SH_SDHI=y |
||||
CONFIG_DM_ETH=y |
||||
CONFIG_RENESAS_RAVB=y |
||||
CONFIG_USB=y |
||||
CONFIG_USB_EHCI_HCD=y |
||||
CONFIG_USB_STORAGE=y |
||||
CONFIG_OF_LIBFDT=y |
||||
@ -0,0 +1,110 @@ |
||||
/*
|
||||
* include/configs/ulcb.h |
||||
* This file is ULCB board configuration. |
||||
* |
||||
* Copyright (C) 2017 Renesas Electronics Corporation |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __ULCB_H |
||||
#define __ULCB_H |
||||
|
||||
#undef DEBUG |
||||
|
||||
#define CONFIG_RCAR_BOARD_STRING "ULCB" |
||||
|
||||
#include "rcar-gen3-common.h" |
||||
|
||||
/* M3 ULCB has 2 banks, each with 1 GiB of RAM */ |
||||
#if defined(CONFIG_R8A7796) |
||||
#undef PHYS_SDRAM_1_SIZE |
||||
#undef PHYS_SDRAM_2_SIZE |
||||
#define PHYS_SDRAM_1_SIZE (0x40000000u - DRAM_RSV_SIZE) |
||||
#define PHYS_SDRAM_2_SIZE 0x40000000u |
||||
#endif |
||||
|
||||
/* SCIF */ |
||||
#define CONFIG_SCIF_CONSOLE |
||||
#define CONFIG_CONS_SCIF2 |
||||
#define CONFIG_CONS_INDEX 2 |
||||
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ |
||||
|
||||
/* [A] Hyper Flash */ |
||||
/* use to RPC(SPI Multi I/O Bus Controller) */ |
||||
|
||||
/* Ethernet RAVB */ |
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_PHY_MICREL |
||||
#define CONFIG_BITBANGMII |
||||
#define CONFIG_BITBANGMII_MULTI |
||||
|
||||
/* Board Clock */ |
||||
/* XTAL_CLK : 33.33MHz */ |
||||
#define RCAR_XTAL_CLK 33333333u |
||||
#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK |
||||
/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */ |
||||
/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */ |
||||
#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) |
||||
#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2) |
||||
#define CONFIG_S3D2_CLK_FREQ (266666666u/2) |
||||
#define CONFIG_S3D4_CLK_FREQ (266666666u/4) |
||||
|
||||
/* Generic Timer Definitions (use in assembler source) */ |
||||
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ |
||||
|
||||
/* Generic Interrupt Controller Definitions */ |
||||
#define CONFIG_GICV2 |
||||
#define GICD_BASE 0xF1010000 |
||||
#define GICC_BASE 0xF1020000 |
||||
|
||||
/* CPLD SPI */ |
||||
#define CONFIG_CMD_SPI |
||||
#define CONFIG_SOFT_SPI |
||||
#define SPI_DELAY udelay(0) |
||||
#define SPI_SDA(val) ulcb_softspi_sda(val) |
||||
#define SPI_SCL(val) ulcb_softspi_scl(val) |
||||
#define SPI_READ ulcb_softspi_read() |
||||
#ifndef __ASSEMBLY__ |
||||
void ulcb_softspi_sda(int); |
||||
void ulcb_softspi_scl(int); |
||||
unsigned char ulcb_softspi_read(void); |
||||
#endif |
||||
|
||||
/* i2c */ |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_SH |
||||
#define CONFIG_SYS_I2C_SLAVE 0x60 |
||||
#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1 |
||||
#define CONFIG_SYS_I2C_SH_SPEED0 400000 |
||||
#define CONFIG_SH_I2C_DATA_HIGH 4 |
||||
#define CONFIG_SH_I2C_DATA_LOW 5 |
||||
#define CONFIG_SH_I2C_CLOCK 10000000 |
||||
|
||||
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30 |
||||
|
||||
/* USB */ |
||||
#ifdef CONFIG_R8A7795 |
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 |
||||
#else |
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
||||
#endif |
||||
|
||||
/* SDHI */ |
||||
#define CONFIG_SH_SDHI_FREQ 200000000 |
||||
|
||||
/* Environment in eMMC, at the end of 2nd "boot sector" */ |
||||
#define CONFIG_ENV_IS_IN_MMC |
||||
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) |
||||
#define CONFIG_SYS_MMC_ENV_DEV 1 |
||||
#define CONFIG_SYS_MMC_ENV_PART 2 |
||||
|
||||
/* Module stop status bits */ |
||||
/* MFIS, SCIF1 */ |
||||
#define CONFIG_SMSTP2_ENA 0x00002040 |
||||
/* SCIF2 */ |
||||
#define CONFIG_SMSTP3_ENA 0x00000400 |
||||
/* INTC-AP, IRQC */ |
||||
#define CONFIG_SMSTP4_ENA 0x00000180 |
||||
|
||||
#endif /* __ULCB_H */ |
||||
Loading…
Reference in new issue