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Migrate esd 405EP boards to new NAND subsystem

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Migrate esd 405EP boards to new NAND subsystem

-cleanup
-use correct io accessors (in/out_be32())

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
master
Matthias Fuchs 18 years ago committed by Stefan Roese
parent e09f7ab574
commit bd84ee4c20
21 changed files with 120 additions and 456 deletions
  1. 4
      board/esd/ash405/Makefile
  2. 43
      board/esd/ash405/ash405.c
  3. 5
      board/esd/cms700/Makefile
  4. 39
      board/esd/cms700/cms700.c
  5. 5
      board/esd/hh405/Makefile
  6. 22
      board/esd/hh405/hh405.c
  7. 4
      board/esd/hub405/Makefile
  8. 34
      board/esd/hub405/hub405.c
  9. 5
      board/esd/plu405/Makefile
  10. 56
      board/esd/plu405/plu405.c
  11. 4
      board/esd/voh405/Makefile
  12. 20
      board/esd/voh405/voh405.c
  13. 4
      board/esd/wuh405/Makefile
  14. 33
      board/esd/wuh405/wuh405.c
  15. 43
      include/configs/ASH405.h
  16. 39
      include/configs/CMS700.h
  17. 39
      include/configs/HH405.h
  18. 39
      include/configs/HUB405.h
  19. 57
      include/configs/PLU405.h
  20. 39
      include/configs/VOH405.h
  21. 42
      include/configs/WUH405.h

4
board/esd/ash405/Makefile
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@ -28,7 +28,9 @@ endif
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o ../common/misc.o
COBJS = $(BOARD).o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

43
board/esd/ash405/ash405.c
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@ -23,6 +23,7 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <command.h>
#include <malloc.h>
@ -33,6 +34,7 @@
#endif
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
extern void lxt971_no_sleep(void);
/* fpga configuration data - gzip compressed and generated by bin2c */
const unsigned char fpgadata[] =
@ -164,18 +166,12 @@ int misc_init_r (void)
/*
* Reset external DUARTs
*/
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST);
udelay(10); /* wait 10us */
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST);
udelay(1000); /* wait 1ms */
/*
* Set NAND-FLASH GPIO signals to default
*/
out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
/*
* Enable interrupts in exar duart mcr[3]
*/
*duart0_mcr = 0x08;
@ -218,35 +214,18 @@ long int initdram (int board_type)
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
#if 0
printf("\nmb0cf=%x\n", val); /* test-only */
printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
/* ------------------------------------------------------------------------- */
int testdram (void)
void reset_phy(void)
{
/* TODO: XXX XXX XXX */
printf ("test: 16 MB - ok\n");
return (0);
}
#ifdef CONFIG_LXT971_NO_SLEEP
/* ------------------------------------------------------------------------- */
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)
{
nand_probe(CFG_NAND_BASE);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
}
/*
* Disable sleep mode in LXT971
*/
lxt971_no_sleep();
#endif
}

5
board/esd/cms700/Makefile
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@ -33,7 +33,10 @@ CPLD = ../common/xilinx_jtag/lenval.o \
../common/xilinx_jtag/micro.o \
../common/xilinx_jtag/ports.o
COBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD)
COBJS = $(BOARD).o flash.o \
../common/misc.o \
$(CPLD) \
../common/esd405ep_nand.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

39
board/esd/cms700/cms700.c
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@ -1,5 +1,5 @@
/*
* (C) Copyright 2005
* (C) Copyright 2005-2007
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
@ -23,6 +23,7 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <command.h>
#include <malloc.h>
@ -68,9 +69,9 @@ int board_early_init_f (void)
/*
* Reset CPLD via GPIO12 (CS3) pin
*/
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET);
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_PLD_RESET);
udelay(1000); /* wait 1ms */
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET);
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_PLD_RESET);
udelay(1000); /* wait 1ms */
return 0;
@ -94,13 +95,7 @@ int misc_init_r (void)
/*
* Setup and enable EEPROM write protection
*/
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
/*
* Set NAND-FLASH GPIO signals to default
*/
out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
return (0);
}
@ -153,11 +148,6 @@ long int initdram (int board_type)
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
#if 0
printf("\nmb0cf=%x\n", val); /* test-only */
printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
@ -180,17 +170,17 @@ int eeprom_write_enable (unsigned dev_addr, int state)
switch (state) {
case 1:
/* Enable write access, clear bit GPIO_SINT2. */
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_EEPROM_WP);
state = 0;
break;
case 0:
/* Disable write access, set bit GPIO_SINT2. */
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
state = 0;
break;
default:
/* Read current status back. */
state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
state = (0 == (in_be32((void *)GPIO0_OR) & CFG_EEPROM_WP));
break;
}
}
@ -235,19 +225,6 @@ U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
/* ------------------------------------------------------------------------- */
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)
{
nand_probe(CFG_NAND_BASE);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
}
#endif
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP

5
board/esd/hh405/Makefile
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@ -28,7 +28,10 @@ endif
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
COBJS = $(BOARD).o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \
../common/auto_update.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

22
board/esd/hh405/hh405.c
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@ -5,7 +5,7 @@
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2006
* (C) Copyright 2006-2007
* Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
@ -477,12 +477,6 @@ int misc_init_r (void)
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
/*
* Set NAND-FLASH GPIO signals to default
*/
out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
/*
* Reset touch-screen controller
*/
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_TOUCH_RST);
@ -690,20 +684,6 @@ void ide_set_reset(int on)
#endif /* CONFIG_IDE_RESET */
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)
{
nand_probe(CFG_NAND_BASE);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
}
#endif
#if defined(CFG_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state

4
board/esd/hub405/Makefile
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@ -28,7 +28,9 @@ endif
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o ../common/misc.o
COBJS = $(BOARD).o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

34
board/esd/hub405/hub405.c
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@ -153,12 +153,6 @@ int misc_init_r (void)
out32(GPIO0_OR, val);
/*
* Set NAND-FLASH GPIO signals to default
*/
out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
/*
* check board type and setup AP power
*/
str = getenv("bd_type"); /* this is only set on non prototype hardware */
@ -242,33 +236,5 @@ long int initdram (int board_type)
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
#if 0
printf("\nmb0cf=%x\n", val); /* test-only */
printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
int testdram (void)
{
/* TODO: XXX XXX XXX */
printf ("test: 16 MB - ok\n");
return (0);
}
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)
{
nand_probe(CFG_NAND_BASE);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
}
#endif

5
board/esd/plu405/Makefile
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@ -28,7 +28,10 @@ endif
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
COBJS = $(BOARD).o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \
../common/auto_update.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

56
board/esd/plu405/plu405.c
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@ -23,6 +23,7 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <command.h>
#include <malloc.h>
@ -31,6 +32,8 @@
#define FPGA_DEBUG
#endif
DECLARE_GLOBAL_DATA_PTR;
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
extern void lxt971_no_sleep(void);
@ -114,6 +117,10 @@ int misc_init_r (void)
int index;
int i;
/* adjust flash start and offset */
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
dst = malloc(CFG_FPGA_MAX_SIZE);
if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
@ -177,18 +184,12 @@ int misc_init_r (void)
/*
* Reset external DUARTs
*/
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST);
udelay(10); /* wait 10us */
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST);
udelay(1000); /* wait 1ms */
/*
* Set NAND-FLASH GPIO signals to default
*/
out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
/*
* Enable interrupts in exar duart mcr[3]
*/
*duart0_mcr = 0x08;
@ -226,24 +227,10 @@ long int initdram (int board_type)
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
#if 0
printf("\nmb0cf=%x\n", val); /* test-only */
printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
int testdram (void)
{
/* TODO: XXX XXX XXX */
printf ("test: 16 MB - ok\n");
return (0);
}
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
@ -262,31 +249,6 @@ void ide_set_reset(int on)
#endif /* CONFIG_IDE_RESET */
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)
{
nand_probe(CFG_NAND_BASE);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
}
#endif
#ifdef CONFIG_AUTO_UPDATE_SHOW
void board_auto_update_show(int au_active)
{
if (au_active) {
printf("\n Dies ist die board-funktion: Updating!!!\n");
} else {
printf("\n Dies ist die board-funktion: Updating done!!!\n");
}
}
#endif
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP

4
board/esd/voh405/Makefile
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@ -28,7 +28,9 @@ endif
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o ../common/misc.o
COBJS = $(BOARD).o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

20
board/esd/voh405/voh405.c
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@ -195,12 +195,6 @@ int misc_init_r (void)
udelay(1000); /* wait 1ms */
/*
* Set NAND-FLASH GPIO signals to default
*/
out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
/*
* Enable interrupts in exar duart mcr[3]
*/
*duart0_mcr = 0x08;
@ -340,17 +334,3 @@ void ide_set_reset(int on)
}
}
#endif /* CONFIG_IDE_RESET */
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)
{
nand_probe(CFG_NAND_BASE);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
}
#endif

4
board/esd/wuh405/Makefile
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@ -28,7 +28,9 @@ endif
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o ../common/misc.o
COBJS = $(BOARD).o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

33
board/esd/wuh405/wuh405.c
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@ -170,12 +170,6 @@ int misc_init_r (void)
udelay(1000); /* wait 1ms */
/*
* Set NAND-FLASH GPIO signals to default
*/
out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
/*
* Enable interrupts in exar duart mcr[3]
*/
*duart0_mcr = 0x08;
@ -218,35 +212,8 @@ long int initdram (int board_type)
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
#if 0
printf("\nmb0cf=%x\n", val); /* test-only */
printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
/* ------------------------------------------------------------------------- */
int testdram (void)
{
/* TODO: XXX XXX XXX */
printf ("test: 16 MB - ok\n");
return (0);
}
/* ------------------------------------------------------------------------- */
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
void nand_init(void)
{
nand_probe(CFG_NAND_BASE);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
}
#endif

43
include/configs/ASH405.h
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@ -53,9 +53,13 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
@ -132,39 +136,16 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
#define CFG_NAND_LEGACY
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
/*-----------------------------------------------------------------------

39
include/configs/CMS700.h
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@ -81,8 +81,6 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
@ -148,34 +146,15 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */

39
include/configs/HH405.h
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@ -130,8 +130,6 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_NAND_LEGACY
#undef CONFIG_BZIP2 /* include support for bzip2 compressed images */
#undef CONFIG_WATCHDOG /* watchdog disabled */
@ -198,34 +196,15 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */

39
include/configs/HUB405.h
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@ -135,36 +135,15 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_NAND_LEGACY
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */

57
include/configs/PLU405.h
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@ -81,7 +81,6 @@
#define CONFIG_SUPPORT_VFAT
#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
#define CONFIG_AUTO_UPDATE_SHOW 1 /* use board show routine */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
@ -156,36 +155,15 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_NAND_LEGACY
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
@ -264,11 +242,6 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#if 0 /* test-only */
#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
#endif
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
@ -294,9 +267,6 @@
#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
/* total size of a CAT24WC16 is 2048 bytes */
#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
#define CFG_NVRAM_SIZE 242 /* NVRAM size */
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
*/
@ -305,7 +275,7 @@
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
#if 1 /* test-only */
/* CAT24WC08/16... */
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
@ -313,15 +283,6 @@
#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
/* 16 byte page write mode using*/
/* last 4 bits of the address */
#else
/* CAT24WC32/64... */
#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
/* 32 byte page write mode using*/
/* last 5 bits of the address */
#endif
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE

39
include/configs/VOH405.h
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@ -141,36 +141,15 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_NAND_LEGACY
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */

42
include/configs/WUH405.h
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@ -133,38 +133,16 @@
* NAND-FLASH stuff
*-----------------------------------------------------------------------
*/
#define CFG_NAND_LEGACY
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0)
#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0)
#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0)
#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0)
#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0)
#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0)
#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY))
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
/*-----------------------------------------------------------------------

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