Wolfgang Denk
15 years ago
commit
be1a91320c
@ -0,0 +1,44 @@ |
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o fpga.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,44 @@ |
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#ifndef __ASTRO_H__ |
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#define __ASTRO_H__ |
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/* in mcf5373l.c */ |
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int rs_serial_init(int port, int baud); |
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void astro_put_char(char ch); |
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int astro_is_char(void); |
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int astro_get_char(void); |
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/* in fpga.c */ |
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int astro5373l_altera_load(void); |
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int astro5373l_xilinx_load(void); |
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/* data structures used for communication (update.c) */ |
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typedef struct card_id { |
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char card_type; |
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char hardware_version; |
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char software_version; |
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char software_subversion; /* " ","a".."z" */ |
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char fpga_version_altera; |
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char fpga_version_xilinx; |
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} card_id_t; |
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typedef struct { |
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unsigned char mode; |
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unsigned char deviation; |
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unsigned short freq; |
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} __attribute__ ((packed)) output_params_t; |
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typedef struct { |
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unsigned short satfreq; |
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unsigned char satdatallg; |
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unsigned short symbolrate; |
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unsigned char viterbirate; |
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unsigned char symbolrate_l; |
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output_params_t output_params; |
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unsigned char reserve; |
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unsigned char card_error; |
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unsigned short dummy_ts_id; |
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unsigned char dummy_pat_ver; |
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unsigned char dummy_sdt_ver; |
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} __attribute__ ((packed)) parameters_t; |
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#endif /* __ASTRO_H__ */ |
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@ -0,0 +1,27 @@ |
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#
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# (C) Copyright 2000-2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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TEXT_BASE = $(CONFIG_TEXT_BASE)
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PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
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@ -0,0 +1,425 @@ |
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/*
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* (C) Copyright 2006 |
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* Wolfgang Wegner, ASTRO Strobel Kommunikationssysteme GmbH, |
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* w.wegner@astro-kom.de |
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* |
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* based on the files by |
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* Heiko Schocher, DENX Software Engineering, hs@denx.de |
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* and |
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com. |
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* Keith Outwater, keith_outwater@mvis.com. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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* |
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*/ |
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/* Altera/Xilinx FPGA configuration support for the ASTRO "URMEL" board */ |
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#include <common.h> |
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#include <watchdog.h> |
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#include <altera.h> |
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#include <ACEX1K.h> |
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#include <spartan3.h> |
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#include <command.h> |
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#include <asm/immap_5329.h> |
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#include <asm/io.h> |
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#include "fpga.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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int altera_pre_fn(int cookie) |
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{ |
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO; |
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unsigned char tmp_char; |
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unsigned short tmp_short; |
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/* first, set the required pins to GPIO function */ |
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/* PAR_T0IN -> GPIO */ |
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tmp_char = readb(&gpiop->par_timer); |
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tmp_char &= 0xfc; |
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writeb(tmp_char, &gpiop->par_timer); |
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/* all QSPI pins -> GPIO */ |
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writew(0x0000, &gpiop->par_qspi); |
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/* U0RTS, U0CTS -> GPIO */ |
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tmp_short = __raw_readw(&gpiop->par_uart); |
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tmp_short &= 0xfff3; |
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__raw_writew(tmp_short, &gpiop->par_uart); |
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/* all PWM pins -> GPIO */ |
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writeb(0x00, &gpiop->par_pwm); |
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/* next, set data direction registers */ |
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writeb(0x01, &gpiop->pddr_timer); |
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writeb(0x25, &gpiop->pddr_qspi); |
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writeb(0x0c, &gpiop->pddr_uart); |
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writeb(0x04, &gpiop->pddr_pwm); |
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/* ensure other SPI peripherals are deselected */ |
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writeb(0x08, &gpiop->ppd_uart); |
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writeb(0x38, &gpiop->ppd_qspi); |
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/* CONFIG = 0 STATUS = 0 -> FPGA in reset state */ |
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writeb(0xFB, &gpiop->pclrr_uart); |
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/* enable Altera configuration by clearing QSPI_CS2 and DT0IN */ |
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writeb(0xFE, &gpiop->pclrr_timer); |
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writeb(0xDF, &gpiop->pclrr_qspi); |
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return FPGA_SUCCESS; |
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} |
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/* Set the state of CONFIG Pin */ |
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int altera_config_fn(int assert_config, int flush, int cookie) |
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{ |
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO; |
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if (assert_config) |
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writeb(0x04, &gpiop->ppd_uart); |
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else |
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writeb(0xFB, &gpiop->pclrr_uart); |
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return FPGA_SUCCESS; |
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} |
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/* Returns the state of STATUS Pin */ |
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int altera_status_fn(int cookie) |
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{ |
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO; |
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if (readb(&gpiop->ppd_pwm) & 0x08) |
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return FPGA_FAIL; |
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return FPGA_SUCCESS; |
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} |
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/* Returns the state of CONF_DONE Pin */ |
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int altera_done_fn(int cookie) |
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{ |
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO; |
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if (readb(&gpiop->ppd_pwm) & 0x20) |
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return FPGA_FAIL; |
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return FPGA_SUCCESS; |
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} |
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/*
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* writes the complete buffer to the FPGA |
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* writing the complete buffer in one function is much faster, |
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* then calling it for every bit |
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*/ |
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int altera_write_fn(void *buf, size_t len, int flush, int cookie) |
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{ |
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size_t bytecount = 0; |
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO; |
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unsigned char *data = (unsigned char *)buf; |
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unsigned char val = 0; |
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int i; |
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int len_40 = len / 40; |
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while (bytecount < len) { |
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val = data[bytecount++]; |
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i = 8; |
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do { |
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writeb(0xFB, &gpiop->pclrr_qspi); |
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if (val & 0x01) |
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writeb(0x01, &gpiop->ppd_qspi); |
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else |
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writeb(0xFE, &gpiop->pclrr_qspi); |
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writeb(0x04, &gpiop->ppd_qspi); |
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val >>= 1; |
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i--; |
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} while (i > 0); |
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if (bytecount % len_40 == 0) { |
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#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) |
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WATCHDOG_RESET(); |
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#endif |
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK |
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putc('.'); /* let them know we are alive */ |
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#endif |
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#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC |
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if (ctrlc()) |
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return FPGA_FAIL; |
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#endif |
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} |
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} |
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return FPGA_SUCCESS; |
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} |
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/* called, when programming is aborted */ |
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int altera_abort_fn(int cookie) |
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{ |
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO; |
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writeb(0x20, &gpiop->ppd_qspi); |
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writeb(0x08, &gpiop->ppd_uart); |
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return FPGA_SUCCESS; |
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} |
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/* called, when programming was succesful */ |
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int altera_post_fn(int cookie) |
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{ |
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return altera_abort_fn(cookie); |
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} |
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/*
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* Note that these are pointers to code that is in Flash. They will be |
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* relocated at runtime. |
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* FIXME: relocation not yet working for coldfire, see below! |
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*/ |
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Altera_CYC2_Passive_Serial_fns altera_fns = { |
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altera_pre_fn, |
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altera_config_fn, |
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altera_status_fn, |
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altera_done_fn, |
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altera_write_fn, |
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altera_abort_fn, |
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altera_post_fn |
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}; |
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Altera_desc altera_fpga[CONFIG_FPGA_COUNT] = { |
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{Altera_CYC2, |
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passive_serial, |
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85903, |
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(void *)&altera_fns, |
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NULL, |
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0} |
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}; |
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/* Initialize the fpga. Return 1 on success, 0 on failure. */ |
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int astro5373l_altera_load(void) |
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{ |
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int i; |
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for (i = 0; i < CONFIG_FPGA_COUNT; i++) { |
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/*
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* I did not yet manage to get relocation work properly, |
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* so set stuff here instead of static initialisation: |
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*/ |
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altera_fns.pre = altera_pre_fn; |
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altera_fns.config = altera_config_fn; |
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altera_fns.status = altera_status_fn; |
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altera_fns.done = altera_done_fn; |
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altera_fns.write = altera_write_fn; |
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altera_fns.abort = altera_abort_fn; |
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altera_fns.post = altera_post_fn; |
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altera_fpga[i].iface_fns = (void *)&altera_fns; |
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fpga_add(fpga_altera, &altera_fpga[i]); |
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} |
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return 1; |
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} |
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/* Set the FPGA's PROG_B line to the specified level */ |
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int xilinx_pgm_fn(int assert, int flush, int cookie) |
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{ |
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO; |
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if (assert) |
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writeb(0xFB, &gpiop->pclrr_uart); |
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else |
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writeb(0x04, &gpiop->ppd_uart); |
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return assert; |
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} |
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/*
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* Test the state of the active-low FPGA INIT line. Return 1 on INIT |
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* asserted (low). |
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*/ |
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int xilinx_init_fn(int cookie) |
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{ |
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO; |
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return (readb(&gpiop->ppd_pwm) & 0x08) == 0; |
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} |
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/* Test the state of the active-high FPGA DONE pin */ |
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int xilinx_done_fn(int cookie) |
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{ |
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO; |
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return (readb(&gpiop->ppd_pwm) & 0x20) >> 5; |
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} |
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/* Abort an FPGA operation */ |
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int xilinx_abort_fn(int cookie) |
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{ |
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO; |
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/* ensure all SPI peripherals and FPGAs are deselected */ |
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writeb(0x08, &gpiop->ppd_uart); |
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writeb(0x01, &gpiop->ppd_timer); |
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writeb(0x38, &gpiop->ppd_qspi); |
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return FPGA_FAIL; |
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} |
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|
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/*
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* FPGA pre-configuration function. Just make sure that |
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* FPGA reset is asserted to keep the FPGA from starting up after |
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* configuration. |
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*/ |
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int xilinx_pre_config_fn(int cookie) |
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{ |
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO; |
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unsigned char tmp_char; |
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unsigned short tmp_short; |
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/* first, set the required pins to GPIO function */ |
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/* PAR_T0IN -> GPIO */ |
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tmp_char = readb(&gpiop->par_timer); |
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tmp_char &= 0xfc; |
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writeb(tmp_char, &gpiop->par_timer); |
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/* all QSPI pins -> GPIO */ |
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writew(0x0000, &gpiop->par_qspi); |
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/* U0RTS, U0CTS -> GPIO */ |
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tmp_short = __raw_readw(&gpiop->par_uart); |
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tmp_short &= 0xfff3; |
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__raw_writew(tmp_short, &gpiop->par_uart); |
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/* all PWM pins -> GPIO */ |
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writeb(0x00, &gpiop->par_pwm); |
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/* next, set data direction registers */ |
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writeb(0x01, &gpiop->pddr_timer); |
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writeb(0x25, &gpiop->pddr_qspi); |
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writeb(0x0c, &gpiop->pddr_uart); |
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writeb(0x04, &gpiop->pddr_pwm); |
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/* ensure other SPI peripherals are deselected */ |
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writeb(0x08, &gpiop->ppd_uart); |
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writeb(0x38, &gpiop->ppd_qspi); |
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writeb(0x01, &gpiop->ppd_timer); |
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/* CONFIG = 0, STATUS = 0 -> FPGA in reset state */ |
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writeb(0xFB, &gpiop->pclrr_uart); |
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/* enable Xilinx configuration by clearing QSPI_CS2 and U0CTS */ |
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writeb(0xF7, &gpiop->pclrr_uart); |
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writeb(0xDF, &gpiop->pclrr_qspi); |
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return 0; |
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} |
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|
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/*
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* FPGA post configuration function. Should perform a test if FPGA is running. |
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*/ |
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int xilinx_post_config_fn(int cookie) |
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{ |
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int rc = 0; |
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/*
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* no test yet |
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*/ |
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return rc; |
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} |
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|
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int xilinx_clk_fn(int assert_clk, int flush, int cookie) |
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{ |
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO; |
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|
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if (assert_clk) |
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writeb(0x04, &gpiop->ppd_qspi); |
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else |
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writeb(0xFB, &gpiop->pclrr_qspi); |
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return assert_clk; |
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} |
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|
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int xilinx_wr_fn(int assert_write, int flush, int cookie) |
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{ |
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO; |
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|
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if (assert_write) |
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writeb(0x01, &gpiop->ppd_qspi); |
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else |
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writeb(0xFE, &gpiop->pclrr_qspi); |
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return assert_write; |
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} |
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|
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int xilinx_fastwr_fn(void *buf, size_t len, int flush, int cookie) |
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{ |
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size_t bytecount = 0; |
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gpio_t *gpiop = (gpio_t *)MMAP_GPIO; |
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unsigned char *data = (unsigned char *)buf; |
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unsigned char val = 0; |
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int i; |
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int len_40 = len / 40; |
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|
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for (bytecount = 0; bytecount < len; bytecount++) { |
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val = *(data++); |
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for (i = 8; i > 0; i--) { |
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writeb(0xFB, &gpiop->pclrr_qspi); |
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if (val & 0x80) |
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writeb(0x01, &gpiop->ppd_qspi); |
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else |
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writeb(0xFE, &gpiop->pclrr_qspi); |
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writeb(0x04, &gpiop->ppd_qspi); |
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val <<= 1; |
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} |
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if (bytecount % len_40 == 0) { |
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#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) |
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WATCHDOG_RESET(); |
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#endif |
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK |
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putc('.'); /* let them know we are alive */ |
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#endif |
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#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC |
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if (ctrlc()) |
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return FPGA_FAIL; |
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#endif |
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} |
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} |
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return FPGA_SUCCESS; |
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} |
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|
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/*
|
||||
* Note that these are pointers to code that is in Flash. They will be |
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* relocated at runtime. |
||||
* FIXME: relocation not yet working for coldfire, see below! |
||||
*/ |
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Xilinx_Spartan3_Slave_Serial_fns xilinx_fns = { |
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xilinx_pre_config_fn, |
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xilinx_pgm_fn, |
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xilinx_clk_fn, |
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xilinx_init_fn, |
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xilinx_done_fn, |
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xilinx_wr_fn, |
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0, |
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xilinx_fastwr_fn |
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}; |
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|
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Xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = { |
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{Xilinx_Spartan3, |
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slave_serial, |
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XILINX_XC3S4000_SIZE, |
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(void *)&xilinx_fns, |
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0} |
||||
}; |
||||
|
||||
/* Initialize the fpga. Return 1 on success, 0 on failure. */ |
||||
int astro5373l_xilinx_load(void) |
||||
{ |
||||
int i; |
||||
|
||||
fpga_init(); |
||||
|
||||
for (i = 0; i < CONFIG_FPGA_COUNT; i++) { |
||||
/*
|
||||
* I did not yet manage to get relocation work properly, |
||||
* so set stuff here instead of static initialisation: |
||||
*/ |
||||
xilinx_fns.pre = xilinx_pre_config_fn; |
||||
xilinx_fns.pgm = xilinx_pgm_fn; |
||||
xilinx_fns.clk = xilinx_clk_fn; |
||||
xilinx_fns.init = xilinx_init_fn; |
||||
xilinx_fns.done = xilinx_done_fn; |
||||
xilinx_fns.wr = xilinx_wr_fn; |
||||
xilinx_fns.bwr = xilinx_fastwr_fn; |
||||
xilinx_fpga[i].iface_fns = (void *)&xilinx_fns; |
||||
fpga_add(fpga_xilinx, &xilinx_fpga[i]); |
||||
} |
||||
return 1; |
||||
} |
||||
@ -0,0 +1,211 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2003 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* modified by Wolfgang Wegner <w.wegner@astro-kom.de> for ASTRO 5373l |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <watchdog.h> |
||||
#include <command.h> |
||||
#include <asm/m5329.h> |
||||
#include <asm/immap_5329.h> |
||||
#include <asm/io.h> |
||||
|
||||
/* needed for astro bus: */ |
||||
#include <asm/uart.h> |
||||
#include "astro.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
extern void uart_port_conf(void); |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
puts("Board: "); |
||||
puts("ASTRO MCF5373L (Urmel) Board\n"); |
||||
return 0; |
||||
} |
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
#if !defined(CONFIG_MONITOR_IS_IN_RAM) |
||||
sdram_t *sdp = (sdram_t *)(MMAP_SDRAM); |
||||
|
||||
/*
|
||||
* GPIO configuration for bus should be set correctly from reset, |
||||
* so we do not care! First, set up address space: at this point, |
||||
* we should be running from internal SRAM; |
||||
* so use CONFIG_SYS_SDRAM_BASE as the base address for SDRAM, |
||||
* and do not care where it is |
||||
*/ |
||||
__raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018, |
||||
&sdp->cs0); |
||||
__raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000, |
||||
&sdp->cs1); |
||||
/*
|
||||
* I am not sure from the data sheet, but it seems burst length |
||||
* has to be 8 for the 16 bit data bus we use; |
||||
* so these values are for BL = 8 |
||||
*/ |
||||
__raw_writel(0x33211530, &sdp->cfg1); |
||||
__raw_writel(0x56570000, &sdp->cfg2); |
||||
/* send PrechargeALL, REF and IREF remain cleared! */ |
||||
__raw_writel(0xE1462C02, &sdp->ctrl); |
||||
udelay(1); |
||||
/* refresh SDRAM twice */ |
||||
__raw_writel(0xE1462C04, &sdp->ctrl); |
||||
udelay(1); |
||||
__raw_writel(0xE1462C04, &sdp->ctrl); |
||||
/* init MR */ |
||||
__raw_writel(0x008D0000, &sdp->mode); |
||||
/* initialize EMR */ |
||||
__raw_writel(0x80010000, &sdp->mode); |
||||
/* wait until DLL is locked */ |
||||
udelay(1); |
||||
/*
|
||||
* enable automatic refresh, lock mode register, |
||||
* clear iref and ipall |
||||
*/ |
||||
__raw_writel(0x71462C00, &sdp->ctrl); |
||||
/* Dummy write to start SDRAM */ |
||||
writel(0, CONFIG_SYS_SDRAM_BASE); |
||||
#endif |
||||
|
||||
/*
|
||||
* for get_ram_size() to work, both CS areas have to be |
||||
* configured, i.e. CS1 has to be explicitely disabled, else |
||||
* probing for memory will cause the SDRAM bus to hang! |
||||
* (Do not rely on the SDCS register(s) being set to 0x00000000 |
||||
* during reset as stated in the data sheet.) |
||||
*/ |
||||
return get_ram_size((unsigned long *)CONFIG_SYS_SDRAM_BASE, |
||||
0x80000000 - CONFIG_SYS_SDRAM_BASE); |
||||
} |
||||
|
||||
#define UART_BASE MMAP_UART0 |
||||
int rs_serial_init(int port, int baud) |
||||
{ |
||||
uart_t *uart; |
||||
u32 counter; |
||||
|
||||
switch (port) { |
||||
case 0: |
||||
uart = (uart_t *)(MMAP_UART0); |
||||
break; |
||||
case 1: |
||||
uart = (uart_t *)(MMAP_UART1); |
||||
break; |
||||
case 2: |
||||
uart = (uart_t *)(MMAP_UART2); |
||||
break; |
||||
default: |
||||
uart = (uart_t *)(MMAP_UART0); |
||||
} |
||||
|
||||
uart_port_conf(); |
||||
|
||||
/* write to SICR: SIM2 = uart mode,dcd does not affect rx */ |
||||
writeb(UART_UCR_RESET_RX, &uart->ucr); |
||||
writeb(UART_UCR_RESET_TX, &uart->ucr); |
||||
writeb(UART_UCR_RESET_ERROR, &uart->ucr); |
||||
writeb(UART_UCR_RESET_MR, &uart->ucr); |
||||
__asm__ ("nop"); |
||||
|
||||
writeb(0, &uart->uimr); |
||||
|
||||
/* write to CSR: RX/TX baud rate from timers */ |
||||
writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr); |
||||
|
||||
writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr); |
||||
writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr); |
||||
|
||||
/* Setting up BaudRate */ |
||||
counter = (u32) (gd->bus_clk / (baud)); |
||||
counter >>= 5; |
||||
|
||||
/* write to CTUR: divide counter upper byte */ |
||||
writeb((u8) ((counter & 0xff00) >> 8), &uart->ubg1); |
||||
/* write to CTLR: divide counter lower byte */ |
||||
writeb((u8) (counter & 0x00ff), &uart->ubg2); |
||||
|
||||
writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void astro_put_char(char ch) |
||||
{ |
||||
uart_t *uart; |
||||
unsigned long timer; |
||||
|
||||
uart = (uart_t *)(MMAP_UART0); |
||||
/*
|
||||
* Wait for last character to go. Timeout of 6ms should |
||||
* be enough for our lowest baud rate of 2400. |
||||
*/ |
||||
timer = get_timer(0); |
||||
while (get_timer(timer) < 6) { |
||||
if (readb(&uart->usr) & UART_USR_TXRDY) |
||||
break; |
||||
} |
||||
writeb(ch, &uart->utb); |
||||
|
||||
return; |
||||
} |
||||
|
||||
int astro_is_char(void) |
||||
{ |
||||
uart_t *uart; |
||||
|
||||
uart = (uart_t *)(MMAP_UART0); |
||||
return readb(&uart->usr) & UART_USR_RXRDY; |
||||
} |
||||
|
||||
int astro_get_char(void) |
||||
{ |
||||
uart_t *uart; |
||||
|
||||
uart = (uart_t *)(MMAP_UART0); |
||||
while (!(readb(&uart->usr) & UART_USR_RXRDY)) ; |
||||
return readb(&uart->urb); |
||||
} |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
int retval = 0; |
||||
|
||||
puts("Configure Xilinx FPGA..."); |
||||
retval = astro5373l_xilinx_load(); |
||||
if (!retval) { |
||||
puts("failed!\n"); |
||||
return retval; |
||||
} |
||||
puts("done\n"); |
||||
|
||||
puts("Configure Altera FPGA..."); |
||||
retval = astro5373l_altera_load(); |
||||
if (!retval) { |
||||
puts("failed!\n"); |
||||
return retval; |
||||
} |
||||
puts("done\n"); |
||||
|
||||
return retval; |
||||
} |
||||
@ -0,0 +1,142 @@ |
||||
/* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(m68k) |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/mcf532x/start.o (.text) |
||||
lib_m68k/traps.o (.text) |
||||
lib_m68k/interrupts.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
|
||||
. = DEFINED(env_offset) ? env_offset : .; |
||||
common/env_embedded.o (.text) |
||||
|
||||
*(.text) |
||||
/* *(.fixup)*/ |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
|
||||
.reloc : |
||||
{ |
||||
__got_start = .; |
||||
*(.got) |
||||
__got_end = .; |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
_sbss = .; |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
. = ALIGN(4); |
||||
_ebss = .; |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
@ -0,0 +1,210 @@ |
||||
/*
|
||||
* ColdFire cache |
||||
* |
||||
* Copyright (C) 2004-2010 Freescale Semiconductor, Inc. |
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CACHE_H |
||||
#define __CACHE_H |
||||
|
||||
#if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \ |
||||
defined(CONFIG_MCF52x2) || defined(CONFIG_MCF5227x) |
||||
#define CONFIG_CF_V2 |
||||
#endif |
||||
|
||||
#if defined(CONFIG_MCF532x) || defined(CONFIG_MCF5301x) |
||||
#define CONFIG_CF_V3 |
||||
#endif |
||||
|
||||
#if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x) |
||||
#define CONFIG_CF_V4 |
||||
#if defined(CONFIG_MCF5441x) |
||||
#define CONFIG_CF_V4E /* Four Extra ACRn */ |
||||
#endif |
||||
#endif |
||||
|
||||
/* ***** CACR ***** */ |
||||
/* V2 Core */ |
||||
#ifdef CONFIG_CF_V2 |
||||
|
||||
#define CF_CACR_CENB (1 << 31) |
||||
#define CF_CACR_CPD (1 << 28) |
||||
#define CF_CACR_CFRZ (1 << 27) |
||||
#define CF_CACR_CEIB (1 << 10) |
||||
#define CF_CACR_DCM (1 << 9) |
||||
#define CF_CACR_DBWE (1 << 8) |
||||
|
||||
#if defined(CONFIG_MCF5249) || defined(CONFIG_MCF5253) |
||||
#define CF_CACR_DWP (1 << 6) |
||||
#else |
||||
#define CF_CACR_CINV (1 << 24) |
||||
#define CF_CACR_DISI (1 << 23) |
||||
#define CF_CACR_DISD (1 << 22) |
||||
#define CF_CACR_INVI (1 << 21) |
||||
#define CF_CACR_INVD (1 << 20) |
||||
#define CF_CACR_DWP (1 << 5) |
||||
#define CF_CACR_EUSP (1 << 4) |
||||
#endif /* CONFIG_MCF5249 || CONFIG_MCF5253 */ |
||||
|
||||
#endif /* CONFIG_CF_V2 */ |
||||
|
||||
/* V3 Core */ |
||||
#ifdef CONFIG_CF_V3 |
||||
|
||||
#define CF_CACR_EC (1 << 31) |
||||
#define CF_CACR_ESB (1 << 29) |
||||
#define CF_CACR_DPI (1 << 28) |
||||
#define CF_CACR_HLCK (1 << 27) |
||||
#define CF_CACR_CINVA (1 << 24) |
||||
#define CF_CACR_DNFB (1 << 10) |
||||
#define CF_CACR_DCM_UNMASK 0xFFFFFCFF |
||||
#define CF_CACR_DCM_WT (0 << 8) |
||||
#define CF_CACR_DCM_CB (1 << 8) |
||||
#define CF_CACR_DCM_P (2 << 8) |
||||
#define CF_CACR_DCM_IP (3 << 8) |
||||
#define CF_CACR_DW (1 << 5) |
||||
#define CF_CACR_EUSP (1 << 4) |
||||
|
||||
#endif /* CONFIG_CF_V3 */ |
||||
|
||||
/* V4 Core */ |
||||
#ifdef CONFIG_CF_V4 |
||||
|
||||
#define CF_CACR_DEC (1 << 31) |
||||
#define CF_CACR_DW (1 << 30) |
||||
#define CF_CACR_DESB (1 << 29) |
||||
#define CF_CACR_DDPI (1 << 28) |
||||
#define CF_CACR_DHLCK (1 << 27) |
||||
#define CF_CACR_DDCM_UNMASK (0xF9FFFFFF) |
||||
#define CF_CACR_DDCM_WT (0 << 25) |
||||
#define CF_CACR_DDCM_CB (1 << 25) |
||||
#define CF_CACR_DDCM_P (2 << 25) |
||||
#define CF_CACR_DDCM_IP (3 << 25) |
||||
#define CF_CACR_DCINVA (1 << 24) |
||||
|
||||
#define CF_CACR_DDSP (1 << 23) |
||||
#define CF_CACR_BEC (1 << 19) |
||||
#define CF_CACR_BCINVA (1 << 18) |
||||
#define CF_CACR_IEC (1 << 15) |
||||
#define CF_CACR_DNFB (1 << 13) |
||||
#define CF_CACR_IDPI (1 << 12) |
||||
#define CF_CACR_IHLCK (1 << 11) |
||||
#define CF_CACR_IDCM (1 << 10) |
||||
#define CF_CACR_ICINVA (1 << 8) |
||||
#define CF_CACR_IDSP (1 << 7) |
||||
#define CF_CACR_EUSP (1 << 5) |
||||
|
||||
#ifdef CONFIG_MCF5445x |
||||
#define CF_CACR_IVO (1 << 20) |
||||
#define CF_CACR_SPA (1 << 14) |
||||
#else |
||||
#define CF_CACR_DF (1 << 4) |
||||
#endif |
||||
|
||||
#endif /* CONFIG_CF_V4 */ |
||||
|
||||
/* ***** ACR ***** */ |
||||
#define CF_ACR_ADR_UNMASK (0x00FFFFFF) |
||||
#define CF_ACR_ADR(x) ((x & 0xFF) << 24) |
||||
#define CF_ACR_ADRMSK_UNMASK (0xFF00FFFF) |
||||
#define CF_ACR_ADRMSK(x) ((x & 0xFF) << 16) |
||||
#define CF_ACR_EN (1 << 15) |
||||
#define CF_ACR_SM_UNMASK (0xFFFF9FFF) |
||||
#define CF_ACR_SM_UM (0 << 13) |
||||
#define CF_ACR_SM_SM (1 << 13) |
||||
#define CF_ACR_SM_ALL (3 << 13) |
||||
#define CF_ACR_WP (1 << 2) |
||||
|
||||
/* V2 Core */ |
||||
#ifdef CONFIG_CF_V2 |
||||
#define CF_ACR_CM (1 << 6) |
||||
#define CF_ACR_BWE (1 << 5) |
||||
#else |
||||
/* V3 & V4 */ |
||||
#define CF_ACR_CM_UNMASK (0xFFFFFF9F) |
||||
#define CF_ACR_CM_WT (0 << 5) |
||||
#define CF_ACR_CM_CB (1 << 5) |
||||
#define CF_ACR_CM_P (2 << 5) |
||||
#define CF_ACR_CM_IP (3 << 5) |
||||
#endif /* CONFIG_CF_V2 */ |
||||
|
||||
/* V4 Core */ |
||||
#ifdef CONFIG_CF_V4 |
||||
#define CF_ACR_AMM (1 << 10) |
||||
#define CF_ACR_SP (1 << 3) |
||||
#endif /* CONFIG_CF_V4 */ |
||||
|
||||
|
||||
#ifndef CONFIG_SYS_CACHE_ICACR |
||||
#define CONFIG_SYS_CACHE_ICACR 0 |
||||
#endif |
||||
|
||||
#ifndef CONFIG_SYS_CACHE_DCACR |
||||
#ifdef CONFIG_SYS_CACHE_ICACR |
||||
#define CONFIG_SYS_CACHE_DCACR CONFIG_SYS_CACHE_ICACR |
||||
#else |
||||
#define CONFIG_SYS_CACHE_DCACR 0 |
||||
#endif |
||||
#endif |
||||
|
||||
#ifndef CONFIG_SYS_CACHE_ACR0 |
||||
#define CONFIG_SYS_CACHE_ACR0 0 |
||||
#endif |
||||
|
||||
#ifndef CONFIG_SYS_CACHE_ACR1 |
||||
#define CONFIG_SYS_CACHE_ACR1 0 |
||||
#endif |
||||
|
||||
#ifndef CONFIG_SYS_CACHE_ACR2 |
||||
#define CONFIG_SYS_CACHE_ACR2 0 |
||||
#endif |
||||
|
||||
#ifndef CONFIG_SYS_CACHE_ACR3 |
||||
#define CONFIG_SYS_CACHE_ACR3 0 |
||||
#endif |
||||
|
||||
#ifndef CONFIG_SYS_CACHE_ACR4 |
||||
#define CONFIG_SYS_CACHE_ACR4 0 |
||||
#endif |
||||
|
||||
#ifndef CONFIG_SYS_CACHE_ACR5 |
||||
#define CONFIG_SYS_CACHE_ACR5 0 |
||||
#endif |
||||
|
||||
#ifndef CONFIG_SYS_CACHE_ACR6 |
||||
#define CONFIG_SYS_CACHE_ACR6 0 |
||||
#endif |
||||
|
||||
#ifndef CONFIG_SYS_CACHE_ACR7 |
||||
#define CONFIG_SYS_CACHE_ACR7 0 |
||||
#endif |
||||
|
||||
#define CF_ADDRMASK(x) (((x > 0x10) ? ((x >> 4) - 1) : (x)) << 16) |
||||
|
||||
#ifndef __ASSEMBLY__ /* put C only stuff in this section */ |
||||
|
||||
void icache_invalid(void); |
||||
void dcache_invalid(void); |
||||
|
||||
#endif |
||||
|
||||
#endif /* __CACHE_H */ |
||||
@ -0,0 +1,400 @@ |
||||
/*
|
||||
* Configuration settings for the Sentec Cobra Board. |
||||
* |
||||
* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* configuration for ASTRO "Urmel" board. |
||||
* Originating from Cobra5272 configuration, messed up by |
||||
* Wolfgang Wegner <w.wegner@astro-kom.de> |
||||
* Please do not bother the original author with bug reports |
||||
* concerning this file. |
||||
*/ |
||||
|
||||
#ifndef _CONFIG_ASTRO_MCF5373L_H |
||||
#define _CONFIG_ASTRO_MCF5373L_H |
||||
|
||||
/*
|
||||
* set the card type to actually compile for; either of |
||||
* the possibilities listed below has to be used! |
||||
*/ |
||||
#define CONFIG_ASTRO_V532 1 |
||||
|
||||
#if CONFIG_ASTRO_V532 |
||||
#define ASTRO_ID 0xF8 |
||||
#elif CONFIG_ASTRO_V512 |
||||
#define ASTRO_ID 0xFA |
||||
#elif CONFIG_ASTRO_TWIN7S2 |
||||
#define ASTRO_ID 0xF9 |
||||
#elif CONFIG_ASTRO_V912 |
||||
#define ASTRO_ID 0xFC |
||||
#elif CONFIG_ASTRO_COFDMDUOS2 |
||||
#define ASTRO_ID 0xFB |
||||
#else |
||||
#error No card type defined! |
||||
#endif |
||||
|
||||
/*
|
||||
* Define processor |
||||
* possible values for Urmel board: only Coldfire M5373 processor supported |
||||
* (please do not change) |
||||
*/ |
||||
|
||||
/* it seems not clear yet which processor defines we should use */ |
||||
#define CONFIG_MCF537x /* define processor family */ |
||||
#define CONFIG_MCF532x /* define processor family */ |
||||
#define CONFIG_M5373 /* define processor type */ |
||||
#define CONFIG_ASTRO5373L /* define board type */ |
||||
|
||||
/* Command line configuration */ |
||||
#include <config_cmd_default.h> |
||||
|
||||
/*
|
||||
* CONFIG_MK_RAM defines if u-boot is loaded via BDM (or started from |
||||
* a different bootloader that has already performed RAM setup) or |
||||
* started directly from flash, which is the regular case for production |
||||
* boards. |
||||
*/ |
||||
#ifdef CONFIG_MK_RAM |
||||
#define CONFIG_MONITOR_IS_IN_RAM |
||||
#define CONFIG_TEXT_BASE 0x40020000 |
||||
#define ENABLE_JFFS 0 |
||||
#else |
||||
#define CONFIG_TEXT_BASE 0x00000000 |
||||
#define ENABLE_JFFS 1 |
||||
#endif |
||||
|
||||
/* Define which commmands should be available at u-boot command prompt */ |
||||
|
||||
#define CONFIG_CMD_CACHE |
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_ELF |
||||
#define CONFIG_CMD_FLASH |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_MEMORY |
||||
#define CONFIG_CMD_MISC |
||||
#define CONFIG_CMD_XIMG |
||||
#undef CONFIG_CMD_NET |
||||
#undef CONFIG_CMD_NFS |
||||
#if ENABLE_JFFS |
||||
#define CONFIG_CMD_JFFS2 |
||||
#endif |
||||
#define CONFIG_CMD_REGINFO |
||||
#define CONFIG_CMD_LOADS |
||||
#define CONFIG_CMD_LOADB |
||||
#define CONFIG_CMD_FPGA |
||||
#define CONFIG_CMDLINE_EDITING |
||||
|
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
|
||||
#define CONFIG_MCFRTC |
||||
#undef RTC_DEBUG |
||||
|
||||
/* Timer */ |
||||
#define CONFIG_MCFTMR |
||||
#undef CONFIG_MCFPIT |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_FSL_I2C |
||||
#define CONFIG_HARD_I2C /* I2C with hw support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CONFIG_SYS_I2C_SPEED 80000 |
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F |
||||
#define CONFIG_SYS_I2C_OFFSET 0x58000 |
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
||||
|
||||
/*
|
||||
* Defines processor clock - important for correct timings concerning serial |
||||
* interface etc. |
||||
* CONFIG_SYS_HZ gives unit: 1000 -> 1 Hz ^= 1000 ms |
||||
*/ |
||||
|
||||
#define CONFIG_SYS_HZ 1000 |
||||
#define CONFIG_SYS_CLK 80000000 |
||||
#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3) |
||||
#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ |
||||
|
||||
#define CONFIG_SYS_CORE_SRAM_SIZE 0x8000 |
||||
#define CONFIG_SYS_CORE_SRAM 0x80000000 |
||||
|
||||
#define CONFIG_SYS_UNIFY_CACHE |
||||
|
||||
/*
|
||||
* Define baudrate for UART1 (console output, tftp, ...) |
||||
* default value of CONFIG_BAUDRATE for Sentec board: 19200 baud |
||||
* CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected |
||||
* in u-boot command interface |
||||
*/ |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } |
||||
|
||||
#define CONFIG_MCFUART |
||||
#define CONFIG_SYS_UART_PORT (2) |
||||
#define CONFIG_SYS_UART2_ALT3_GPIO |
||||
|
||||
/*
|
||||
* Watchdog configuration; Watchdog is disabled for running from RAM |
||||
* and set to highest possible value else. Beware there is no check |
||||
* in the watchdog code to validate the timeout value set here! |
||||
*/ |
||||
|
||||
#ifndef CONFIG_MONITOR_IS_IN_RAM |
||||
#define CONFIG_WATCHDOG |
||||
#define CONFIG_WATCHDOG_TIMEOUT 3355 /* timeout in milliseconds */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Configuration for environment |
||||
* Environment is located in the last sector of the flash |
||||
*/ |
||||
|
||||
#ifndef CONFIG_MONITOR_IS_IN_RAM |
||||
#define CONFIG_ENV_OFFSET 0x1FF8000 |
||||
#define CONFIG_ENV_SECT_SIZE 0x8000 |
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#else |
||||
/*
|
||||
* environment in RAM - This is used to use a single PC-based application |
||||
* to load an image, load U-Boot, load an environment and then start U-Boot |
||||
* to execute the commands from the environment. Feedback is done via setting |
||||
* and reading memory locations. |
||||
*/ |
||||
#define CONFIG_ENV_ADDR 0x40060000 |
||||
#define CONFIG_ENV_SECT_SIZE 0x8000 |
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#endif |
||||
|
||||
/* here we put our FPGA configuration... */ |
||||
#define CONFIG_MISC_INIT_R 1 |
||||
|
||||
/* Define user parameters that have to be customized most likely */ |
||||
|
||||
/* AUTOBOOT settings - booting images automatically by u-boot after power on */ |
||||
|
||||
/*
|
||||
* used for autoboot, delay in seconds u-boot will wait before starting |
||||
* defined (auto-)boot command, setting to -1 disables delay, setting to |
||||
* 0 will too prevent access to u-boot command interface: u-boot then has |
||||
* to be reflashed |
||||
* beware - watchdog is not serviced during autoboot delay time! |
||||
*/ |
||||
#ifdef CONFIG_MONITOR_IS_IN_RAM |
||||
#define CONFIG_BOOTDELAY 1 |
||||
#else |
||||
#define CONFIG_BOOTDELAY 1 |
||||
#endif |
||||
|
||||
/*
|
||||
* The following settings will be contained in the environment block ; if you |
||||
* want to use a neutral environment all those settings can be manually set in |
||||
* u-boot: 'set' command |
||||
*/ |
||||
|
||||
#define _QUOTEME(x) #x |
||||
#define QUOTEME(x) _QUOTEME(x) |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"loaderversion=11\0" \
|
||||
"card_id="QUOTEME(ASTRO_ID)"\0" \
|
||||
"alterafile=0\0" \
|
||||
"xilinxfile=0\0" \
|
||||
"xilinxload=imxtract 0x540000 $xilinxfile 0x41000000&&"\
|
||||
"fpga load 0 0x41000000 $filesize\0" \
|
||||
"alteraload=imxtract 0x6c0000 $alterafile 0x41000000&&"\
|
||||
"fpga load 1 0x41000000 $filesize\0" \
|
||||
"env_default=1\0" \
|
||||
"env_check=if test $env_default -eq 1;"\
|
||||
" then setenv env_default 0;saveenv;fi\0" |
||||
|
||||
/*
|
||||
* "update" is a non-standard command that has to be supplied |
||||
* by external update.c; This is not included in mainline because |
||||
* it needs non-blocking CFI routines. |
||||
*/ |
||||
#ifdef CONFIG_MONITOR_IS_IN_RAM |
||||
#define CONFIG_BOOTCOMMAND "" /* no autoboot in this case */ |
||||
#else |
||||
#if CONFIG_ASTRO_V532 |
||||
#define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\ |
||||
"run xilinxload&&run alteraload&&bootm 0x80000;"\
|
||||
"update;reset" |
||||
#else |
||||
#define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\ |
||||
"run xilinxload&&bootm 0x80000;update;reset" |
||||
#endif |
||||
#endif |
||||
|
||||
/* default bootargs that are considered during boot */ |
||||
#define CONFIG_BOOTARGS " console=ttyS2,115200 rootfstype=romfs"\ |
||||
" loaderversion=$loaderversion" |
||||
|
||||
#define CONFIG_SYS_PROMPT "URMEL > " |
||||
|
||||
/* default RAM address for user programs */ |
||||
#define CONFIG_SYS_LOAD_ADDR 0x20000 |
||||
|
||||
#define CONFIG_SYS_LONGHELP |
||||
|
||||
#if (CONFIG_COMMANDS & CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CBSIZE 1024 |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
||||
#define CONFIG_SYS_MAXARGS 16 |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
|
||||
#define CONFIG_FPGA_COUNT 1 |
||||
#define CONFIG_FPGA |
||||
#define CONFIG_FPGA_XILINX |
||||
#define CONFIG_FPGA_SPARTAN3 |
||||
#define CONFIG_FPGA_ALTERA |
||||
#define CONFIG_FPGA_CYCLON2 |
||||
#define CONFIG_SYS_FPGA_PROG_FEEDBACK |
||||
#define CONFIG_SYS_FPGA_WAIT 1000 |
||||
|
||||
/* End of user parameters to be customized */ |
||||
|
||||
/* Defines memory range for test */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x40020000 |
||||
#define CONFIG_SYS_MEMTEST_END 0x41ffffff |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
|
||||
/* Base register address */ |
||||
|
||||
#define CONFIG_SYS_MBAR 0xFC000000 /* Register Base Addrs */ |
||||
|
||||
/* System Conf. Reg. & System Protection Reg. */ |
||||
|
||||
#define CONFIG_SYS_SCR 0x0003; |
||||
#define CONFIG_SYS_SPR 0xffff; |
||||
|
||||
/*
|
||||
* Definitions for initial stack pointer and data area (in internal SRAM) |
||||
*/ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 |
||||
#define CONFIG_SYS_INIT_RAM_END 0x8000 |
||||
#define CONFIG_SYS_INIT_RAM_CTRL 0x221 |
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ |
||||
CONFIG_SYS_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
/*
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* for MCF5373, the allowable range is 0x40000000 to 0x7FF00000 |
||||
*/ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x40000000 |
||||
|
||||
/*
|
||||
* Chipselect bank definitions |
||||
* |
||||
* CS0 - Flash 32MB (first 16MB) |
||||
* CS1 - Flash 32MB (second half) |
||||
* CS2 - FPGA |
||||
* CS3 - FPGA |
||||
* CS4 - unused |
||||
* CS5 - unused |
||||
*/ |
||||
#define CONFIG_SYS_CS0_BASE 0 |
||||
#define CONFIG_SYS_CS0_MASK 0x00ff0001 |
||||
#define CONFIG_SYS_CS0_CTRL 0x00001fc0 |
||||
|
||||
#define CONFIG_SYS_CS1_BASE 0x01000000 |
||||
#define CONFIG_SYS_CS1_MASK 0x00ff0001 |
||||
#define CONFIG_SYS_CS1_CTRL 0x00001fc0 |
||||
|
||||
#define CONFIG_SYS_CS2_BASE 0x20000000 |
||||
#define CONFIG_SYS_CS2_MASK 0x00ff0001 |
||||
#define CONFIG_SYS_CS2_CTRL 0x0000fec0 |
||||
|
||||
#define CONFIG_SYS_CS3_BASE 0x21000000 |
||||
#define CONFIG_SYS_CS3_MASK 0x00ff0001 |
||||
#define CONFIG_SYS_CS3_CTRL 0x0000fec0 |
||||
|
||||
#define CONFIG_SYS_FLASH_BASE 0x00000000 |
||||
|
||||
#ifdef CONFIG_MONITOR_IS_IN_RAM |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_TEXT_BASE |
||||
#else |
||||
/* This is mainly used during relocation in start.S */ |
||||
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
||||
#endif |
||||
/* Reserve 256 kB for Monitor */ |
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) |
||||
|
||||
#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) |
||||
/* Reserve 128 kB for malloc() */ |
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization ?? |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ |
||||
(CONFIG_SYS_SDRAM_SIZE << 20)) |
||||
|
||||
/* FLASH organization */ |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 259 |
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 |
||||
|
||||
#define CONFIG_SYS_FLASH_CFI 1 |
||||
#define CONFIG_FLASH_CFI_DRIVER 1 |
||||
#define CONFIG_SYS_FLASH_SIZE 0x2000000 |
||||
#define CONFIG_SYS_FLASH_PROTECTION 1 |
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
||||
#define CONFIG_SYS_FLASH_CFI_NONBLOCK 1 |
||||
|
||||
#if ENABLE_JFFS |
||||
/* JFFS Partition offset set */ |
||||
#define CONFIG_SYS_JFFS2_FIRST_BANK 0 |
||||
#define CONFIG_SYS_JFFS2_NUM_BANKS 1 |
||||
/* 512k reserved for u-boot */ |
||||
#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0x40 |
||||
#endif |
||||
|
||||
/* Cache Configuration */ |
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 |
||||
|
||||
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
||||
CONFIG_SYS_INIT_RAM_END - 8) |
||||
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
||||
CONFIG_SYS_INIT_RAM_END - 4) |
||||
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) |
||||
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ |
||||
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
|
||||
CF_ACR_EN | CF_ACR_SM_ALL) |
||||
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ |
||||
CF_CACR_DCM_P) |
||||
|
||||
#endif /* _CONFIG_ASTRO_MCF5373L_H */ |
||||
Loading…
Reference in new issue