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armv7: Add ST-Ericsson u8500 arch

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Based on ST-Ericsson internal git repo.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: John Rigby <john.rigby@linaro.org>
CC: Albert Aribaud <albert.aribaud@free.fr>
master
John Rigby 13 years ago committed by Albert ARIBAUD
parent 92ff2d82b0
commit be72e0c8c5
9 changed files with 767 additions and 0 deletions
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  1. 46
      arch/arm/cpu/armv7/u8500/Makefile
  2. 56
      arch/arm/cpu/armv7/u8500/clock.c
  3. 35
      arch/arm/cpu/armv7/u8500/lowlevel.S
  4. 154
      arch/arm/cpu/armv7/u8500/timer.c
  5. 72
      arch/arm/include/asm/arch-u8500/clock.h
  6. 247
      arch/arm/include/asm/arch-u8500/gpio.h
  7. 83
      arch/arm/include/asm/arch-u8500/hardware.h
  8. 27
      arch/arm/include/asm/arch-u8500/sys_proto.h
  9. 47
      arch/arm/include/asm/arch-u8500/u8500.h

46
arch/arm/cpu/armv7/u8500/Makefile
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#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS = timer.o clock.o
SOBJS = lowlevel.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

56
arch/arm/cpu/armv7/u8500/clock.c
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/*
* (C) Copyright 2009 ST-Ericsson
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
struct clkrst {
unsigned int pcken;
unsigned int pckdis;
unsigned int kcken;
unsigned int kckdis;
};
static unsigned int clkrst_base[] = {
U8500_CLKRST1_BASE,
U8500_CLKRST2_BASE,
U8500_CLKRST3_BASE,
0,
U8500_CLKRST5_BASE,
U8500_CLKRST6_BASE,
U8500_CLKRST7_BASE, /* ED only */
};
/* Turn on peripheral clock at PRCC level */
void u8500_clock_enable(int periph, int cluster, int kern)
{
struct clkrst *clkrst = (struct clkrst *) clkrst_base[periph - 1];
if (kern != -1)
writel(1 << kern, &clkrst->kcken);
if (cluster != -1)
writel(1 << cluster, &clkrst->pcken);
}

35
arch/arm/cpu/armv7/u8500/lowlevel.S
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/*
* (C) Copyright 2011 ST-Ericsson
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <config.h>
.globl lowlevel_init
lowlevel_init:
mov pc, lr
.align 5
.globl reset_cpu
reset_cpu:
ldr r0, =CFG_PRCMU_BASE
ldr r1, =0x1
str r1, [r0, #0x228]
_loop_forever:
b _loop_forever

154
arch/arm/cpu/armv7/u8500/timer.c
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/*
* Copyright (C) 2010 Linaro Limited
* John Rigby <john.rigby@linaro.org>
*
* Based on original from Linux kernel source and
* internal ST-Ericsson U-Boot source.
* (C) Copyright 2009 Alessandro Rubini
* (C) Copyright 2010 ST-Ericsson
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* The MTU device has some interrupt control registers
* followed by 4 timers.
*/
/* The timers */
struct u8500_mtu_timer {
u32 lr; /* Load value */
u32 cv; /* Current value */
u32 cr; /* Control reg */
u32 bglr; /* ??? */
};
/* The MTU that contains the timers */
struct u8500_mtu {
u32 imsc; /* Interrupt mask set/clear */
u32 ris; /* Raw interrupt status */
u32 mis; /* Masked interrupt status */
u32 icr; /* Interrupt clear register */
struct u8500_mtu_timer pt[4];
};
/* bits for the control register */
#define MTU_CR_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR */
#define MTU_CR_32BITS 0x02
#define MTU_CR_PRESCALE_1 0x00
#define MTU_CR_PRESCALE_16 0x04
#define MTU_CR_PRESCALE_256 0x08
#define MTU_CR_PRESCALE_MASK 0x0c
#define MTU_CR_PERIODIC 0x40 /* if 0 = free-running */
#define MTU_CR_ENA 0x80
/*
* The MTU is clocked at 133 MHz by default. (V1 and later)
*/
#define TIMER_CLOCK (133 * 1000 * 1000 / 16)
#define COUNT_TO_USEC(x) ((x) * 16 / 133)
#define USEC_TO_COUNT(x) ((x) * 133 / 16)
#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
#define TIMER_LOAD_VAL 0xffffffff
/*
* MTU timer to use (from 0 to 3).
*/
#define MTU_TIMER 2
static struct u8500_mtu_timer *timer_base =
&((struct u8500_mtu *)U8500_MTU0_BASE_V1)->pt[MTU_TIMER];
/* macro to read the 32 bit timer: since it decrements, we invert read value */
#define READ_TIMER() (~readl(&timer_base->cv))
/* Configure a free-running, auto-wrap counter with /16 prescaler */
int timer_init(void)
{
writel(MTU_CR_ENA | MTU_CR_PRESCALE_16 | MTU_CR_32BITS,
&timer_base->cr);
return 0;
}
ulong get_timer_masked(void)
{
/* current tick value */
ulong now = TICKS_TO_HZ(READ_TIMER());
if (now >= gd->lastinc) /* normal (non rollover) */
gd->tbl += (now - gd->lastinc);
else /* rollover */
gd->tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL) - gd->lastinc) + now;
gd->lastinc = now;
return gd->tbl;
}
/* Delay x useconds */
void __udelay(ulong usec)
{
long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
ulong now, last = READ_TIMER();
while (tmo > 0) {
now = READ_TIMER();
if (now > last) /* normal (non rollover) */
tmo -= now - last;
else /* rollover */
tmo -= TIMER_LOAD_VAL - last + now;
last = now;
}
}
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
void set_timer(ulong t)
{
gd->tbl = t;
}
/*
* Emulation of Power architecture long long timebase.
*
* TODO: Support gd->tbu for real long long timebase.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* Emulation of Power architecture timebase.
* NB: Low resolution compared to Power tbclk.
*/
ulong get_tbclk(void)
{
return CONFIG_SYS_HZ;
}

72
arch/arm/include/asm/arch-u8500/clock.h
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/*
* Copyright (C) ST-Ericsson SA 2009
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_CLOCK
#define __ASM_ARCH_CLOCK
struct prcmu {
unsigned int armclkfix_mgt;
unsigned int armclk_mgt;
unsigned int svammdspclk_mgt;
unsigned int siammdspclk_mgt;
unsigned int reserved;
unsigned int sgaclk_mgt;
unsigned int uartclk_mgt;
unsigned int msp02clk_mgt;
unsigned int i2cclk_mgt;
unsigned int sdmmcclk_mgt;
unsigned int slimclk_mgt;
unsigned int per1clk_mgt;
unsigned int per2clk_mgt;
unsigned int per3clk_mgt;
unsigned int per5clk_mgt;
unsigned int per6clk_mgt;
unsigned int per7clk_mgt;
unsigned int lcdclk_mgt;
unsigned int reserved1;
unsigned int bmlclk_mgt;
unsigned int hsitxclk_mgt;
unsigned int hsirxclk_mgt;
unsigned int hdmiclk_mgt;
unsigned int apeatclk_mgt;
unsigned int apetraceclk_mgt;
unsigned int mcdeclk_mgt;
unsigned int ipi2cclk_mgt;
unsigned int dsialtclk_mgt;
unsigned int spare2clk_mgt;
unsigned int dmaclk_mgt;
unsigned int b2r2clk_mgt;
unsigned int tvclk_mgt;
unsigned int unused[82];
unsigned int tcr;
unsigned int unused1[23];
unsigned int ape_softrst;
};
extern void u8500_clock_enable(int periph, int kern, int cluster);
static inline void u8500_prcmu_enable(unsigned int *reg)
{
writel(readl(reg) | (1 << 8), reg);
}
#endif /* __ASM_ARCH_CLOCK */

247
arch/arm/include/asm/arch-u8500/gpio.h
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/*
* Copyright (C) ST-Ericsson SA 2009
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _UX500_GPIO_h
#define _UX500_GPIO_h
#include <asm/types.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/u8500.h>
#define GPIO_TOTAL_PINS 268
#define GPIO_PINS_PER_BLOCK 32
#define GPIO_BLOCKS_COUNT (GPIO_TOTAL_PINS/GPIO_PINS_PER_BLOCK + 1)
#define GPIO_BLOCK(pin) (((pin + GPIO_PINS_PER_BLOCK) >> 5) - 1)
struct gpio_register {
u32 gpio_dat; /* data register *//*0x000 */
u32 gpio_dats; /* data Set register *//*0x004 */
u32 gpio_datc; /* data Clear register *//*0x008 */
u32 gpio_pdis; /* Pull disable register *//*0x00C */
u32 gpio_dir; /* data direction register *//*0x010 */
u32 gpio_dirs; /* data dir Set register *//*0x014 */
u32 gpio_dirc; /* data dir Clear register *//*0x018 */
u32 gpio_slpm; /* Sleep mode register *//*0x01C */
u32 gpio_afsa; /* AltFun A Select reg *//*0x020 */
u32 gpio_afsb; /* AltFun B Select reg *//*0x024 */
u32 gpio_lowemi;/* low EMI Select reg *//*0x028 */
u32 reserved_1[(0x040 - 0x02C) >> 2]; /*0x028-0x3C Reserved*/
u32 gpio_rimsc; /* rising edge intr set/clear *//*0x040 */
u32 gpio_fimsc; /* falling edge intr set/clear register *//*0x044 */
u32 gpio_mis; /* masked interrupt status register *//*0x048 */
u32 gpio_ic; /* Interrupt Clear register *//*0x04C */
u32 gpio_rwimsc;/* Rising-edge Wakeup IMSC register *//*0x050 */
u32 gpio_fwimsc;/* Falling-edge Wakeup IMSC register *//*0x054 */
u32 gpio_wks; /* Wakeup Status register *//*0x058 */
};
/* Error values returned by functions */
enum gpio_error {
GPIO_OK = 0,
GPIO_UNSUPPORTED_HW = -2,
GPIO_UNSUPPORTED_FEATURE = -3,
GPIO_INVALID_PARAMETER = -4,
GPIO_REQUEST_NOT_APPLICABLE = -5,
GPIO_REQUEST_PENDING = -6,
GPIO_NOT_CONFIGURED = -7,
GPIO_INTERNAL_ERROR = -8,
GPIO_INTERNAL_EVENT = 1,
GPIO_REMAINING_EVENT = 2,
GPIO_NO_MORE_PENDING_EVENT = 3,
GPIO_INVALID_CLIENT = -25,
GPIO_INVALID_PIN = -26,
GPIO_PIN_BUSY = -27,
GPIO_PIN_NOT_ALLOCATED = -28,
GPIO_WRONG_CLIENT = -29,
GPIO_UNSUPPORTED_ALTFUNC = -30,
};
/*GPIO DEVICE ID */
enum gpio_device_id {
GPIO_DEVICE_ID_0,
GPIO_DEVICE_ID_1,
GPIO_DEVICE_ID_2,
GPIO_DEVICE_ID_3,
GPIO_DEVICE_ID_INVALID
};
/*
* Alternate Function:
* refered in altfun_table to pointout particular altfun to be enabled
* when using GPIO_ALT_FUNCTION A/B/C enable/disable operation
*/
enum gpio_alt_function {
GPIO_ALT_UART_0_MODEM,
GPIO_ALT_UART_0_NO_MODEM,
GPIO_ALT_UART_1,
GPIO_ALT_UART_2,
GPIO_ALT_I2C_0,
GPIO_ALT_I2C_1,
GPIO_ALT_I2C_2,
GPIO_ALT_I2C_3,
GPIO_ALT_MSP_0,
GPIO_ALT_MSP_1,
GPIO_ALT_MSP_2,
GPIO_ALT_MSP_3,
GPIO_ALT_MSP_4,
GPIO_ALT_MSP_5,
GPIO_ALT_SSP_0,
GPIO_ALT_SSP_1,
GPIO_ALT_MM_CARD0,
GPIO_ALT_SD_CARD0,
GPIO_ALT_DMA_0,
GPIO_ALT_DMA_1,
GPIO_ALT_HSI0,
GPIO_ALT_CCIR656_INPUT,
GPIO_ALT_CCIR656_OUTPUT,
GPIO_ALT_LCD_PANEL,
GPIO_ALT_MDIF,
GPIO_ALT_SDRAM,
GPIO_ALT_HAMAC_AUDIO_DBG,
GPIO_ALT_HAMAC_VIDEO_DBG,
GPIO_ALT_CLOCK_RESET,
GPIO_ALT_TSP,
GPIO_ALT_IRDA,
GPIO_ALT_USB_MINIMUM,
GPIO_ALT_USB_I2C,
GPIO_ALT_OWM,
GPIO_ALT_PWL,
GPIO_ALT_FSMC,
GPIO_ALT_COMP_FLASH,
GPIO_ALT_SRAM_NOR_FLASH,
GPIO_ALT_FSMC_ADDLINE_0_TO_15,
GPIO_ALT_SCROLL_KEY,
GPIO_ALT_MSHC,
GPIO_ALT_HPI,
GPIO_ALT_USB_OTG,
GPIO_ALT_SDIO,
GPIO_ALT_HSMMC,
GPIO_ALT_FSMC_ADD_DATA_0_TO_25,
GPIO_ALT_HSI1,
GPIO_ALT_NOR,
GPIO_ALT_NAND,
GPIO_ALT_KEYPAD,
GPIO_ALT_VPIP,
GPIO_ALT_CAM,
GPIO_ALT_CCP1,
GPIO_ALT_EMMC,
GPIO_ALT_POP_EMMC,
GPIO_ALT_FUNMAX /* Add new alt func before this */
};
/* Defines pin assignment(Software mode or Alternate mode) */
enum gpio_mode {
GPIO_MODE_LEAVE_UNCHANGED, /* Parameter will be ignored */
GPIO_MODE_SOFTWARE, /* Pin connected to GPIO (SW controlled) */
GPIO_ALTF_A, /* Pin connected to altfunc 1 (HW periph 1) */
GPIO_ALTF_B, /* Pin connected to altfunc 2 (HW periph 2) */
GPIO_ALTF_C, /* Pin connected to altfunc 3 (HW periph 3) */
GPIO_ALTF_FIND, /* Pin connected to altfunc 3 (HW periph 3) */
GPIO_ALTF_DISABLE /* Pin connected to altfunc 3 (HW periph 3) */
};
/* Defines GPIO pin direction */
enum gpio_direction {
GPIO_DIR_LEAVE_UNCHANGED, /* Parameter will be ignored */
GPIO_DIR_INPUT, /* GPIO set as input */
GPIO_DIR_OUTPUT /* GPIO set as output */
};
/* Interrupt trigger mode */
enum gpio_trig {
GPIO_TRIG_LEAVE_UNCHANGED, /* Parameter will be ignored */
GPIO_TRIG_DISABLE, /* Trigger no IT */
GPIO_TRIG_RISING_EDGE, /* Trigger an IT on rising edge */
GPIO_TRIG_FALLING_EDGE, /* Trigger an IT on falling edge */
GPIO_TRIG_BOTH_EDGES, /* Trigger an IT on rising and falling edge */
GPIO_TRIG_HIGH_LEVEL, /* Trigger an IT on high level */
GPIO_TRIG_LOW_LEVEL /* Trigger an IT on low level */
};
/* Configuration parameters for one GPIO pin.*/
struct gpio_config {
enum gpio_mode mode;
enum gpio_direction direction;
enum gpio_trig trig;
char *dev_name; /* Who owns the gpio pin */
};
/* GPIO pin data*/
enum gpio_data {
GPIO_DATA_LOW,
GPIO_DATA_HIGH
};
/* GPIO behaviour in sleep mode */
enum gpio_sleep_mode {
GPIO_SLEEP_MODE_LEAVE_UNCHANGED, /* Parameter will be ignored */
GPIO_SLEEP_MODE_INPUT_DEFAULTVOLT, /* GPIO is an input with pull
up/down enabled when in sleep
mode. */
GPIO_SLEEP_MODE_CONTROLLED_BY_GPIO /* GPIO pin is controlled by
GPIO IP. So mode, direction
and data values for GPIO pin
in sleep mode are determined
by configuration set to GPIO
pin before entering to sleep
mode. */
};
/* GPIO ability to wake the system up from sleep mode.*/
enum gpio_wake {
GPIO_WAKE_LEAVE_UNCHANGED, /* Parameter will be ignored */
GPIO_WAKE_DISABLE, /* No wake of system from sleep mode. */
GPIO_WAKE_LOW_LEVEL, /* Wake the system up on a LOW level. */
GPIO_WAKE_HIGH_LEVEL, /* Wake the system up on a HIGH level. */
GPIO_WAKE_RISING_EDGE, /* Wake the system up on a RISING edge. */
GPIO_WAKE_FALLING_EDGE, /* Wake the system up on a FALLING edge. */
GPIO_WAKE_BOTH_EDGES /* Wake the system up on both RISE and FALL. */
};
/* Configuration parameters for one GPIO pin in sleep mode.*/
struct gpio_sleep_config {
enum gpio_sleep_mode sleep_mode;/* GPIO behaviour in sleep mode. */
enum gpio_wake wake; /* GPIO ability to wake up system. */
};
extern int gpio_setpinconfig(int pin_id, struct gpio_config *pin_config);
extern int gpio_resetpinconfig(int pin_id, char *dev_name);
extern int gpio_writepin(int pin_id, enum gpio_data value, char *dev_name);
extern int gpio_readpin(int pin_id, enum gpio_data *value);
extern int gpio_altfuncenable(enum gpio_alt_function altfunc,
char *dev_name);
extern int gpio_altfuncdisable(enum gpio_alt_function altfunc,
char *dev_name);
struct gpio_altfun_data {
u16 altfun;
u16 start;
u16 end;
u16 cont;
u8 type;
};
#endif

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arch/arm/include/asm/arch-u8500/hardware.h
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/*
* Copyright (C) ST-Ericsson SA 2009
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
/* Peripheral clusters */
#define U8500_PER3_BASE 0x80000000
#define U8500_PER2_BASE 0x80110000
#define U8500_PER1_BASE 0x80120000
#define U8500_PER4_BASE 0x80150000
#define U8500_PER6_BASE 0xa03c0000
#define U8500_PER7_BASE 0xa03d0000
#define U8500_PER5_BASE 0xa03e0000
/* GPIO */
#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000)
#define U8500_GPIO1_BASE (U8500_PER1_BASE + 0xE000 + 0x80)
#define U8500_GPIO2_BASE (U8500_PER3_BASE + 0xE000)
#define U8500_GPIO3_BASE (U8500_PER3_BASE + 0xE000 + 0x80)
#define U8500_GPIO4_BASE (U8500_PER3_BASE + 0xE000 + 0x100)
#define U8500_GPIO5_BASE (U8500_PER3_BASE + 0xE000 + 0x180)
#define U8500_GPIO6_BASE (U8500_PER2_BASE + 0xE000)
#define U8500_GPIO7_BASE (U8500_PER2_BASE + 0xE000 + 0x80)
#define U8500_GPIO8_BASE (U8500_PER5_BASE + 0x1E000)
/* Per7 */
#define U8500_CLKRST7_BASE (U8500_PER7_BASE + 0xf000)
/* Per6 */
#define U8500_MTU0_BASE_V1 (U8500_PER6_BASE + 0x6000)
#define U8500_MTU1_BASE_V1 (U8500_PER6_BASE + 0x7000)
#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
/* Per5 */
#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000)
/* Per4 */
#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x0f000)
/* Per3 */
#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000)
/* Per2 */
#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
/* Per1 */
#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000)
/* Last page of Boot ROM */
#define U8500_BOOTROM_BASE 0x9001f000
#define U8500_BOOTROM_ASIC_ID_OFFSET 0x0ff4
#endif /* __ASM_ARCH_HARDWARE_H */

27
arch/arm/include/asm/arch-u8500/sys_proto.h
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/*
* Copyright (C) ST-Ericsson SA 2010
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
void gpio_init(void);
#endif /* _SYS_PROTO_H_ */

47
arch/arm/include/asm/arch-u8500/u8500.h
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/*
* Copyright (C) ST-Ericsson SA 2009
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __U8500_H
#define __U8500_H
/*
* base register values for U8500
*/
#define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock
Management Unit */
#define CFG_SDRAMC_BASE 0x903CF000 /* SDRAMC cnf registers */
#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */
/*
* U8500 GPIO register base for 9 banks
*/
#define U8500_GPIO_0_BASE 0x8012E000
#define U8500_GPIO_1_BASE 0x8012E080
#define U8500_GPIO_2_BASE 0x8000E000
#define U8500_GPIO_3_BASE 0x8000E080
#define U8500_GPIO_4_BASE 0x8000E100
#define U8500_GPIO_5_BASE 0x8000E180
#define U8500_GPIO_6_BASE 0x8011E000
#define U8500_GPIO_7_BASE 0x8011E080
#define U8500_GPIO_8_BASE 0xA03FE000
#endif /* __U8500_H */
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