commit
be9db564de
@ -0,0 +1,63 @@ |
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
|
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(SOC).o
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COBJS += generic.o
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COBJS += timer.o
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COBJS += iomux.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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all: $(obj).depend $(LIB) |
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$(LIB): $(OBJS) |
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$(call cmd_link_o_target, $(OBJS))
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$(OBJS) : $(TOPDIR)/include/asm/arch/asm-offsets.h |
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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$(TOPDIR)/include/asm/arch/asm-offsets.h: $(TOPDIR)/include/autoconf.mk.dep \
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./asm-offsets.s
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@echo Generating $@
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$(TOPDIR)/tools/scripts/make-asm-offsets ./asm-offsets.s $@
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asm-offsets.s: $(TOPDIR)/include/autoconf.mk.dep \
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./asm-offsets.c
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$(CC) -DDO_DEPS_ONLY \
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$(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
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-o $@ ./asm-offsets.c -c -S
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@ -0,0 +1,43 @@ |
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/*
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* Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c |
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* |
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* This program is used to generate definitions needed by |
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* assembly language modules. |
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* |
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* We use the technique used in the OSF Mach kernel code: |
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* generate asm statements containing #defines, |
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* compile this file to assembler, and then extract the |
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* #defines from the assembly-language output. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* as published by the Free Software Foundation; either version |
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* 2 of the License, or (at your option) any later version. |
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*/ |
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#include <common.h> |
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#include <asm/arch/imx-regs.h> |
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#include <linux/kbuild.h> |
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int main(void) |
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{ |
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/* Round up to make sure size gives nice stack alignment */ |
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DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr)); |
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DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0)); |
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DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1)); |
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DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2)); |
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DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3)); |
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DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4)); |
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DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr)); |
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DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl)); |
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DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl)); |
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DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr)); |
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DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr)); |
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DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0)); |
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DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1)); |
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DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2)); |
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return 0; |
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} |
@ -0,0 +1,463 @@ |
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/*
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* (C) Copyright 2007 |
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* Sascha Hauer, Pengutronix |
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* |
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* (C) Copyright 2008-2010 Freescale Semiconductor, Inc. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/errno.h> |
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#include <asm/arch/imx-regs.h> |
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#include <asm/arch/crm_regs.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/sys_proto.h> |
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#include <netdev.h> |
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#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel)) |
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#define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF) |
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#define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF) |
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#define CLK_CODE_PATH(c) ((c) & 0xFF) |
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#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o)) |
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#ifdef CONFIG_FSL_ESDHC |
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DECLARE_GLOBAL_DATA_PTR; |
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#endif |
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static int g_clk_mux_auto[8] = { |
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CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1, |
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CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1, |
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}; |
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static int g_clk_mux_consumer[16] = { |
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CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1, |
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-1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0), |
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CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1, |
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-1, -1, CLK_CODE(4, 2, 0), -1, |
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}; |
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static int hsp_div_table[3][16] = { |
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{4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1}, |
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{-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1}, |
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{3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1}, |
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}; |
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u32 get_cpu_rev(void) |
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{ |
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int reg; |
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struct iim_regs *iim = |
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(struct iim_regs *)IIM_BASE_ADDR; |
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reg = readl(&iim->iim_srev); |
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if (!reg) { |
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reg = readw(ROMPATCH_REV); |
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reg <<= 4; |
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} else { |
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reg += CHIP_REV_1_0; |
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} |
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return 0x35000 + (reg & 0xFF); |
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} |
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static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd) |
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{ |
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int *pclk_mux; |
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if (pdr0 & MXC_CCM_PDR0_AUTO_CON) { |
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pclk_mux = g_clk_mux_consumer + |
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((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >> |
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MXC_CCM_PDR0_CON_MUX_DIV_OFFSET); |
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} else { |
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pclk_mux = g_clk_mux_auto + |
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((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >> |
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MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET); |
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} |
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if ((*pclk_mux) == -1) |
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return -1; |
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if (fi && fd) { |
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if (!CLK_CODE_PATH(*pclk_mux)) { |
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*fi = *fd = 1; |
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return CLK_CODE_ARM(*pclk_mux); |
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} |
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if (pdr0 & MXC_CCM_PDR0_AUTO_CON) { |
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*fi = 3; |
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*fd = 4; |
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} else { |
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*fi = 2; |
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*fd = 3; |
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} |
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} |
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return CLK_CODE_ARM(*pclk_mux); |
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} |
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static int get_ahb_div(u32 pdr0) |
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{ |
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int *pclk_mux; |
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pclk_mux = g_clk_mux_consumer + |
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((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >> |
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MXC_CCM_PDR0_CON_MUX_DIV_OFFSET); |
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if ((*pclk_mux) == -1) |
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return -1; |
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return CLK_CODE_AHB(*pclk_mux); |
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} |
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static u32 decode_pll(u32 reg, u32 infreq) |
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{ |
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u32 mfi = (reg >> 10) & 0xf; |
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u32 mfn = reg & 0x3f; |
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u32 mfd = (reg >> 16) & 0x3f; |
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u32 pd = (reg >> 26) & 0xf; |
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mfi = mfi <= 5 ? 5 : mfi; |
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mfd += 1; |
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pd += 1; |
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return ((2 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000; |
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} |
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static u32 get_mcu_main_clk(void) |
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{ |
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u32 arm_div = 0, fi = 0, fd = 0; |
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struct ccm_regs *ccm = |
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(struct ccm_regs *)IMX_CCM_BASE; |
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arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd); |
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fi *= |
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decode_pll(readl(&ccm->mpctl), |
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CONFIG_MX35_HCLK_FREQ); |
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return fi / (arm_div * fd); |
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} |
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static u32 get_ipg_clk(void) |
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{ |
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u32 freq = get_mcu_main_clk(); |
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struct ccm_regs *ccm = |
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(struct ccm_regs *)IMX_CCM_BASE; |
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u32 pdr0 = readl(&ccm->pdr0); |
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return freq / (get_ahb_div(pdr0) * 2); |
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} |
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static u32 get_ipg_per_clk(void) |
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{ |
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u32 freq = get_mcu_main_clk(); |
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struct ccm_regs *ccm = |
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(struct ccm_regs *)IMX_CCM_BASE; |
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u32 pdr0 = readl(&ccm->pdr0); |
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u32 pdr4 = readl(&ccm->pdr4); |
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u32 div; |
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if (pdr0 & MXC_CCM_PDR0_PER_SEL) { |
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div = (CCM_GET_DIVIDER(pdr4, |
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MXC_CCM_PDR4_PER0_PRDF_MASK, |
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MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) * |
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(CCM_GET_DIVIDER(pdr4, |
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MXC_CCM_PDR4_PER0_PODF_MASK, |
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MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1); |
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} else { |
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div = CCM_GET_DIVIDER(pdr0, |
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MXC_CCM_PDR0_PER_PODF_MASK, |
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MXC_CCM_PDR0_PER_PODF_OFFSET) + 1; |
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freq /= get_ahb_div(pdr0); |
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} |
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return freq / div; |
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} |
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u32 imx_get_uartclk(void) |
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{ |
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u32 freq; |
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struct ccm_regs *ccm = |
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(struct ccm_regs *)IMX_CCM_BASE; |
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u32 pdr4 = readl(&ccm->pdr4); |
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|
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if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) { |
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freq = get_mcu_main_clk(); |
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} else { |
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freq = decode_pll(readl(&ccm->ppctl), |
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CONFIG_MX35_HCLK_FREQ); |
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} |
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freq /= ((CCM_GET_DIVIDER(pdr4, |
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MXC_CCM_PDR4_UART_PRDF_MASK, |
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MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) * |
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(CCM_GET_DIVIDER(pdr4, |
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MXC_CCM_PDR4_UART_PODF_MASK, |
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MXC_CCM_PDR4_UART_PODF_OFFSET) + 1)); |
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return freq; |
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} |
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|
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unsigned int mxc_get_main_clock(enum mxc_main_clocks clk) |
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{ |
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u32 nfc_pdf, hsp_podf; |
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u32 pll, ret_val = 0, usb_prdf, usb_podf; |
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struct ccm_regs *ccm = |
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(struct ccm_regs *)IMX_CCM_BASE; |
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|
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u32 reg = readl(&ccm->pdr0); |
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u32 reg4 = readl(&ccm->pdr4); |
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|
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reg |= 0x1; |
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|
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switch (clk) { |
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case CPU_CLK: |
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ret_val = get_mcu_main_clk(); |
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break; |
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case AHB_CLK: |
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ret_val = get_mcu_main_clk(); |
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break; |
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case HSP_CLK: |
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if (reg & CLKMODE_CONSUMER) { |
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hsp_podf = (reg >> 20) & 0x3; |
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pll = get_mcu_main_clk(); |
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hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF]; |
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if (hsp_podf > 0) { |
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ret_val = pll / hsp_podf; |
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} else { |
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puts("mismatch HSP with ARM clock setting\n"); |
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ret_val = 0; |
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} |
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} else { |
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ret_val = get_mcu_main_clk(); |
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} |
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break; |
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case IPG_CLK: |
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ret_val = get_ipg_clk();; |
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break; |
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case IPG_PER_CLK: |
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ret_val = get_ipg_per_clk(); |
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break; |
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case NFC_CLK: |
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nfc_pdf = (reg4 >> 28) & 0xF; |
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pll = get_mcu_main_clk(); |
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/* AHB/nfc_pdf */ |
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ret_val = pll / (nfc_pdf + 1); |
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break; |
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case USB_CLK: |
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usb_prdf = (reg4 >> 25) & 0x7; |
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usb_podf = (reg4 >> 22) & 0x7; |
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if (reg4 & 0x200) { |
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pll = get_mcu_main_clk(); |
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} else { |
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pll = decode_pll(readl(&ccm->ppctl), |
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CONFIG_MX35_HCLK_FREQ); |
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} |
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|
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ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1)); |
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break; |
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default: |
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printf("Unknown clock: %d\n", clk); |
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break; |
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} |
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|
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return ret_val; |
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} |
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unsigned int mxc_get_peri_clock(enum mxc_peri_clocks clk) |
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{ |
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u32 ret_val = 0, pdf, pre_pdf, clk_sel; |
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struct ccm_regs *ccm = |
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(struct ccm_regs *)IMX_CCM_BASE; |
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u32 mpdr2 = readl(&ccm->pdr2); |
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u32 mpdr3 = readl(&ccm->pdr3); |
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u32 mpdr4 = readl(&ccm->pdr4); |
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|
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switch (clk) { |
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case UART1_BAUD: |
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case UART2_BAUD: |
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case UART3_BAUD: |
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clk_sel = mpdr3 & (1 << 14); |
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pre_pdf = (mpdr4 >> 13) & 0x7; |
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pdf = (mpdr4 >> 10) & 0x7; |
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : |
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decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / |
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((pre_pdf + 1) * (pdf + 1)); |
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break; |
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case SSI1_BAUD: |
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pre_pdf = (mpdr2 >> 24) & 0x7; |
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pdf = mpdr2 & 0x3F; |
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clk_sel = mpdr2 & (1 << 6); |
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : |
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decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / |
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((pre_pdf + 1) * (pdf + 1)); |
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break; |
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case SSI2_BAUD: |
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pre_pdf = (mpdr2 >> 27) & 0x7; |
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pdf = (mpdr2 >> 8) & 0x3F; |
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clk_sel = mpdr2 & (1 << 6); |
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : |
||||
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / |
||||
((pre_pdf + 1) * (pdf + 1)); |
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break; |
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case CSI_BAUD: |
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clk_sel = mpdr2 & (1 << 7); |
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pre_pdf = (mpdr2 >> 16) & 0x7; |
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pdf = (mpdr2 >> 19) & 0x7; |
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : |
||||
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / |
||||
((pre_pdf + 1) * (pdf + 1)); |
||||
break; |
||||
case MSHC_CLK: |
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pre_pdf = readl(&ccm->pdr1); |
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clk_sel = (pre_pdf & 0x80); |
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pdf = (pre_pdf >> 22) & 0x3F; |
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pre_pdf = (pre_pdf >> 28) & 0x7; |
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ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : |
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decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / |
||||
((pre_pdf + 1) * (pdf + 1)); |
||||
break; |
||||
case ESDHC1_CLK: |
||||
clk_sel = mpdr3 & 0x40; |
||||
pre_pdf = mpdr3 & 0x7; |
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pdf = (mpdr3>>3) & 0x7; |
||||
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : |
||||
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / |
||||
((pre_pdf + 1) * (pdf + 1)); |
||||
break; |
||||
case ESDHC2_CLK: |
||||
clk_sel = mpdr3 & 0x40; |
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pre_pdf = (mpdr3 >> 8) & 0x7; |
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pdf = (mpdr3 >> 11) & 0x7; |
||||
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : |
||||
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / |
||||
((pre_pdf + 1) * (pdf + 1)); |
||||
break; |
||||
case ESDHC3_CLK: |
||||
clk_sel = mpdr3 & 0x40; |
||||
pre_pdf = (mpdr3 >> 16) & 0x7; |
||||
pdf = (mpdr3 >> 19) & 0x7; |
||||
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : |
||||
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / |
||||
((pre_pdf + 1) * (pdf + 1)); |
||||
break; |
||||
case SPDIF_CLK: |
||||
clk_sel = mpdr3 & 0x400000; |
||||
pre_pdf = (mpdr3 >> 29) & 0x7; |
||||
pdf = (mpdr3 >> 23) & 0x3F; |
||||
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : |
||||
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) / |
||||
((pre_pdf + 1) * (pdf + 1)); |
||||
break; |
||||
default: |
||||
printf("%s(): This clock: %d not supported yet\n", |
||||
__func__, clk); |
||||
break; |
||||
} |
||||
|
||||
return ret_val; |
||||
} |
||||
|
||||
unsigned int mxc_get_clock(enum mxc_clock clk) |
||||
{ |
||||
switch (clk) { |
||||
case MXC_ARM_CLK: |
||||
return get_mcu_main_clk(); |
||||
case MXC_AHB_CLK: |
||||
break; |
||||
case MXC_IPG_CLK: |
||||
return get_ipg_clk(); |
||||
case MXC_IPG_PERCLK: |
||||
return get_ipg_per_clk(); |
||||
case MXC_UART_CLK: |
||||
return imx_get_uartclk(); |
||||
case MXC_ESDHC_CLK: |
||||
return mxc_get_peri_clock(ESDHC1_CLK); |
||||
case MXC_USB_CLK: |
||||
return mxc_get_main_clock(USB_CLK); |
||||
case MXC_FEC_CLK: |
||||
return get_ipg_clk(); |
||||
case MXC_CSPI_CLK: |
||||
return get_ipg_clk(); |
||||
} |
||||
return -1; |
||||
} |
||||
|
||||
#ifdef CONFIG_FEC_MXC |
||||
/*
|
||||
* The MX35 has no fuse for MAC, return a NULL MAC |
||||
*/ |
||||
void imx_get_mac_from_fuse(unsigned char *mac) |
||||
{ |
||||
memset(mac, 0, 6); |
||||
} |
||||
|
||||
u32 imx_get_fecclk(void) |
||||
{ |
||||
return mxc_get_clock(MXC_IPG_CLK); |
||||
} |
||||
#endif |
||||
|
||||
int do_mx35_showclocks(cmd_tbl_t *cmdtp, |
||||
int flag, int argc, char * const argv[]) |
||||
{ |
||||
u32 cpufreq = get_mcu_main_clk(); |
||||
printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000); |
||||
printf("ipg clock : %dHz\n", get_ipg_clk()); |
||||
printf("ipg per clock : %dHz\n", get_ipg_per_clk()); |
||||
printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK)); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
U_BOOT_CMD( |
||||
clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks, |
||||
"display clocks\n", |
||||
"" |
||||
); |
||||
|
||||
#if defined(CONFIG_DISPLAY_CPUINFO) |
||||
int print_cpuinfo(void) |
||||
{ |
||||
printf("CPU: Freescale i.MX35 at %d MHz\n", |
||||
get_mcu_main_clk() / 1000000); |
||||
/* mxc_dump_clocks(); */ |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
/*
|
||||
* Initializes on-chip ethernet controllers. |
||||
* to override, implement board_eth_init() |
||||
*/ |
||||
|
||||
int cpu_eth_init(bd_t *bis) |
||||
{ |
||||
int rc = -ENODEV; |
||||
|
||||
#if defined(CONFIG_FEC_MXC) |
||||
rc = fecmxc_initialize(bis); |
||||
#endif |
||||
|
||||
return rc; |
||||
} |
||||
|
||||
int get_clocks(void) |
||||
{ |
||||
#ifdef CONFIG_FSL_ESDHC |
||||
gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
||||
#endif |
||||
return 0; |
||||
} |
||||
|
||||
void reset_cpu(ulong addr) |
||||
{ |
||||
struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; |
||||
writew(4, &wdog->wcr); |
||||
} |
@ -0,0 +1,116 @@ |
||||
/*
|
||||
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/imx-regs.h> |
||||
#include <asm/arch/mx35_pins.h> |
||||
#include <asm/arch/iomux.h> |
||||
|
||||
/*
|
||||
* IOMUX register (base) addresses |
||||
*/ |
||||
enum iomux_reg_addr { |
||||
IOMUXGPR = IOMUXC_BASE_ADDR, /* General purpose */ |
||||
IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR + 4, /* MUX control */ |
||||
IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + 0x324, /* last MUX control */ |
||||
IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + 0x328, /* Pad control */ |
||||
IOMUXSW_PAD_END = IOMUXC_BASE_ADDR + 0x794, /* last Pad control */ |
||||
IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + 0x7AC, /* input select */ |
||||
IOMUXSW_INPUT_END = IOMUXC_BASE_ADDR + 0x9F4, /* last input select */ |
||||
}; |
||||
|
||||
#define MUX_PIN_NUM_MAX \ |
||||
(((IOMUXSW_PAD_END - IOMUXSW_PAD_CTL) >> 2) + 1) |
||||
#define MUX_INPUT_NUM_MUX \ |
||||
(((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1) |
||||
|
||||
#define PIN_TO_IOMUX_INDEX(pin) ((PIN_TO_IOMUX_PAD(pin) - 0x328) >> 2) |
||||
|
||||
/*
|
||||
* Request ownership for an IO pin. This function has to be the first one |
||||
* being called before that pin is used. |
||||
*/ |
||||
void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) |
||||
{ |
||||
u32 mux_reg = PIN_TO_IOMUX_MUX(pin); |
||||
|
||||
if (mux_reg != NON_MUX_I) { |
||||
mux_reg += IOMUXGPR; |
||||
writel(cfg, mux_reg); |
||||
} |
||||
} |
||||
|
||||
/*
|
||||
* Release ownership for an IO pin |
||||
*/ |
||||
void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) |
||||
{ |
||||
} |
||||
|
||||
/*
|
||||
* This function configures the pad value for a IOMUX pin. |
||||
* |
||||
* @param pin a pin number as defined in iomux_pin_name_t |
||||
* @param config the ORed value of elements defined in iomux_pad_config_t |
||||
*/ |
||||
void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config) |
||||
{ |
||||
u32 pad_reg = IOMUXGPR + PIN_TO_IOMUX_PAD(pin); |
||||
|
||||
writel(config, pad_reg); |
||||
} |
||||
|
||||
/*
|
||||
* This function enables/disables the general purpose function for a particular |
||||
* signal. |
||||
* |
||||
* @param gp one signal as defined in iomux_gp_func_t |
||||
* @param en enable/disable |
||||
*/ |
||||
void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en) |
||||
{ |
||||
u32 l; |
||||
|
||||
l = readl(IOMUXGPR); |
||||
if (en) |
||||
l |= gp; |
||||
else |
||||
l &= ~gp; |
||||
|
||||
writel(l, IOMUXGPR); |
||||
} |
||||
|
||||
/*
|
||||
* This function configures input path. |
||||
* |
||||
* @param input index of input select register as defined in |
||||
* iomux_input_select_t |
||||
* @param config the binary value of elements defined in |
||||
* iomux_input_config_t |
||||
*/ |
||||
void mxc_iomux_set_input(iomux_input_select_t input, u32 config) |
||||
{ |
||||
u32 reg = IOMUXSW_INPUT_CTL + (input << 2); |
||||
|
||||
writel(config, reg); |
||||
} |
@ -0,0 +1,120 @@ |
||||
/*
|
||||
* (C) Copyright 2007 |
||||
* Sascha Hauer, Pengutronix |
||||
* |
||||
* (C) Copyright 2008-2009 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/imx-regs.h> |
||||
|
||||
/* General purpose timers bitfields */ |
||||
#define GPTCR_SWR (1<<15) /* Software reset */ |
||||
#define GPTCR_FRR (1<<9) /* Freerun / restart */ |
||||
#define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */ |
||||
#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */ |
||||
#define GPTCR_TEN (1) /* Timer enable */ |
||||
#define GPTPR_VAL (66) |
||||
|
||||
int timer_init(void) |
||||
{ |
||||
int i; |
||||
struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; |
||||
|
||||
/* setup GP Timer 1 */ |
||||
writel(GPTCR_SWR, &gpt->ctrl); |
||||
for (i = 0; i < 100; i++) |
||||
writel(0, &gpt->ctrl); /* We have no udelay by now */ |
||||
|
||||
writel(GPTPR_VAL, &gpt->pre); |
||||
/* Freerun Mode, PERCLK1 input */ |
||||
writel(readl(&gpt->ctrl) | |
||||
GPTCR_CLKSOURCE_IPG | GPTCR_TEN, |
||||
&gpt->ctrl); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void reset_timer_masked(void) |
||||
{ |
||||
struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; |
||||
|
||||
writel(0, &gpt->ctrl); |
||||
/* Freerun Mode, PERCLK1 input */ |
||||
writel(GPTCR_CLKSOURCE_IPG | GPTCR_TEN, |
||||
&gpt->ctrl); |
||||
} |
||||
|
||||
inline ulong get_timer_masked(void) |
||||
{ |
||||
|
||||
struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; |
||||
ulong val = readl(&gpt->counter); |
||||
|
||||
return val; |
||||
} |
||||
|
||||
void reset_timer(void) |
||||
{ |
||||
reset_timer_masked(); |
||||
} |
||||
|
||||
ulong get_timer(ulong base) |
||||
{ |
||||
ulong tmp; |
||||
|
||||
tmp = get_timer_masked(); |
||||
|
||||
if (tmp <= (base * 1000)) { |
||||
/* Overflow */ |
||||
tmp += (0xffffffff - base); |
||||
} |
||||
|
||||
return (tmp / 1000) - base; |
||||
} |
||||
|
||||
void set_timer(ulong t) |
||||
{ |
||||
} |
||||
|
||||
/*
|
||||
* delay x useconds AND preserve advance timstamp value |
||||
* GPTCNT is now supposed to tick 1 by 1 us. |
||||
*/ |
||||
void __udelay(unsigned long usec) |
||||
{ |
||||
ulong tmp; |
||||
|
||||
tmp = get_timer_masked(); /* get current timestamp */ |
||||
|
||||
/* if setting this forward will roll time stamp */ |
||||
if ((usec + tmp + 1) < tmp) { |
||||
/* reset "advancing" timestamp to 0, set lastinc value */ |
||||
reset_timer_masked(); |
||||
} else { |
||||
/* else, set advancing stamp wake up time */ |
||||
tmp += usec; |
||||
} |
||||
|
||||
while (get_timer_masked() < tmp) /* loop till event */ |
||||
/*NOP*/; |
||||
} |
@ -0,0 +1,55 @@ |
||||
/*
|
||||
* LSI ET1011C PHY Driver for TI DaVinci(TMS320DM6467) board. |
||||
* |
||||
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <net.h> |
||||
#include <miiphy.h> |
||||
#include <asm/arch/emac_defs.h> |
||||
|
||||
#ifdef CONFIG_DRIVER_TI_EMAC |
||||
|
||||
#ifdef CONFIG_CMD_NET |
||||
|
||||
/* LSI PHYSICAL LAYER TRANSCEIVER ET1011C */ |
||||
|
||||
#define MII_PHY_CONFIG_REG 22 |
||||
|
||||
/* PHY Config bits */ |
||||
#define PHY_SYS_CLK_EN (1 << 4) |
||||
|
||||
int et1011c_get_link_speed(int phy_addr) |
||||
{ |
||||
u_int16_t data; |
||||
|
||||
if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &data) && (data & 0x04)) { |
||||
davinci_eth_phy_read(EMAC_MDIO_PHY_NUM, |
||||
MII_PHY_CONFIG_REG, &data); |
||||
/* Enable 125MHz clock sourced from PHY */ |
||||
davinci_eth_phy_write(EMAC_MDIO_PHY_NUM, |
||||
MII_PHY_CONFIG_REG, |
||||
data | PHY_SYS_CLK_EN); |
||||
return (1); |
||||
} |
||||
return (0); |
||||
} |
||||
|
||||
#endif /* CONFIG_CMD_NET */ |
||||
|
||||
#endif /* CONFIG_DRIVER_ETHER */ |
@ -0,0 +1,42 @@ |
||||
#
|
||||
# Copyright (C) 2009 Samsung Electronics
|
||||
# Minkyu Kang <mk7.kang@samsung.com>
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(SOC).o
|
||||
|
||||
COBJS += clock.o soc.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
|
||||
|
||||
all: $(obj).depend $(LIB) |
||||
|
||||
$(LIB): $(OBJS) |
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
@ -0,0 +1,220 @@ |
||||
/*
|
||||
* Copyright (C) 2010 Samsung Electronics |
||||
* Minkyu Kang <mk7.kang@samsung.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/clk.h> |
||||
|
||||
#ifndef CONFIG_SYS_CLK_FREQ_C210 |
||||
#define CONFIG_SYS_CLK_FREQ_C210 24000000 |
||||
#endif |
||||
|
||||
/* s5pc210: return pll clock frequency */ |
||||
static unsigned long s5pc210_get_pll_clk(int pllreg) |
||||
{ |
||||
struct s5pc210_clock *clk = |
||||
(struct s5pc210_clock *)samsung_get_base_clock(); |
||||
unsigned long r, m, p, s, k = 0, mask, fout; |
||||
unsigned int freq; |
||||
|
||||
switch (pllreg) { |
||||
case APLL: |
||||
r = readl(&clk->apll_con0); |
||||
break; |
||||
case MPLL: |
||||
r = readl(&clk->mpll_con0); |
||||
break; |
||||
case EPLL: |
||||
r = readl(&clk->epll_con0); |
||||
k = readl(&clk->epll_con1); |
||||
break; |
||||
case VPLL: |
||||
r = readl(&clk->vpll_con0); |
||||
k = readl(&clk->vpll_con1); |
||||
break; |
||||
default: |
||||
printf("Unsupported PLL (%d)\n", pllreg); |
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* APLL_CON: MIDV [25:16] |
||||
* MPLL_CON: MIDV [25:16] |
||||
* EPLL_CON: MIDV [24:16] |
||||
* VPLL_CON: MIDV [24:16] |
||||
*/ |
||||
if (pllreg == APLL || pllreg == MPLL) |
||||
mask = 0x3ff; |
||||
else |
||||
mask = 0x1ff; |
||||
|
||||
m = (r >> 16) & mask; |
||||
|
||||
/* PDIV [13:8] */ |
||||
p = (r >> 8) & 0x3f; |
||||
/* SDIV [2:0] */ |
||||
s = r & 0x7; |
||||
|
||||
freq = CONFIG_SYS_CLK_FREQ_C210; |
||||
|
||||
if (pllreg == EPLL) { |
||||
k = k & 0xffff; |
||||
/* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */ |
||||
fout = (m + k / 65536) * (freq / (p * (1 << s))); |
||||
} else if (pllreg == VPLL) { |
||||
k = k & 0xfff; |
||||
/* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */ |
||||
fout = (m + k / 1024) * (freq / (p * (1 << s))); |
||||
} else { |
||||
if (s < 1) |
||||
s = 1; |
||||
/* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */ |
||||
fout = m * (freq / (p * (1 << (s - 1)))); |
||||
} |
||||
|
||||
return fout; |
||||
} |
||||
|
||||
/* s5pc210: return ARM clock frequency */ |
||||
static unsigned long s5pc210_get_arm_clk(void) |
||||
{ |
||||
struct s5pc210_clock *clk = |
||||
(struct s5pc210_clock *)samsung_get_base_clock(); |
||||
unsigned long div; |
||||
unsigned long dout_apll; |
||||
unsigned int apll_ratio; |
||||
|
||||
div = readl(&clk->div_cpu0); |
||||
|
||||
/* APLL_RATIO: [26:24] */ |
||||
apll_ratio = (div >> 24) & 0x7; |
||||
|
||||
dout_apll = get_pll_clk(APLL) / (apll_ratio + 1); |
||||
|
||||
return dout_apll; |
||||
} |
||||
|
||||
/* s5pc210: return pwm clock frequency */ |
||||
static unsigned long s5pc210_get_pwm_clk(void) |
||||
{ |
||||
struct s5pc210_clock *clk = |
||||
(struct s5pc210_clock *)samsung_get_base_clock(); |
||||
unsigned long pclk, sclk; |
||||
unsigned int sel; |
||||
unsigned int ratio; |
||||
|
||||
/*
|
||||
* CLK_SRC_PERIL0 |
||||
* PWM_SEL [27:24] |
||||
*/ |
||||
sel = readl(&clk->src_peril0); |
||||
sel = (sel >> 24) & 0xf; |
||||
|
||||
if (sel == 0x6) |
||||
sclk = get_pll_clk(MPLL); |
||||
else if (sel == 0x7) |
||||
sclk = get_pll_clk(EPLL); |
||||
else if (sel == 0x8) |
||||
sclk = get_pll_clk(VPLL); |
||||
else |
||||
return 0; |
||||
|
||||
/*
|
||||
* CLK_DIV_PERIL3 |
||||
* PWM_RATIO [3:0] |
||||
*/ |
||||
ratio = readl(&clk->div_peril3); |
||||
ratio = ratio & 0xf; |
||||
|
||||
pclk = sclk / (ratio + 1); |
||||
|
||||
return pclk; |
||||
} |
||||
|
||||
/* s5pc210: return uart clock frequency */ |
||||
static unsigned long s5pc210_get_uart_clk(int dev_index) |
||||
{ |
||||
struct s5pc210_clock *clk = |
||||
(struct s5pc210_clock *)samsung_get_base_clock(); |
||||
unsigned long uclk, sclk; |
||||
unsigned int sel; |
||||
unsigned int ratio; |
||||
|
||||
/*
|
||||
* CLK_SRC_PERIL0 |
||||
* UART0_SEL [3:0] |
||||
* UART1_SEL [7:4] |
||||
* UART2_SEL [8:11] |
||||
* UART3_SEL [12:15] |
||||
* UART4_SEL [16:19] |
||||
* UART5_SEL [23:20] |
||||
*/ |
||||
sel = readl(&clk->src_peril0); |
||||
sel = (sel >> (dev_index << 2)) & 0xf; |
||||
|
||||
if (sel == 0x6) |
||||
sclk = get_pll_clk(MPLL); |
||||
else if (sel == 0x7) |
||||
sclk = get_pll_clk(EPLL); |
||||
else if (sel == 0x8) |
||||
sclk = get_pll_clk(VPLL); |
||||
else |
||||
return 0; |
||||
|
||||
/*
|
||||
* CLK_DIV_PERIL0 |
||||
* UART0_RATIO [3:0] |
||||
* UART1_RATIO [7:4] |
||||
* UART2_RATIO [8:11] |
||||
* UART3_RATIO [12:15] |
||||
* UART4_RATIO [16:19] |
||||
* UART5_RATIO [23:20] |
||||
*/ |
||||
ratio = readl(&clk->div_peril0); |
||||
ratio = (ratio >> (dev_index << 2)) & 0xf; |
||||
|
||||
uclk = sclk / (ratio + 1); |
||||
|
||||
return uclk; |
||||
} |
||||
|
||||
unsigned long get_pll_clk(int pllreg) |
||||
{ |
||||
return s5pc210_get_pll_clk(pllreg); |
||||
} |
||||
|
||||
unsigned long get_arm_clk(void) |
||||
{ |
||||
return s5pc210_get_arm_clk(); |
||||
} |
||||
|
||||
unsigned long get_pwm_clk(void) |
||||
{ |
||||
return s5pc210_get_pwm_clk(); |
||||
} |
||||
|
||||
unsigned long get_uart_clk(int dev_index) |
||||
{ |
||||
return s5pc210_get_uart_clk(dev_index); |
||||
} |
@ -0,0 +1,30 @@ |
||||
/*
|
||||
* Copyright (c) 2010 Samsung Electronics. |
||||
* Minkyu Kang <mk7.kang@samsung.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
|
||||
void reset_cpu(ulong addr) |
||||
{ |
||||
writel(0x1, samsung_get_base_swreset()); |
||||
} |
@ -0,0 +1,175 @@ |
||||
/*
|
||||
* Davinci MMC Controller Defines - Based on Linux davinci_mmc.c |
||||
* |
||||
* Copyright (C) 2010 Texas Instruments Incorporated |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
*/ |
||||
|
||||
#ifndef _SDMMC_DEFS_H_ |
||||
#define _SDMMC_DEFS_H_ |
||||
|
||||
#include <asm/arch/hardware.h> |
||||
|
||||
/* MMC Control Reg fields */ |
||||
#define MMCCTL_DATRST (1 << 0) |
||||
#define MMCCTL_CMDRST (1 << 1) |
||||
#define MMCCTL_WIDTH_4_BIT (1 << 2) |
||||
#define MMCCTL_DATEG_DISABLED (0 << 6) |
||||
#define MMCCTL_DATEG_RISING (1 << 6) |
||||
#define MMCCTL_DATEG_FALLING (2 << 6) |
||||
#define MMCCTL_DATEG_BOTH (3 << 6) |
||||
#define MMCCTL_PERMDR_LE (0 << 9) |
||||
#define MMCCTL_PERMDR_BE (1 << 9) |
||||
#define MMCCTL_PERMDX_LE (0 << 10) |
||||
#define MMCCTL_PERMDX_BE (1 << 10) |
||||
|
||||
/* MMC Clock Control Reg fields */ |
||||
#define MMCCLK_CLKEN (1 << 8) |
||||
#define MMCCLK_CLKRT_MASK (0xFF << 0) |
||||
|
||||
/* MMC Status Reg0 fields */ |
||||
#define MMCST0_DATDNE (1 << 0) |
||||
#define MMCST0_BSYDNE (1 << 1) |
||||
#define MMCST0_RSPDNE (1 << 2) |
||||
#define MMCST0_TOUTRD (1 << 3) |
||||
#define MMCST0_TOUTRS (1 << 4) |
||||
#define MMCST0_CRCWR (1 << 5) |
||||
#define MMCST0_CRCRD (1 << 6) |
||||
#define MMCST0_CRCRS (1 << 7) |
||||
#define MMCST0_DXRDY (1 << 9) |
||||
#define MMCST0_DRRDY (1 << 10) |
||||
#define MMCST0_DATED (1 << 11) |
||||
#define MMCST0_TRNDNE (1 << 12) |
||||
|
||||
#define MMCST0_ERR_MASK (0x00F8) |
||||
|
||||
/* MMC Status Reg1 fields */ |
||||
#define MMCST1_BUSY (1 << 0) |
||||
#define MMCST1_CLKSTP (1 << 1) |
||||
#define MMCST1_DXEMP (1 << 2) |
||||
#define MMCST1_DRFUL (1 << 3) |
||||
#define MMCST1_DAT3ST (1 << 4) |
||||
#define MMCST1_FIFOEMP (1 << 5) |
||||
#define MMCST1_FIFOFUL (1 << 6) |
||||
|
||||
/* MMC INT Mask Reg fields */ |
||||
#define MMCIM_EDATDNE (1 << 0) |
||||
#define MMCIM_EBSYDNE (1 << 1) |
||||
#define MMCIM_ERSPDNE (1 << 2) |
||||
#define MMCIM_ETOUTRD (1 << 3) |
||||
#define MMCIM_ETOUTRS (1 << 4) |
||||
#define MMCIM_ECRCWR (1 << 5) |
||||
#define MMCIM_ECRCRD (1 << 6) |
||||
#define MMCIM_ECRCRS (1 << 7) |
||||
#define MMCIM_EDXRDY (1 << 9) |
||||
#define MMCIM_EDRRDY (1 << 10) |
||||
#define MMCIM_EDATED (1 << 11) |
||||
#define MMCIM_ETRNDNE (1 << 12) |
||||
|
||||
#define MMCIM_MASKALL (0xFFFFFFFF) |
||||
|
||||
/* MMC Resp Tout Reg fields */ |
||||
#define MMCTOR_TOR_MASK (0xFF) /* dont write to reg, | it */ |
||||
#define MMCTOR_TOD_20_16_SHIFT (8) |
||||
|
||||
/* MMC Data Read Tout Reg fields */ |
||||
#define MMCTOD_TOD_0_15_MASK (0xFFFF) |
||||
|
||||
/* MMC Block len Reg fields */ |
||||
#define MMCBLEN_BLEN_MASK (0xFFF) |
||||
|
||||
/* MMC Num Blocks Reg fields */ |
||||
#define MMCNBLK_NBLK_MASK (0xFFFF) |
||||
#define MMCNBLK_NBLK_MAX (0xFFFF) |
||||
|
||||
/* MMC Num Blocks Counter Reg fields */ |
||||
#define MMCNBLC_NBLC_MASK (0xFFFF) |
||||
|
||||
/* MMC Cmd Reg fields */ |
||||
#define MMCCMD_CMD_MASK (0x3F) |
||||
#define MMCCMD_PPLEN (1 << 7) |
||||
#define MMCCMD_BSYEXP (1 << 8) |
||||
#define MMCCMD_RSPFMT_NONE (0 << 9) |
||||
#define MMCCMD_RSPFMT_R1567 (1 << 9) |
||||
#define MMCCMD_RSPFMT_R2 (2 << 9) |
||||
#define MMCCMD_RSPFMT_R3 (3 << 9) |
||||
#define MMCCMD_DTRW (1 << 11) |
||||
#define MMCCMD_STRMTP (1 << 12) |
||||
#define MMCCMD_WDATX (1 << 13) |
||||
#define MMCCMD_INITCK (1 << 14) |
||||
#define MMCCMD_DCLR (1 << 15) |
||||
#define MMCCMD_DMATRIG (1 << 16) |
||||
|
||||
/* FIFO control Reg fields */ |
||||
#define MMCFIFOCTL_FIFORST (1 << 0) |
||||
#define MMCFIFOCTL_FIFODIR (1 << 1) |
||||
#define MMCFIFOCTL_FIFOLEV (1 << 2) |
||||
#define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */ |
||||
#define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */ |
||||
#define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */ |
||||
#define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */ |
||||
|
||||
/* Davinci MMC Register definitions */ |
||||
struct davinci_mmc_regs { |
||||
dv_reg mmcctl; |
||||
dv_reg mmcclk; |
||||
dv_reg mmcst0; |
||||
dv_reg mmcst1; |
||||
dv_reg mmcim; |
||||
dv_reg mmctor; |
||||
dv_reg mmctod; |
||||
dv_reg mmcblen; |
||||
dv_reg mmcnblk; |
||||
dv_reg mmcnblc; |
||||
dv_reg mmcdrr; |
||||
dv_reg mmcdxr; |
||||
dv_reg mmccmd; |
||||
dv_reg mmcarghl; |
||||
dv_reg mmcrsp01; |
||||
dv_reg mmcrsp23; |
||||
dv_reg mmcrsp45; |
||||
dv_reg mmcrsp67; |
||||
dv_reg mmcdrsp; |
||||
dv_reg mmcetok; |
||||
dv_reg mmccidx; |
||||
dv_reg mmcckc; |
||||
dv_reg mmctorc; |
||||
dv_reg mmctodc; |
||||
dv_reg mmcblnc; |
||||
dv_reg sdioctl; |
||||
dv_reg sdiost0; |
||||
dv_reg sdioien; |
||||
dv_reg sdioist; |
||||
dv_reg mmcfifoctl; |
||||
}; |
||||
|
||||
/* Davinci MMC board definitions */ |
||||
struct davinci_mmc { |
||||
struct davinci_mmc_regs *reg_base; /* Register base address */ |
||||
uint input_clk; /* Input clock to MMC controller */ |
||||
uint host_caps; /* Host capabilities */ |
||||
uint voltages; /* Host supported voltages */ |
||||
uint version; /* MMC Controller version */ |
||||
}; |
||||
|
||||
enum { |
||||
MMC_CTLR_VERSION_1 = 0, /* DM644x and DM355 */ |
||||
MMC_CTLR_VERSION_2, /* DA830 */ |
||||
}; |
||||
|
||||
int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host); |
||||
|
||||
#endif /* _SDMMC_DEFS_H */ |
@ -0,0 +1,45 @@ |
||||
/*
|
||||
* (C) Copyright 2011 |
||||
* Stefano Babic, DENX Software Engineering, sbabic@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARCH_CLOCK_H |
||||
#define __ASM_ARCH_CLOCK_H |
||||
|
||||
enum mxc_clock { |
||||
MXC_ARM_CLK = 0, |
||||
MXC_AHB_CLK, |
||||
MXC_IPG_CLK, |
||||
MXC_IPG_PERCLK, |
||||
MXC_UART_CLK, |
||||
MXC_ESDHC_CLK, |
||||
MXC_USB_CLK, |
||||
MXC_CSPI_CLK, |
||||
MXC_FEC_CLK, |
||||
}; |
||||
|
||||
unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); |
||||
|
||||
u32 imx_get_uartclk(void); |
||||
u32 imx_get_fecclk(void); |
||||
unsigned int mxc_get_clock(enum mxc_clock clk); |
||||
|
||||
#endif /* __ASM_ARCH_CLOCK_H */ |
@ -0,0 +1,270 @@ |
||||
/*
|
||||
* Copyright 2004-2009 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CPU_ARM1136_MX35_CRM_REGS_H__ |
||||
#define __CPU_ARM1136_MX35_CRM_REGS_H__ |
||||
|
||||
/* Register bit definitions */ |
||||
#define MXC_CCM_CCMR_WFI (1 << 30) |
||||
#define MXC_CCM_CCMR_STBY_EXIT_SRC (1 << 29) |
||||
#define MXC_CCM_CCMR_VSTBY (1 << 28) |
||||
#define MXC_CCM_CCMR_WBEN (1 << 27) |
||||
#define MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET 20 |
||||
#define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20) |
||||
#define MXC_CCM_CCMR_ROMW_OFFSET 18 |
||||
#define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18) |
||||
#define MXC_CCM_CCMR_RAMW_OFFSET 21 |
||||
#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 21) |
||||
#define MXC_CCM_CCMR_LPM_OFFSET 14 |
||||
#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) |
||||
#define MXC_CCM_CCMR_UPE (1 << 9) |
||||
#define MXC_CCM_CCMR_MPE (1 << 3) |
||||
|
||||
#define MXC_CCM_PDR0_PER_SEL (1 << 26) |
||||
#define MXC_CCM_PDR0_IPU_HND_BYP (1 << 23) |
||||
#define MXC_CCM_PDR0_HSP_PODF_OFFSET 20 |
||||
#define MXC_CCM_PDR0_HSP_PODF_MASK (0x3 << 20) |
||||
#define MXC_CCM_PDR0_CON_MUX_DIV_OFFSET 16 |
||||
#define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16) |
||||
#define MXC_CCM_PDR0_CKIL_SEL (1 << 15) |
||||
#define MXC_CCM_PDR0_PER_PODF_OFFSET 12 |
||||
#define MXC_CCM_PDR0_PER_PODF_MASK (0xF << 12) |
||||
#define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9 |
||||
#define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9) |
||||
#define MXC_CCM_PDR0_AUTO_CON 0x1 |
||||
|
||||
#define MXC_CCM_PDR1_MSHC_PRDF_OFFSET 28 |
||||
#define MXC_CCM_PDR1_MSHC_PRDF_MASK (0x7 << 28) |
||||
#define MXC_CCM_PDR1_MSHC_PODF_OFFSET 22 |
||||
#define MXC_CCM_PDR1_MSHC_PODF_MASK (0x3F << 22) |
||||
#define MXC_CCM_PDR1_MSHC_M_U (1 << 7) |
||||
|
||||
#define MXC_CCM_PDR2_SSI2_PRDF_OFFSET 27 |
||||
#define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27) |
||||
#define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24 |
||||
#define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24) |
||||
#define MXC_CCM_PDR2_CSI_PRDF_OFFSET 19 |
||||
#define MXC_CCM_PDR2_CSI_PRDF_MASK (0x7 << 19) |
||||
#define MXC_CCM_PDR2_CSI_PODF_OFFSET 16 |
||||
#define MXC_CCM_PDR2_CSI_PODF_MASK (0x7 << 16) |
||||
#define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8 |
||||
#define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8) |
||||
#define MXC_CCM_PDR2_CSI_M_U (1 << 7) |
||||
#define MXC_CCM_PDR2_SSI_M_U (1 << 6) |
||||
#define MXC_CCM_PDR2_SSI1_PODF_OFFSET 0 |
||||
#define MXC_CCM_PDR2_SSI1_PODF_MASK (0x3F) |
||||
|
||||
#define MXC_CCM_PDR3_SPDIF_PRDF_OFFSET 29 |
||||
#define MXC_CCM_PDR3_SPDIF_PRDF_MASK (0x7 << 29) |
||||
#define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23 |
||||
#define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23) |
||||
#define MXC_CCM_PDR3_SPDIF_M_U (1 << 22) |
||||
#define MXC_CCM_PDR3_ESDHC3_PRDF_OFFSET 19 |
||||
#define MXC_CCM_PDR3_ESDHC3_PRDF_MASK (0x7 << 19) |
||||
#define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16 |
||||
#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x7 << 16) |
||||
#define MXC_CCM_PDR3_UART_M_U (1 << 15) |
||||
#define MXC_CCM_PDR3_ESDHC2_PRDF_OFFSET 11 |
||||
#define MXC_CCM_PDR3_ESDHC2_PRDF_MASK (0x7 << 11) |
||||
#define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8 |
||||
#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x7 << 8) |
||||
#define MXC_CCM_PDR3_ESDHC_M_U (1 << 6) |
||||
#define MXC_CCM_PDR3_ESDHC1_PRDF_OFFSET 3 |
||||
#define MXC_CCM_PDR3_ESDHC1_PRDF_MASK (0x7 << 3) |
||||
#define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0 |
||||
#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x7) |
||||
|
||||
#define MXC_CCM_PDR4_NFC_PODF_OFFSET 28 |
||||
#define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28) |
||||
#define MXC_CCM_PDR4_USB_PRDF_OFFSET 25 |
||||
#define MXC_CCM_PDR4_USB_PRDF_MASK (0x7 << 25) |
||||
#define MXC_CCM_PDR4_USB_PODF_OFFSET 22 |
||||
#define MXC_CCM_PDR4_USB_PODF_MASK (0x7 << 22) |
||||
#define MXC_CCM_PDR4_PER0_PRDF_OFFSET 19 |
||||
#define MXC_CCM_PDR4_PER0_PRDF_MASK (0x7 << 19) |
||||
#define MXC_CCM_PDR4_PER0_PODF_OFFSET 16 |
||||
#define MXC_CCM_PDR4_PER0_PODF_MASK (0x7 << 16) |
||||
#define MXC_CCM_PDR4_UART_PRDF_OFFSET 13 |
||||
#define MXC_CCM_PDR4_UART_PRDF_MASK (0x7 << 13) |
||||
#define MXC_CCM_PDR4_UART_PODF_OFFSET 10 |
||||
#define MXC_CCM_PDR4_UART_PODF_MASK (0x7 << 10) |
||||
#define MXC_CCM_PDR4_USB_M_U (1 << 9) |
||||
|
||||
/* Bit definitions for RCSR */ |
||||
#define MXC_CCM_RCSR_BUS_WIDTH (1 << 29) |
||||
#define MXC_CCM_RCSR_BUS_16BIT (1 << 29) |
||||
#define MXC_CCM_RCSR_PAGE_SIZE (3 << 27) |
||||
#define MXC_CCM_RCSR_PAGE_512 (0 << 27) |
||||
#define MXC_CCM_RCSR_PAGE_2K (1 << 27) |
||||
#define MXC_CCM_RCSR_PAGE_4K1 (2 << 27) |
||||
#define MXC_CCM_RCSR_PAGE_4K2 (3 << 27) |
||||
#define MXC_CCM_RCSR_SOFT_RESET (1 << 15) |
||||
#define MXC_CCM_RCSR_NF16B (1 << 14) |
||||
#define MXC_CCM_RCSR_NFC_4K (1 << 9) |
||||
#define MXC_CCM_RCSR_NFC_FMS (1 << 8) |
||||
|
||||
/* Bit definitions for both MCU, PERIPHERAL PLL control registers */ |
||||
#define MXC_CCM_PCTL_BRM 0x80000000 |
||||
#define MXC_CCM_PCTL_PD_OFFSET 26 |
||||
#define MXC_CCM_PCTL_PD_MASK (0xF << 26) |
||||
#define MXC_CCM_PCTL_MFD_OFFSET 16 |
||||
#define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16) |
||||
#define MXC_CCM_PCTL_MFI_OFFSET 10 |
||||
#define MXC_CCM_PCTL_MFI_MASK (0xF << 10) |
||||
#define MXC_CCM_PCTL_MFN_OFFSET 0 |
||||
#define MXC_CCM_PCTL_MFN_MASK 0x3FF |
||||
|
||||
/* Bit definitions for Audio clock mux register*/ |
||||
#define MXC_CCM_ACMR_ESAI_CLK_SEL_OFFSET 12 |
||||
#define MXC_CCM_ACMR_ESAI_CLK_SEL_MASK (0xF << 12) |
||||
#define MXC_CCM_ACMR_SPDIF_CLK_SEL_OFFSET 8 |
||||
#define MXC_CCM_ACMR_SPDIF_CLK_SEL_MASK (0xF << 8) |
||||
#define MXC_CCM_ACMR_SSI1_CLK_SEL_OFFSET 4 |
||||
#define MXC_CCM_ACMR_SSI1_CLK_SEL_MASK (0xF << 4) |
||||
#define MXC_CCM_ACMR_SSI2_CLK_SEL_OFFSET 0 |
||||
#define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0) |
||||
|
||||
/* Bit definitions for Clock gating Register*/ |
||||
#define MXC_CCM_CGR0_ASRC_OFFSET 0 |
||||
#define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0) |
||||
#define MXC_CCM_CGR0_ATA_OFFSET 2 |
||||
#define MXC_CCM_CGR0_ATA_MASK (0x3 << 2) |
||||
#define MXC_CCM_CGR0_CAN1_OFFSET 6 |
||||
#define MXC_CCM_CGR0_CAN1_MASK (0x3 << 6) |
||||
#define MXC_CCM_CGR0_CAN2_OFFSET 8 |
||||
#define MXC_CCM_CGR0_CAN2_MASK (0x3 << 8) |
||||
#define MXC_CCM_CGR0_CSPI1_OFFSET 10 |
||||
#define MXC_CCM_CGR0_CSPI1_MASK (0x3 << 10) |
||||
#define MXC_CCM_CGR0_CSPI2_OFFSET 12 |
||||
#define MXC_CCM_CGR0_CSPI2_MASK (0x3 << 12) |
||||
#define MXC_CCM_CGR0_ECT_OFFSET 14 |
||||
#define MXC_CCM_CGR0_ECT_MASK (0x3 << 14) |
||||
#define MXC_CCM_CGR0_EDI0_OFFSET 16 |
||||
#define MXC_CCM_CGR0_EDI0_MASK (0x3 << 16) |
||||
#define MXC_CCM_CGR0_EMI_OFFSET 18 |
||||
#define MXC_CCM_CGR0_EMI_MASK (0x3 << 18) |
||||
#define MXC_CCM_CGR0_EPIT1_OFFSET 20 |
||||
#define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 20) |
||||
#define MXC_CCM_CGR0_EPIT2_OFFSET 22 |
||||
#define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 22) |
||||
#define MXC_CCM_CGR0_ESAI_OFFSET 24 |
||||
#define MXC_CCM_CGR0_ESAI_MASK (0x3 << 24) |
||||
#define MXC_CCM_CGR0_ESDHC1_OFFSET 26 |
||||
#define MXC_CCM_CGR0_ESDHC1_MASK (0x3 << 26) |
||||
#define MXC_CCM_CGR0_ESDHC2_OFFSET 28 |
||||
#define MXC_CCM_CGR0_ESDHC2_MASK (0x3 << 28) |
||||
#define MXC_CCM_CGR0_ESDHC3_OFFSET 30 |
||||
#define MXC_CCM_CGR0_ESDHC3_MASK (0x3 << 30) |
||||
|
||||
#define MXC_CCM_CGR1_FEC_OFFSET 0 |
||||
#define MXC_CCM_CGR1_FEC_MASK (0x3 << 0) |
||||
#define MXC_CCM_CGR1_GPIO1_OFFSET 2 |
||||
#define MXC_CCM_CGR1_GPIO1_MASK (0x3 << 2) |
||||
#define MXC_CCM_CGR1_GPIO2_OFFSET 4 |
||||
#define MXC_CCM_CGR1_GPIO2_MASK (0x3 << 4) |
||||
#define MXC_CCM_CGR1_GPIO3_OFFSET 6 |
||||
#define MXC_CCM_CGR1_GPIO3_MASK (0x3 << 6) |
||||
#define MXC_CCM_CGR1_GPT_OFFSET 8 |
||||
#define MXC_CCM_CGR1_GPT_MASK (0x3 << 8) |
||||
#define MXC_CCM_CGR1_I2C1_OFFSET 10 |
||||
#define MXC_CCM_CGR1_I2C1_MASK (0x3 << 10) |
||||
#define MXC_CCM_CGR1_I2C2_OFFSET 12 |
||||
#define MXC_CCM_CGR1_I2C2_MASK (0x3 << 12) |
||||
#define MXC_CCM_CGR1_I2C3_OFFSET 14 |
||||
#define MXC_CCM_CGR1_I2C3_MASK (0x3 << 14) |
||||
#define MXC_CCM_CGR1_IOMUXC_OFFSET 16 |
||||
#define MXC_CCM_CGR1_IOMUXC_MASK (0x3 << 16) |
||||
#define MXC_CCM_CGR1_IPU_OFFSET 18 |
||||
#define MXC_CCM_CGR1_IPU_MASK (0x3 << 18) |
||||
#define MXC_CCM_CGR1_KPP_OFFSET 20 |
||||
#define MXC_CCM_CGR1_KPP_MASK (0x3 << 20) |
||||
#define MXC_CCM_CGR1_MLB_OFFSET 22 |
||||
#define MXC_CCM_CGR1_MLB_MASK (0x3 << 22) |
||||
#define MXC_CCM_CGR1_MSHC_OFFSET 24 |
||||
#define MXC_CCM_CGR1_MSHC_MASK (0x3 << 24) |
||||
#define MXC_CCM_CGR1_OWIRE_OFFSET 26 |
||||
#define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 26) |
||||
#define MXC_CCM_CGR1_PWM_OFFSET 28 |
||||
#define MXC_CCM_CGR1_PWM_MASK (0x3 << 28) |
||||
#define MXC_CCM_CGR1_RNGC_OFFSET 30 |
||||
#define MXC_CCM_CGR1_RNGC_MASK (0x3 << 30) |
||||
|
||||
#define MXC_CCM_CGR2_RTC_OFFSET 0 |
||||
#define MXC_CCM_CGR2_RTC_MASK (0x3 << 0) |
||||
#define MXC_CCM_CGR2_RTIC_OFFSET 2 |
||||
#define MXC_CCM_CGR2_RTIC_MASK (0x3 << 2) |
||||
#define MXC_CCM_CGR2_SCC_OFFSET 4 |
||||
#define MXC_CCM_CGR2_SCC_MASK (0x3 << 4) |
||||
#define MXC_CCM_CGR2_SDMA_OFFSET 6 |
||||
#define MXC_CCM_CGR2_SDMA_MASK (0x3 << 6) |
||||
#define MXC_CCM_CGR2_SPBA_OFFSET 8 |
||||
#define MXC_CCM_CGR2_SPBA_MASK (0x3 << 8) |
||||
#define MXC_CCM_CGR2_SPDIF_OFFSET 10 |
||||
#define MXC_CCM_CGR2_SPDIF_MASK (0x3 << 10) |
||||
#define MXC_CCM_CGR2_SSI1_OFFSET 12 |
||||
#define MXC_CCM_CGR2_SSI1_MASK (0x3 << 12) |
||||
#define MXC_CCM_CGR2_SSI2_OFFSET 14 |
||||
#define MXC_CCM_CGR2_SSI2_MASK (0x3 << 14) |
||||
#define MXC_CCM_CGR2_UART1_OFFSET 16 |
||||
#define MXC_CCM_CGR2_UART1_MASK (0x3 << 16) |
||||
#define MXC_CCM_CGR2_UART2_OFFSET 18 |
||||
#define MXC_CCM_CGR2_UART2_MASK (0x3 << 18) |
||||
#define MXC_CCM_CGR2_UART3_OFFSET 20 |
||||
#define MXC_CCM_CGR2_UART3_MASK (0x3 << 20) |
||||
#define MXC_CCM_CGR2_USBOTG_OFFSET 22 |
||||
#define MXC_CCM_CGR2_USBOTG_MASK (0x3 << 22) |
||||
#define MXC_CCM_CGR2_WDOG_OFFSET 24 |
||||
#define MXC_CCM_CGR2_WDOG_MASK (0x3 << 24) |
||||
#define MXC_CCM_CGR2_MAX_OFFSET 26 |
||||
#define MXC_CCM_CGR2_MAX_MASK (0x3 << 26) |
||||
#define MXC_CCM_CGR2_MAX_ENABLE (0x2 << 26) |
||||
#define MXC_CCM_CGR2_AUDMUX_OFFSET 30 |
||||
#define MXC_CCM_CGR2_AUDMUX_MASK (0x3 << 30) |
||||
|
||||
#define MXC_CCM_CGR3_CSI_OFFSET 0 |
||||
#define MXC_CCM_CGR3_CSI_MASK (0x3 << 0) |
||||
#define MXC_CCM_CGR3_IIM_OFFSET 2 |
||||
#define MXC_CCM_CGR3_IIM_MASK (0x3 << 2) |
||||
#define MXC_CCM_CGR3_GPU2D_OFFSET 4 |
||||
#define MXC_CCM_CGR3_GPU2D_MASK (0x3 << 4) |
||||
|
||||
#define MXC_CCM_COSR_CLKOSEL_MASK 0x1F |
||||
#define MXC_CCM_COSR_CLKOSEL_OFFSET 0 |
||||
#define MXC_CCM_COSR_CLKOEN (1 << 5) |
||||
#define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6) |
||||
#define MXC_CCM_COSR_CLKOUT_PREDIV_MASK (0x7 << 10) |
||||
#define MXC_CCM_COSR_CLKOUT_PREDIV_OFFSET 10 |
||||
#define MXC_CCM_COSR_CLKOUT_PRODIV_MASK (0x7 << 13) |
||||
#define MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET 13 |
||||
#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16) |
||||
#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16 |
||||
#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18) |
||||
#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_OFFSET 18 |
||||
#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_MASK (0x3 << 20) |
||||
#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_OFFSET 20 |
||||
#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_MASK (0x3 << 22) |
||||
#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_OFFSET 22 |
||||
#define MXC_CCM_COSR_ASRC_AUDIO_EN (1 << 24) |
||||
#define MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK (0x3F << 26) |
||||
#define MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET 26 |
||||
|
||||
#endif |
@ -0,0 +1,303 @@ |
||||
/*
|
||||
* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> |
||||
* |
||||
* (C) Copyright 2008-2009 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARCH_MX35_H |
||||
#define __ASM_ARCH_MX35_H |
||||
|
||||
/*
|
||||
* IRAM |
||||
*/ |
||||
#define IRAM_BASE_ADDR 0x10000000 /* internal ram */ |
||||
#define IRAM_SIZE 0x00020000 /* 128 KB */ |
||||
|
||||
/*
|
||||
* AIPS 1 |
||||
*/ |
||||
#define AIPS1_BASE_ADDR 0x43F00000 |
||||
#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR |
||||
#define MAX_BASE_ADDR 0x43F04000 |
||||
#define EVTMON_BASE_ADDR 0x43F08000 |
||||
#define CLKCTL_BASE_ADDR 0x43F0C000 |
||||
#define I2C_BASE_ADDR 0x43F80000 |
||||
#define I2C3_BASE_ADDR 0x43F84000 |
||||
#define ATA_BASE_ADDR 0x43F8C000 |
||||
#define UART1_BASE_ADDR 0x43F90000 |
||||
#define UART2_BASE_ADDR 0x43F94000 |
||||
#define I2C2_BASE_ADDR 0x43F98000 |
||||
#define CSPI1_BASE_ADDR 0x43FA4000 |
||||
#define IOMUXC_BASE_ADDR 0x43FAC000 |
||||
|
||||
/*
|
||||
* SPBA |
||||
*/ |
||||
#define SPBA_BASE_ADDR 0x50000000 |
||||
#define UART3_BASE_ADDR 0x5000C000 |
||||
#define CSPI2_BASE_ADDR 0x50010000 |
||||
#define ATA_DMA_BASE_ADDR 0x50020000 |
||||
#define FEC_BASE_ADDR 0x50038000 |
||||
#define SPBA_CTRL_BASE_ADDR 0x5003C000 |
||||
|
||||
/*
|
||||
* AIPS 2 |
||||
*/ |
||||
#define AIPS2_BASE_ADDR 0x53F00000 |
||||
#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR |
||||
#define CCM_BASE_ADDR 0x53F80000 |
||||
#define GPT1_BASE_ADDR 0x53F90000 |
||||
#define EPIT1_BASE_ADDR 0x53F94000 |
||||
#define EPIT2_BASE_ADDR 0x53F98000 |
||||
#define GPIO3_BASE_ADDR 0x53FA4000 |
||||
#define MMC_SDHC1_BASE_ADDR 0x53FB4000 |
||||
#define MMC_SDHC2_BASE_ADDR 0x53FB8000 |
||||
#define MMC_SDHC3_BASE_ADDR 0x53FBC000 |
||||
#define IPU_CTRL_BASE_ADDR 0x53FC0000 |
||||
#define GPIO3_BASE_ADDR 0x53FA4000 |
||||
#define GPIO1_BASE_ADDR 0x53FCC000 |
||||
#define GPIO2_BASE_ADDR 0x53FD0000 |
||||
#define SDMA_BASE_ADDR 0x53FD4000 |
||||
#define RTC_BASE_ADDR 0x53FD8000 |
||||
#define WDOG_BASE_ADDR 0x53FDC000 |
||||
#define PWM_BASE_ADDR 0x53FE0000 |
||||
#define RTIC_BASE_ADDR 0x53FEC000 |
||||
#define IIM_BASE_ADDR 0x53FF0000 |
||||
|
||||
#define IMX_CCM_BASE CCM_BASE_ADDR |
||||
|
||||
/*
|
||||
* ROMPATCH and AVIC |
||||
*/ |
||||
#define ROMPATCH_BASE_ADDR 0x60000000 |
||||
#define AVIC_BASE_ADDR 0x68000000 |
||||
|
||||
/*
|
||||
* NAND, SDRAM, WEIM, M3IF, EMI controllers |
||||
*/ |
||||
#define EXT_MEM_CTRL_BASE 0xB8000000 |
||||
#define ESDCTL_BASE_ADDR 0xB8001000 |
||||
#define WEIM_BASE_ADDR 0xB8002000 |
||||
#define WEIM_CTRL_CS0 WEIM_BASE_ADDR |
||||
#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10) |
||||
#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20) |
||||
#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30) |
||||
#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40) |
||||
#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50) |
||||
#define M3IF_BASE_ADDR 0xB8003000 |
||||
#define EMI_BASE_ADDR 0xB8004000 |
||||
|
||||
#define NFC_BASE_ADDR 0xBB000000 |
||||
|
||||
/*
|
||||
* Memory regions and CS |
||||
*/ |
||||
#define IPU_MEM_BASE_ADDR 0x70000000 |
||||
#define CSD0_BASE_ADDR 0x80000000 |
||||
#define CSD1_BASE_ADDR 0x90000000 |
||||
#define CS0_BASE_ADDR 0xA0000000 |
||||
#define CS1_BASE_ADDR 0xA8000000 |
||||
#define CS2_BASE_ADDR 0xB0000000 |
||||
#define CS3_BASE_ADDR 0xB2000000 |
||||
#define CS4_BASE_ADDR 0xB4000000 |
||||
#define CS5_BASE_ADDR 0xB6000000 |
||||
|
||||
/*
|
||||
* IRQ Controller Register Definitions. |
||||
*/ |
||||
#define AVIC_NIMASK 0x04 |
||||
#define AVIC_INTTYPEH 0x18 |
||||
#define AVIC_INTTYPEL 0x1C |
||||
|
||||
/* L210 */ |
||||
#define L2CC_BASE_ADDR 0x30000000 |
||||
#define L2_CACHE_LINE_SIZE 32 |
||||
#define L2_CACHE_CTL_REG 0x100 |
||||
#define L2_CACHE_AUX_CTL_REG 0x104 |
||||
#define L2_CACHE_SYNC_REG 0x730 |
||||
#define L2_CACHE_INV_LINE_REG 0x770 |
||||
#define L2_CACHE_INV_WAY_REG 0x77C |
||||
#define L2_CACHE_CLEAN_LINE_REG 0x7B0 |
||||
#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0 |
||||
#define L2_CACHE_DBG_CTL_REG 0xF40 |
||||
|
||||
#define CLKMODE_AUTO 0 |
||||
#define CLKMODE_CONSUMER 1 |
||||
|
||||
#define PLL_PD(x) (((x) & 0xf) << 26) |
||||
#define PLL_MFD(x) (((x) & 0x3ff) << 16) |
||||
#define PLL_MFI(x) (((x) & 0xf) << 10) |
||||
#define PLL_MFN(x) (((x) & 0x3ff) << 0) |
||||
|
||||
#define CSCR_U(x) (WEIM_CTRL_CS#x + 0) |
||||
#define CSCR_L(x) (WEIM_CTRL_CS#x + 4) |
||||
#define CSCR_A(x) (WEIM_CTRL_CS#x + 8) |
||||
|
||||
#define IIM_SREV 0x24 |
||||
#define ROMPATCH_REV 0x40 |
||||
|
||||
#define IPU_CONF IPU_CTRL_BASE_ADDR |
||||
|
||||
#define IPU_CONF_PXL_ENDIAN (1<<8) |
||||
#define IPU_CONF_DU_EN (1<<7) |
||||
#define IPU_CONF_DI_EN (1<<6) |
||||
#define IPU_CONF_ADC_EN (1<<5) |
||||
#define IPU_CONF_SDC_EN (1<<4) |
||||
#define IPU_CONF_PF_EN (1<<3) |
||||
#define IPU_CONF_ROT_EN (1<<2) |
||||
#define IPU_CONF_IC_EN (1<<1) |
||||
#define IPU_CONF_SCI_EN (1<<0) |
||||
|
||||
#define GPIO_PORT_NUM 3 |
||||
#define GPIO_NUM_PIN 32 |
||||
|
||||
#define CHIP_REV_1_0 0x10 |
||||
#define CHIP_REV_2_0 0x20 |
||||
|
||||
#define BOARD_REV_1_0 0x0 |
||||
#define BOARD_REV_2_0 0x1 |
||||
|
||||
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) |
||||
#include <asm/types.h> |
||||
|
||||
extern void imx_get_mac_from_fuse(unsigned char *mac); |
||||
|
||||
enum mxc_main_clocks { |
||||
CPU_CLK, |
||||
AHB_CLK, |
||||
IPG_CLK, |
||||
IPG_PER_CLK, |
||||
NFC_CLK, |
||||
USB_CLK, |
||||
HSP_CLK, |
||||
}; |
||||
|
||||
enum mxc_peri_clocks { |
||||
UART1_BAUD, |
||||
UART2_BAUD, |
||||
UART3_BAUD, |
||||
SSI1_BAUD, |
||||
SSI2_BAUD, |
||||
CSI_BAUD, |
||||
MSHC_CLK, |
||||
ESDHC1_CLK, |
||||
ESDHC2_CLK, |
||||
ESDHC3_CLK, |
||||
SPDIF_CLK, |
||||
SPI1_CLK, |
||||
SPI2_CLK, |
||||
}; |
||||
|
||||
/* Clock Control Module (CCM) registers */ |
||||
struct ccm_regs { |
||||
u32 ccmr; /* Control */ |
||||
u32 pdr0; /* Post divider 0 */ |
||||
u32 pdr1; /* Post divider 1 */ |
||||
u32 pdr2; /* Post divider 2 */ |
||||
u32 pdr3; /* Post divider 3 */ |
||||
u32 pdr4; /* Post divider 4 */ |
||||
u32 rcsr; /* CCM Status */ |
||||
u32 mpctl; /* Core PLL Control */ |
||||
u32 ppctl; /* Peripheral PLL Control */ |
||||
u32 acmr; /* Audio clock mux */ |
||||
u32 cosr; /* Clock out source */ |
||||
u32 cgr0; /* Clock Gating Control 0 */ |
||||
u32 cgr1; /* Clock Gating Control 1 */ |
||||
u32 cgr2; /* Clock Gating Control 2 */ |
||||
u32 cgr3; /* Clock Gating Control 3 */ |
||||
u32 reserved; |
||||
u32 dcvr0; /* DPTC Comparator 0 */ |
||||
u32 dcvr1; /* DPTC Comparator 0 */ |
||||
u32 dcvr2; /* DPTC Comparator 0 */ |
||||
u32 dcvr3; /* DPTC Comparator 0 */ |
||||
u32 ltr0; /* Load Tracking 0 */ |
||||
u32 ltr1; /* Load Tracking 1 */ |
||||
u32 ltr2; /* Load Tracking 2 */ |
||||
u32 ltr3; /* Load Tracking 3 */ |
||||
u32 ltbr0; /* Load Tracking Buffer 0 */ |
||||
}; |
||||
|
||||
/* IIM control registers */ |
||||
struct iim_regs { |
||||
u32 iim_stat; |
||||
u32 iim_statm; |
||||
u32 iim_err; |
||||
u32 iim_emask; |
||||
u32 iim_fctl; |
||||
u32 iim_ua; |
||||
u32 iim_la; |
||||
u32 iim_sdat; |
||||
u32 iim_prev; |
||||
u32 iim_srev; |
||||
u32 iim_prog_p; |
||||
u32 iim_scs0; |
||||
u32 iim_scs1; |
||||
u32 iim_scs2; |
||||
u32 iim_scs3; |
||||
}; |
||||
|
||||
/* General Purpose Timer (GPT) registers */ |
||||
struct gpt_regs { |
||||
u32 ctrl; /* control */ |
||||
u32 pre; /* prescaler */ |
||||
u32 stat; /* status */ |
||||
u32 intr; /* interrupt */ |
||||
u32 cmp[3]; /* output compare 1-3 */ |
||||
u32 capt[2]; /* input capture 1-2 */ |
||||
u32 counter; /* counter */ |
||||
}; |
||||
|
||||
/* CSPI registers */ |
||||
struct cspi_regs { |
||||
u32 rxdata; |
||||
u32 txdata; |
||||
u32 ctrl; |
||||
u32 intr; |
||||
u32 dma; |
||||
u32 stat; |
||||
u32 period; |
||||
u32 test; |
||||
}; |
||||
|
||||
/* Watchdog Timer (WDOG) registers */ |
||||
struct wdog_regs { |
||||
u16 wcr; /* Control */ |
||||
u16 wsr; /* Service */ |
||||
u16 wrsr; /* Reset Status */ |
||||
u16 wicr; /* Interrupt Control */ |
||||
u16 wmcr; /* Misc Control */ |
||||
}; |
||||
|
||||
/*
|
||||
* NFMS bit in RCSR register for pagesize of nandflash |
||||
*/ |
||||
#define NFMS_BIT 8 |
||||
#define NFMS_NF_DWIDTH 14 |
||||
#define NFMS_NF_PG_SZ 8 |
||||
|
||||
#define CCM_RCSR_NF_16BIT_SEL (1 << 14) |
||||
|
||||
extern unsigned int get_board_rev(void); |
||||
extern int is_soc_rev(int rev); |
||||
extern int sdhc_init(void); |
||||
|
||||
#endif |
||||
#endif /* __ASM_ARCH_MX35_H */ |
@ -0,0 +1,295 @@ |
||||
/*
|
||||
* (C) Copyright 2011 |
||||
* Stefano Babic, DENX Software Engineering, sbabic@denx.de. |
||||
* |
||||
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __MACH_MX35_IOMUX_H__ |
||||
#define __MACH_MX35_IOMUX_H__ |
||||
|
||||
#include <asm/arch/imx-regs.h> |
||||
|
||||
/*
|
||||
* various IOMUX functions |
||||
*/ |
||||
typedef enum iomux_pin_config { |
||||
MUX_CONFIG_FUNC = 0, /* used as function */ |
||||
MUX_CONFIG_ALT1, /* used as alternate function 1 */ |
||||
MUX_CONFIG_ALT2, /* used as alternate function 2 */ |
||||
MUX_CONFIG_ALT3, /* used as alternate function 3 */ |
||||
MUX_CONFIG_ALT4, /* used as alternate function 4 */ |
||||
MUX_CONFIG_ALT5, /* used as alternate function 5 */ |
||||
MUX_CONFIG_ALT6, /* used as alternate function 6 */ |
||||
MUX_CONFIG_ALT7, /* used as alternate function 7 */ |
||||
MUX_CONFIG_SION = 0x1 << 4, /* used as LOOPBACK:MUX SION bit */ |
||||
MUX_CONFIG_GPIO = MUX_CONFIG_ALT5, /* used as GPIO */ |
||||
} iomux_pin_cfg_t; |
||||
|
||||
/*
|
||||
* various IOMUX pad functions |
||||
*/ |
||||
typedef enum iomux_pad_config { |
||||
PAD_CTL_DRV_3_3V = 0x0 << 13, |
||||
PAD_CTL_DRV_1_8V = 0x1 << 13, |
||||
PAD_CTL_HYS_CMOS = 0x0 << 8, |
||||
PAD_CTL_HYS_SCHMITZ = 0x1 << 8, |
||||
PAD_CTL_PKE_NONE = 0x0 << 7, |
||||
PAD_CTL_PKE_ENABLE = 0x1 << 7, |
||||
PAD_CTL_PUE_KEEPER = 0x0 << 6, |
||||
PAD_CTL_PUE_PUD = 0x1 << 6, |
||||
PAD_CTL_100K_PD = 0x0 << 4, |
||||
PAD_CTL_47K_PU = 0x1 << 4, |
||||
PAD_CTL_100K_PU = 0x2 << 4, |
||||
PAD_CTL_22K_PU = 0x3 << 4, |
||||
PAD_CTL_ODE_CMOS = 0x0 << 3, |
||||
PAD_CTL_ODE_OpenDrain = 0x1 << 3, |
||||
PAD_CTL_DRV_NORMAL = 0x0 << 1, |
||||
PAD_CTL_DRV_HIGH = 0x1 << 1, |
||||
PAD_CTL_DRV_MAX = 0x2 << 1, |
||||
PAD_CTL_SRE_SLOW = 0x0 << 0, |
||||
PAD_CTL_SRE_FAST = 0x1 << 0 |
||||
} iomux_pad_config_t; |
||||
|
||||
/*
|
||||
* various IOMUX general purpose functions |
||||
*/ |
||||
typedef enum iomux_gp_func { |
||||
MUX_SDCTL_CSD0_SEL = 0x1 << 0, |
||||
MUX_SDCTL_CSD1_SEL = 0x1 << 1, |
||||
MUX_TAMPER_DETECT_EN = 0x1 << 2, |
||||
} iomux_gp_func_t; |
||||
|
||||
/*
|
||||
* various IOMUX input select register index |
||||
*/ |
||||
typedef enum iomux_input_select { |
||||
MUX_IN_AMX_P5_RXCLK = 0, |
||||
MUX_IN_AMX_P5_RXFS, |
||||
MUX_IN_AMX_P6_DA, |
||||
MUX_IN_AMX_P6_DB, |
||||
MUX_IN_AMX_P6_RXCLK, |
||||
MUX_IN_AMX_P6_RXFS, |
||||
MUX_IN_AMX_P6_TXCLK, |
||||
MUX_IN_AMX_P6_TXFS, |
||||
MUX_IN_CAN1_CANRX, |
||||
MUX_IN_CAN2_CANRX, |
||||
MUX_IN_CCM_32K_MUXED, |
||||
MUX_IN_CCM_PMIC_RDY, |
||||
MUX_IN_CSPI1_SS2_B, |
||||
MUX_IN_CSPI1_SS3_B, |
||||
MUX_IN_CSPI2_CLK_IN, |
||||
MUX_IN_CSPI2_DATAREADY_B, |
||||
MUX_IN_CSPI2_MISO, |
||||
MUX_IN_CSPI2_MOSI, |
||||
MUX_IN_CSPI2_SS0_B, |
||||
MUX_IN_CSPI2_SS1_B, |
||||
MUX_IN_CSPI2_SS2_B, |
||||
MUX_IN_CSPI2_SS3_B, |
||||
MUX_IN_EMI_WEIM_DTACK_B, |
||||
MUX_IN_ESDHC1_DAT4_IN, |
||||
MUX_IN_ESDHC1_DAT5_IN, |
||||
MUX_IN_ESDHC1_DAT6_IN, |
||||
MUX_IN_ESDHC1_DAT7_IN, |
||||
MUX_IN_ESDHC3_CARD_CLK_IN, |
||||
MUX_IN_ESDHC3_CMD_IN, |
||||
MUX_IN_ESDHC3_DAT0, |
||||
MUX_IN_ESDHC3_DAT1, |
||||
MUX_IN_ESDHC3_DAT2, |
||||
MUX_IN_ESDHC3_DAT3, |
||||
MUX_IN_GPIO1_IN_0, |
||||
MUX_IN_GPIO1_IN_10, |
||||
MUX_IN_GPIO1_IN_11, |
||||
MUX_IN_GPIO1_IN_1, |
||||
MUX_IN_GPIO1_IN_20, |
||||
MUX_IN_GPIO1_IN_21, |
||||
MUX_IN_GPIO1_IN_22, |
||||
MUX_IN_GPIO1_IN_2, |
||||
MUX_IN_GPIO1_IN_3, |
||||
MUX_IN_GPIO1_IN_4, |
||||
MUX_IN_GPIO1_IN_5, |
||||
MUX_IN_GPIO1_IN_6, |
||||
MUX_IN_GPIO1_IN_7, |
||||
MUX_IN_GPIO1_IN_8, |
||||
MUX_IN_GPIO1_IN_9, |
||||
MUX_IN_GPIO2_IN_0, |
||||
MUX_IN_GPIO2_IN_10, |
||||
MUX_IN_GPIO2_IN_11, |
||||
MUX_IN_GPIO2_IN_12, |
||||
MUX_IN_GPIO2_IN_13, |
||||
MUX_IN_GPIO2_IN_14, |
||||
MUX_IN_GPIO2_IN_15, |
||||
MUX_IN_GPIO2_IN_16, |
||||
MUX_IN_GPIO2_IN_17, |
||||
MUX_IN_GPIO2_IN_18, |
||||
MUX_IN_GPIO2_IN_19, |
||||
MUX_IN_GPIO2_IN_20, |
||||
MUX_IN_GPIO2_IN_21, |
||||
MUX_IN_GPIO2_IN_22, |
||||
MUX_IN_GPIO2_IN_23, |
||||
MUX_IN_GPIO2_IN_24, |
||||
MUX_IN_GPIO2_IN_25, |
||||
MUX_IN_GPIO2_IN_26, |
||||
MUX_IN_GPIO2_IN_27, |
||||
MUX_IN_GPIO2_IN_28, |
||||
MUX_IN_GPIO2_IN_29, |
||||
MUX_IN_GPIO2_IN_2, |
||||
MUX_IN_GPIO2_IN_30, |
||||
MUX_IN_GPIO2_IN_31, |
||||
MUX_IN_GPIO2_IN_3, |
||||
MUX_IN_GPIO2_IN_4, |
||||
MUX_IN_GPIO2_IN_5, |
||||
MUX_IN_GPIO2_IN_6, |
||||
MUX_IN_GPIO2_IN_7, |
||||
MUX_IN_GPIO2_IN_8, |
||||
MUX_IN_GPIO2_IN_9, |
||||
MUX_IN_GPIO3_IN_0, |
||||
MUX_IN_GPIO3_IN_10, |
||||
MUX_IN_GPIO3_IN_11, |
||||
MUX_IN_GPIO3_IN_12, |
||||
MUX_IN_GPIO3_IN_13, |
||||
MUX_IN_GPIO3_IN_14, |
||||
MUX_IN_GPIO3_IN_15, |
||||
MUX_IN_GPIO3_IN_4, |
||||
MUX_IN_GPIO3_IN_5, |
||||
MUX_IN_GPIO3_IN_6, |
||||
MUX_IN_GPIO3_IN_7, |
||||
MUX_IN_GPIO3_IN_8, |
||||
MUX_IN_GPIO3_IN_9, |
||||
MUX_IN_I2C3_SCL_IN, |
||||
MUX_IN_I2C3_SDA_IN, |
||||
MUX_IN_IPU_DISPB_D0_VSYNC, |
||||
MUX_IN_IPU_DISPB_D12_VSYNC, |
||||
MUX_IN_IPU_DISPB_SD_D, |
||||
MUX_IN_IPU_SENSB_DATA_0, |
||||
MUX_IN_IPU_SENSB_DATA_1, |
||||
MUX_IN_IPU_SENSB_DATA_2, |
||||
MUX_IN_IPU_SENSB_DATA_3, |
||||
MUX_IN_IPU_SENSB_DATA_4, |
||||
MUX_IN_IPU_SENSB_DATA_5, |
||||
MUX_IN_IPU_SENSB_DATA_6, |
||||
MUX_IN_IPU_SENSB_DATA_7, |
||||
MUX_IN_KPP_COL_0, |
||||
MUX_IN_KPP_COL_1, |
||||
MUX_IN_KPP_COL_2, |
||||
MUX_IN_KPP_COL_3, |
||||
MUX_IN_KPP_COL_4, |
||||
MUX_IN_KPP_COL_5, |
||||
MUX_IN_KPP_COL_6, |
||||
MUX_IN_KPP_COL_7, |
||||
MUX_IN_KPP_ROW_0, |
||||
MUX_IN_KPP_ROW_1, |
||||
MUX_IN_KPP_ROW_2, |
||||
MUX_IN_KPP_ROW_3, |
||||
MUX_IN_KPP_ROW_4, |
||||
MUX_IN_KPP_ROW_5, |
||||
MUX_IN_KPP_ROW_6, |
||||
MUX_IN_KPP_ROW_7, |
||||
MUX_IN_OWIRE_BATTERY_LINE, |
||||
MUX_IN_SPDIF_HCKT_CLK2, |
||||
MUX_IN_SPDIF_SPDIF_IN1, |
||||
MUX_IN_UART3_UART_RTS_B, |
||||
MUX_IN_UART3_UART_RXD_MUX, |
||||
MUX_IN_USB_OTG_DATA_0, |
||||
MUX_IN_USB_OTG_DATA_1, |
||||
MUX_IN_USB_OTG_DATA_2, |
||||
MUX_IN_USB_OTG_DATA_3, |
||||
MUX_IN_USB_OTG_DATA_4, |
||||
MUX_IN_USB_OTG_DATA_5, |
||||
MUX_IN_USB_OTG_DATA_6, |
||||
MUX_IN_USB_OTG_DATA_7, |
||||
MUX_IN_USB_OTG_DIR, |
||||
MUX_IN_USB_OTG_NXT, |
||||
MUX_IN_USB_UH2_DATA_0, |
||||
MUX_IN_USB_UH2_DATA_1, |
||||
MUX_IN_USB_UH2_DATA_2, |
||||
MUX_IN_USB_UH2_DATA_3, |
||||
MUX_IN_USB_UH2_DATA_4, |
||||
MUX_IN_USB_UH2_DATA_5, |
||||
MUX_IN_USB_UH2_DATA_6, |
||||
MUX_IN_USB_UH2_DATA_7, |
||||
MUX_IN_USB_UH2_DIR, |
||||
MUX_IN_USB_UH2_NXT, |
||||
MUX_IN_USB_UH2_USB_OC, |
||||
} iomux_input_select_t; |
||||
|
||||
/*
|
||||
* various IOMUX input functions |
||||
*/ |
||||
typedef enum iomux_input_config { |
||||
INPUT_CTL_PATH0 = 0x0, |
||||
INPUT_CTL_PATH1, |
||||
INPUT_CTL_PATH2, |
||||
INPUT_CTL_PATH3, |
||||
INPUT_CTL_PATH4, |
||||
INPUT_CTL_PATH5, |
||||
INPUT_CTL_PATH6, |
||||
INPUT_CTL_PATH7, |
||||
} iomux_input_cfg_t; |
||||
|
||||
/*
|
||||
* Request ownership for an IO pin. This function has to be the first one |
||||
* being called before that pin is used. The caller has to check the |
||||
* return value to make sure it returns 0. |
||||
* |
||||
* @param pin a name defined by iomux_pin_name_t |
||||
* @param cfg an input function as defined in iomux_pin_cfg_t |
||||
* |
||||
* @return 0 if successful; Non-zero otherwise |
||||
*/ |
||||
void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg); |
||||
|
||||
/*
|
||||
* Release ownership for an IO pin |
||||
* |
||||
* @param pin a name defined by iomux_pin_name_t |
||||
* @param cfg an input function as defined in iomux_pin_cfg_t |
||||
*/ |
||||
void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg); |
||||
|
||||
/*
|
||||
* This function enables/disables the general purpose function for a particular |
||||
* signal. |
||||
* |
||||
* @param gp one signal as defined in iomux_gp_func_t |
||||
* @param en 1 to enable; 0 to disable |
||||
*/ |
||||
void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en); |
||||
|
||||
/*
|
||||
* This function configures the pad value for a IOMUX pin. |
||||
* |
||||
* @param pin a pin number as defined in iomux_pin_name_t |
||||
* @param config the ORed value of elements defined in |
||||
* iomux_pad_config_t |
||||
*/ |
||||
void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config); |
||||
|
||||
/*
|
||||
* This function configures input path. |
||||
* |
||||
* @param input index of input select register as defined in |
||||
* iomux_input_select_t |
||||
* @param config the binary value of elements defined in |
||||
* iomux_input_cfg_t |
||||
*/ |
||||
void mxc_iomux_set_input(iomux_input_select_t input, u32 config); |
||||
#endif |
@ -0,0 +1,355 @@ |
||||
/*
|
||||
* (C) Copyright 2011 |
||||
* Stefano Babic, DENX Software Engineering, sbabic@denx.de. |
||||
* |
||||
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARCH_MXC_MX35_PINS_H__ |
||||
#define __ASM_ARCH_MXC_MX35_PINS_H__ |
||||
|
||||
/*!
|
||||
* @file arch-mxc/mx35_pins.h |
||||
* |
||||
* @brief MX35 I/O Pin List |
||||
* |
||||
* @ingroup GPIO_MX35 |
||||
*/ |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
|
||||
/*!
|
||||
* @name IOMUX/PAD Bit field definitions |
||||
*/ |
||||
|
||||
/*! @{ */ |
||||
|
||||
/*!
|
||||
* In order to identify pins more effectively, each mux-controlled pin's |
||||
* enumerated value is constructed in the following way: |
||||
* |
||||
* ------------------------------------------------------------------- |
||||
* 31-29 | 28 - 24 |23 - 21| 20 - 10| 9 - 0 |
||||
* ------------------------------------------------------------------- |
||||
* IO_P | IO_I | RSVD | PAD_I | MUX_I |
||||
* ------------------------------------------------------------------- |
||||
* |
||||
* Bit 0 to 7 contains MUX_I used to identify the register |
||||
* offset (base is IOMUX_module_base ) defined in the Section |
||||
* "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The similar field |
||||
* definitions are used for the pad control register.the MX35_PIN_A0 is |
||||
* defined in the enumeration: ( 0x28 << MUX_I) |( 0x368 << PAD_I) |
||||
* So the absolute address is: IOMUX_module_base + 0x28. |
||||
* The pad control register offset is: 0x368. |
||||
*/ |
||||
|
||||
/*!
|
||||
* Starting bit position within each entry of \b iomux_pins to represent the |
||||
* MUX control register offset |
||||
*/ |
||||
#define MUX_I 0 |
||||
/*!
|
||||
* Starting bit position within each entry of \b iomux_pins to represent the |
||||
* PAD control register offset |
||||
*/ |
||||
#define PAD_I 10 |
||||
|
||||
/*!
|
||||
* Starting bit position within each entry of \b iomux_pins to represent the |
||||
* reserved filed |
||||
*/ |
||||
#define RSVD_I 21 |
||||
|
||||
#define MUX_IO_P 29 |
||||
#define MUX_IO_I 24 |
||||
#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \ |
||||
GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
|
||||
((1 << (MUX_IO_P - MUX_IO_I)) - 1))) |
||||
#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin)) |
||||
#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN) |
||||
#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN) |
||||
|
||||
#define NON_GPIO_I 0x7 |
||||
#define PIN_TO_MUX_MASK ((1<<(PAD_I - MUX_I)) - 1) |
||||
#define PIN_TO_PAD_MASK ((1<<(RSVD_I - PAD_I)) - 1) |
||||
#define NON_MUX_I PIN_TO_MUX_MASK |
||||
|
||||
#define _MXC_BUILD_PIN(gp, gi, mi, pi) \ |
||||
(((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
|
||||
((mi) << MUX_I) | ((pi) << PAD_I)) |
||||
|
||||
#define _MXC_BUILD_GPIO_PIN(gp, gi, mi, pi) \ |
||||
_MXC_BUILD_PIN(gp, gi, mi, pi) |
||||
|
||||
#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \ |
||||
_MXC_BUILD_PIN(NON_GPIO_I, 0, mi, pi) |
||||
|
||||
#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK) |
||||
#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK) |
||||
|
||||
/*! @} End IOMUX/PAD Bit field definitions */ |
||||
|
||||
/*!
|
||||
* This enumeration is constructed based on the Section |
||||
* "sw_pad_ctl & sw_mux_ctl details" of the MX35 IC Spec. Each enumerated |
||||
* value is constructed based on the rules described above. |
||||
*/ |
||||
typedef enum iomux_pins { |
||||
MX35_PIN_CAPTURE = _MXC_BUILD_GPIO_PIN(0, 4, 0x4, 0x328), |
||||
MX35_PIN_COMPARE = _MXC_BUILD_GPIO_PIN(0, 5, 0x8, 0x32C), |
||||
MX35_PIN_WATCHDOG_RST = _MXC_BUILD_GPIO_PIN(0, 6, 0xC, 0x330), |
||||
MX35_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 0x10, 0x334), |
||||
MX35_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 0x14, 0x338), |
||||
MX35_PIN_GPIO2_0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x18, 0x33C), |
||||
MX35_PIN_GPIO3_0 = _MXC_BUILD_GPIO_PIN(2, 1, 0x1C, 0x340), |
||||
MX35_PIN_CLKO = _MXC_BUILD_GPIO_PIN(0, 8, 0x20, 0x34C), |
||||
|
||||
MX35_PIN_POWER_FAIL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x360), |
||||
MX35_PIN_VSTBY = _MXC_BUILD_GPIO_PIN(0, 7, 0x24, 0x364), |
||||
MX35_PIN_A0 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x368), |
||||
MX35_PIN_A1 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x36C), |
||||
MX35_PIN_A2 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x370), |
||||
MX35_PIN_A3 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x374), |
||||
MX35_PIN_A4 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x378), |
||||
MX35_PIN_A5 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x37C), |
||||
MX35_PIN_A6 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x380), |
||||
MX35_PIN_A7 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x384), |
||||
MX35_PIN_A8 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x388), |
||||
MX35_PIN_A9 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x38C), |
||||
MX35_PIN_A10 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x390), |
||||
MX35_PIN_MA10 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x394), |
||||
MX35_PIN_A11 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x398), |
||||
MX35_PIN_A12 = _MXC_BUILD_NON_GPIO_PIN(0x5C, 0x39C), |
||||
MX35_PIN_A13 = _MXC_BUILD_NON_GPIO_PIN(0x60, 0x3A0), |
||||
MX35_PIN_A14 = _MXC_BUILD_NON_GPIO_PIN(0x64, 0x3A4), |
||||
MX35_PIN_A15 = _MXC_BUILD_NON_GPIO_PIN(0x68, 0x3A8), |
||||
MX35_PIN_A16 = _MXC_BUILD_NON_GPIO_PIN(0x6C, 0x3AC), |
||||
MX35_PIN_A17 = _MXC_BUILD_NON_GPIO_PIN(0x70, 0x3B0), |
||||
MX35_PIN_A18 = _MXC_BUILD_NON_GPIO_PIN(0x74, 0x3B4), |
||||
MX35_PIN_A19 = _MXC_BUILD_NON_GPIO_PIN(0x78, 0x3B8), |
||||
MX35_PIN_A20 = _MXC_BUILD_NON_GPIO_PIN(0x7C, 0x3BC), |
||||
MX35_PIN_A21 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x3C0), |
||||
MX35_PIN_A22 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x3C4), |
||||
MX35_PIN_A23 = _MXC_BUILD_NON_GPIO_PIN(0x88, 0x3C8), |
||||
MX35_PIN_A24 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x3CC), |
||||
MX35_PIN_A25 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x3D0), |
||||
|
||||
MX35_PIN_EB0 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x46C), |
||||
MX35_PIN_EB1 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x470), |
||||
MX35_PIN_OE = _MXC_BUILD_NON_GPIO_PIN(0x9C, 0x474), |
||||
MX35_PIN_CS0 = _MXC_BUILD_NON_GPIO_PIN(0xA0, 0x478), |
||||
MX35_PIN_CS1 = _MXC_BUILD_NON_GPIO_PIN(0xA4, 0x47C), |
||||
MX35_PIN_CS2 = _MXC_BUILD_NON_GPIO_PIN(0xA8, 0x480), |
||||
MX35_PIN_CS3 = _MXC_BUILD_NON_GPIO_PIN(0xAC, 0x484), |
||||
MX35_PIN_CS4 = _MXC_BUILD_GPIO_PIN(0, 20, 0xB0, 0x488), |
||||
MX35_PIN_CS5 = _MXC_BUILD_GPIO_PIN(0, 21, 0xB4, 0x48C), |
||||
MX35_PIN_NFCE_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xB8, 0x490), |
||||
|
||||
MX35_PIN_LBA = _MXC_BUILD_NON_GPIO_PIN(0xBC, 0x498), |
||||
MX35_PIN_BCLK = _MXC_BUILD_NON_GPIO_PIN(0xC0, 0x49C), |
||||
MX35_PIN_RW = _MXC_BUILD_NON_GPIO_PIN(0xC4, 0x4A0), |
||||
|
||||
MX35_PIN_NFWE_B = _MXC_BUILD_GPIO_PIN(0, 18, 0xC8, 0x4CC), |
||||
MX35_PIN_NFRE_B = _MXC_BUILD_GPIO_PIN(0, 19, 0xCC, 0x4D0), |
||||
MX35_PIN_NFALE = _MXC_BUILD_GPIO_PIN(0, 20, 0xD0, 0x4D4), |
||||
MX35_PIN_NFCLE = _MXC_BUILD_GPIO_PIN(0, 21, 0xD4, 0x4D8), |
||||
MX35_PIN_NFWP_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xD8, 0x4DC), |
||||
MX35_PIN_NFRB = _MXC_BUILD_GPIO_PIN(0, 23, 0xDC, 0x4E0), |
||||
|
||||
MX35_PIN_D15 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E4), |
||||
MX35_PIN_D14 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E8), |
||||
MX35_PIN_D13 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4EC), |
||||
MX35_PIN_D12 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F0), |
||||
MX35_PIN_D11 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F4), |
||||
MX35_PIN_D10 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F8), |
||||
MX35_PIN_D9 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4FC), |
||||
MX35_PIN_D8 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x500), |
||||
MX35_PIN_D7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x504), |
||||
MX35_PIN_D6 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x508), |
||||
MX35_PIN_D5 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x50C), |
||||
MX35_PIN_D4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x510), |
||||
MX35_PIN_D3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x514), |
||||
MX35_PIN_D2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x518), |
||||
MX35_PIN_D1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x51C), |
||||
MX35_PIN_D0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x520), |
||||
|
||||
MX35_PIN_CSI_D8 = _MXC_BUILD_GPIO_PIN(0, 20, 0xE0, 0x524), |
||||
MX35_PIN_CSI_D9 = _MXC_BUILD_GPIO_PIN(0, 21, 0xE4, 0x528), |
||||
MX35_PIN_CSI_D10 = _MXC_BUILD_GPIO_PIN(0, 22, 0xE8, 0x52C), |
||||
MX35_PIN_CSI_D11 = _MXC_BUILD_GPIO_PIN(0, 23, 0xEC, 0x530), |
||||
MX35_PIN_CSI_D12 = _MXC_BUILD_GPIO_PIN(0, 24, 0xF0, 0x534), |
||||
MX35_PIN_CSI_D13 = _MXC_BUILD_GPIO_PIN(0, 25, 0xF4, 0x538), |
||||
MX35_PIN_CSI_D14 = _MXC_BUILD_GPIO_PIN(0, 26, 0xF8, 0x53C), |
||||
MX35_PIN_CSI_D15 = _MXC_BUILD_GPIO_PIN(0, 27, 0xFC, 0x540), |
||||
MX35_PIN_CSI_MCLK = _MXC_BUILD_GPIO_PIN(0, 28, 0x100, 0x544), |
||||
MX35_PIN_CSI_VSYNC = _MXC_BUILD_GPIO_PIN(0, 29, 0x104, 0x548), |
||||
MX35_PIN_CSI_HSYNC = _MXC_BUILD_GPIO_PIN(0, 30, 0x108, 0x54C), |
||||
MX35_PIN_CSI_PIXCLK = _MXC_BUILD_GPIO_PIN(0, 31, 0x10C, 0x550), |
||||
|
||||
MX35_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(1, 24, 0x110, 0x554), |
||||
MX35_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(1, 25, 0x114, 0x558), |
||||
MX35_PIN_I2C2_CLK = _MXC_BUILD_GPIO_PIN(1, 26, 0x118, 0x55C), |
||||
MX35_PIN_I2C2_DAT = _MXC_BUILD_GPIO_PIN(1, 27, 0x11C, 0x560), |
||||
|
||||
MX35_PIN_STXD4 = _MXC_BUILD_GPIO_PIN(1, 28, 0x120, 0x564), |
||||
MX35_PIN_SRXD4 = _MXC_BUILD_GPIO_PIN(1, 29, 0x124, 0x568), |
||||
MX35_PIN_SCK4 = _MXC_BUILD_GPIO_PIN(1, 30, 0x128, 0x56C), |
||||
MX35_PIN_STXFS4 = _MXC_BUILD_GPIO_PIN(1, 31, 0x12C, 0x570), |
||||
MX35_PIN_STXD5 = _MXC_BUILD_GPIO_PIN(0, 0, 0x130, 0x574), |
||||
MX35_PIN_SRXD5 = _MXC_BUILD_GPIO_PIN(0, 1, 0x134, 0x578), |
||||
MX35_PIN_SCK5 = _MXC_BUILD_GPIO_PIN(0, 2, 0x138, 0x57C), |
||||
MX35_PIN_STXFS5 = _MXC_BUILD_GPIO_PIN(0, 3, 0x13C, 0x580), |
||||
|
||||
MX35_PIN_SCKR = _MXC_BUILD_GPIO_PIN(0, 4, 0x140, 0x584), |
||||
MX35_PIN_FSR = _MXC_BUILD_GPIO_PIN(0, 5, 0x144, 0x588), |
||||
MX35_PIN_HCKR = _MXC_BUILD_GPIO_PIN(0, 6, 0x148, 0x58C), |
||||
MX35_PIN_SCKT = _MXC_BUILD_GPIO_PIN(0, 7, 0x14C, 0x590), |
||||
MX35_PIN_FST = _MXC_BUILD_GPIO_PIN(0, 8, 0x150, 0x594), |
||||
MX35_PIN_HCKT = _MXC_BUILD_GPIO_PIN(0, 9, 0x154, 0x598), |
||||
MX35_PIN_TX5_RX0 = _MXC_BUILD_GPIO_PIN(0, 10, 0x158, 0x59C), |
||||
MX35_PIN_TX4_RX1 = _MXC_BUILD_GPIO_PIN(0, 11, 0x15C, 0x5A0), |
||||
MX35_PIN_TX3_RX2 = _MXC_BUILD_GPIO_PIN(0, 12, 0x160, 0x5A4), |
||||
MX35_PIN_TX2_RX3 = _MXC_BUILD_GPIO_PIN(0, 13, 0x164, 0x5A8), |
||||
MX35_PIN_TX1 = _MXC_BUILD_GPIO_PIN(0, 14, 0x168, 0x5AC), |
||||
MX35_PIN_TX0 = _MXC_BUILD_GPIO_PIN(0, 15, 0x16C, 0x5B0), |
||||
|
||||
MX35_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(0, 16, 0x170, 0x5B4), |
||||
MX35_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(0, 17, 0x174, 0x5B8), |
||||
MX35_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(0, 18, 0x178, 0x5BC), |
||||
MX35_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(0, 19, 0x17C, 0x5C0), |
||||
MX35_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(2, 4, 0x180, 0x5C4), |
||||
MX35_PIN_CSPI1_SPI_RDY = _MXC_BUILD_GPIO_PIN(2, 5, 0x184, 0x5C8), |
||||
|
||||
MX35_PIN_RXD1 = _MXC_BUILD_GPIO_PIN(2, 6, 0x188, 0x5CC), |
||||
MX35_PIN_TXD1 = _MXC_BUILD_GPIO_PIN(2, 7, 0x18C, 0x5D0), |
||||
MX35_PIN_RTS1 = _MXC_BUILD_GPIO_PIN(2, 8, 0x190, 0x5D4), |
||||
MX35_PIN_CTS1 = _MXC_BUILD_GPIO_PIN(2, 9, 0x194, 0x5D8), |
||||
MX35_PIN_RXD2 = _MXC_BUILD_GPIO_PIN(2, 10, 0x198, 0x5DC), |
||||
MX35_PIN_TXD2 = _MXC_BUILD_GPIO_PIN(1, 11, 0x19C, 0x5E0), |
||||
MX35_PIN_RTS2 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1A0, 0x5E4), |
||||
MX35_PIN_CTS2 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1A4, 0x5E8), |
||||
|
||||
MX35_PIN_USBOTG_PWR = _MXC_BUILD_GPIO_PIN(2, 14, 0x1A8, 0x60C), |
||||
MX35_PIN_USBOTG_OC = _MXC_BUILD_GPIO_PIN(2, 15, 0x1AC, 0x610), |
||||
|
||||
MX35_PIN_LD0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x1B0, 0x614), |
||||
MX35_PIN_LD1 = _MXC_BUILD_GPIO_PIN(1, 1, 0x1B4, 0x618), |
||||
MX35_PIN_LD2 = _MXC_BUILD_GPIO_PIN(1, 2, 0x1B8, 0x61C), |
||||
MX35_PIN_LD3 = _MXC_BUILD_GPIO_PIN(1, 3, 0x1BC, 0x620), |
||||
MX35_PIN_LD4 = _MXC_BUILD_GPIO_PIN(1, 4, 0x1C0, 0x624), |
||||
MX35_PIN_LD5 = _MXC_BUILD_GPIO_PIN(1, 5, 0x1C4, 0x628), |
||||
MX35_PIN_LD6 = _MXC_BUILD_GPIO_PIN(1, 6, 0x1C8, 0x62C), |
||||
MX35_PIN_LD7 = _MXC_BUILD_GPIO_PIN(1, 7, 0x1CC, 0x630), |
||||
MX35_PIN_LD8 = _MXC_BUILD_GPIO_PIN(1, 8, 0x1D0, 0x634), |
||||
MX35_PIN_LD9 = _MXC_BUILD_GPIO_PIN(1, 9, 0x1D4, 0x638), |
||||
MX35_PIN_LD10 = _MXC_BUILD_GPIO_PIN(1, 10, 0x1D8, 0x63C), |
||||
MX35_PIN_LD11 = _MXC_BUILD_GPIO_PIN(1, 11, 0x1DC, 0x640), |
||||
MX35_PIN_LD12 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1E0, 0x644), |
||||
MX35_PIN_LD13 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1E4, 0x648), |
||||
MX35_PIN_LD14 = _MXC_BUILD_GPIO_PIN(1, 14, 0x1E8, 0x64C), |
||||
MX35_PIN_LD15 = _MXC_BUILD_GPIO_PIN(1, 15, 0x1EC, 0x650), |
||||
MX35_PIN_LD16 = _MXC_BUILD_GPIO_PIN(1, 16, 0x1F0, 0x654), |
||||
MX35_PIN_LD17 = _MXC_BUILD_GPIO_PIN(1, 17, 0x1F4, 0x658), |
||||
MX35_PIN_LD18 = _MXC_BUILD_GPIO_PIN(2, 24, 0x1F8, 0x65C), |
||||
MX35_PIN_LD19 = _MXC_BUILD_GPIO_PIN(2, 25, 0x1FC, 0x660), |
||||
MX35_PIN_LD20 = _MXC_BUILD_GPIO_PIN(2, 26, 0x200, 0x664), |
||||
MX35_PIN_LD21 = _MXC_BUILD_GPIO_PIN(2, 27, 0x204, 0x668), |
||||
MX35_PIN_LD22 = _MXC_BUILD_GPIO_PIN(2, 28, 0x208, 0x66C), |
||||
MX35_PIN_LD23 = _MXC_BUILD_GPIO_PIN(2, 29, 0x20C, 0x670), |
||||
|
||||
MX35_PIN_D3_HSYNC = _MXC_BUILD_GPIO_PIN(2, 30, 0x210, 0x674), |
||||
MX35_PIN_D3_FPSHIFT = _MXC_BUILD_GPIO_PIN(2, 31, 0x214, 0x678), |
||||
MX35_PIN_D3_DRDY = _MXC_BUILD_GPIO_PIN(0, 0, 0x218, 0x67C), |
||||
MX35_PIN_CONTRAST = _MXC_BUILD_GPIO_PIN(0, 1, 0x21C, 0x680), |
||||
MX35_PIN_D3_VSYNC = _MXC_BUILD_GPIO_PIN(0, 2, 0x220, 0x684), |
||||
MX35_PIN_D3_REV = _MXC_BUILD_GPIO_PIN(0, 3, 0x224, 0x688), |
||||
MX35_PIN_D3_CLS = _MXC_BUILD_GPIO_PIN(0, 4, 0x228, 0x68C), |
||||
MX35_PIN_D3_SPL = _MXC_BUILD_GPIO_PIN(0, 5, 0x22C, 0x690), |
||||
|
||||
MX35_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 6, 0x230, 0x694), |
||||
MX35_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 7, 0x234, 0x698), |
||||
MX35_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 8, 0x238, 0x69C), |
||||
MX35_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 9, 0x23C, 0x6A0), |
||||
MX35_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 10, 0x240, 0x6A4), |
||||
MX35_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 11, 0x244, 0x6A8), |
||||
MX35_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(1, 0, 0x248, 0x6AC), |
||||
MX35_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(1, 1, 0x24C, 0x6B0), |
||||
MX35_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(1, 2, 0x250, 0x6B4), |
||||
MX35_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(1, 3, 0x254, 0x6B8), |
||||
MX35_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(1, 4, 0x258, 0x6BC), |
||||
MX35_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(1, 5, 0x25C, 0x6C0), |
||||
|
||||
MX35_PIN_ATA_CS0 = _MXC_BUILD_GPIO_PIN(1, 6, 0x260, 0x6C4), |
||||
MX35_PIN_ATA_CS1 = _MXC_BUILD_GPIO_PIN(1, 7, 0x264, 0x6C8), |
||||
MX35_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(1, 8, 0x268, 0x6CC), |
||||
MX35_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(1, 9, 0x26C, 0x6D0), |
||||
MX35_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(1, 10, 0x270, 0x6D4), |
||||
MX35_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(1, 11, 0x274, 0x6D8), |
||||
MX35_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(1, 12, 0x278, 0x6DC), |
||||
MX35_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 13, 0x27C, 0x6E0), |
||||
MX35_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 14, 0x280, 0x6E4), |
||||
MX35_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 15, 0x284, 0x6E8), |
||||
MX35_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 16, 0x288, 0x6EC), |
||||
MX35_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 17, 0x28C, 0x6F0), |
||||
MX35_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 18, 0x290, 0x6F4), |
||||
MX35_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 19, 0x294, 0x6F8), |
||||
MX35_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 20, 0x298, 0x6FC), |
||||
MX35_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 21, 0x29C, 0x700), |
||||
MX35_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 22, 0x2A0, 0x704), |
||||
MX35_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 23, 0x2A4, 0x708), |
||||
MX35_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 24, 0x2A8, 0x70C), |
||||
MX35_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 25, 0x2AC, 0x710), |
||||
MX35_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 26, 0x2B0, 0x714), |
||||
MX35_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 27, 0x2B4, 0x718), |
||||
MX35_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 28, 0x2B8, 0x71C), |
||||
MX35_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(1, 29, 0x2BC, 0x720), |
||||
MX35_PIN_ATA_BUFF_EN = _MXC_BUILD_GPIO_PIN(1, 30, 0x2C0, 0x724), |
||||
MX35_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(1, 31, 0x2C4, 0x728), |
||||
MX35_PIN_ATA_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 0x2C8, 0x72C), |
||||
MX35_PIN_ATA_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 0x2CC, 0x730), |
||||
MX35_PIN_ATA_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 0x2D0, 0x734), |
||||
|
||||
MX35_PIN_MLB_CLK = _MXC_BUILD_GPIO_PIN(2, 3, 0x2D4, 0x738), |
||||
MX35_PIN_MLB_DAT = _MXC_BUILD_GPIO_PIN(2, 4, 0x2D8, 0x73C), |
||||
MX35_PIN_MLB_SIG = _MXC_BUILD_GPIO_PIN(2, 5, 0x2DC, 0x740), |
||||
|
||||
MX35_PIN_FEC_TX_CLK = _MXC_BUILD_GPIO_PIN(2, 6, 0x2E0, 0x744), |
||||
MX35_PIN_FEC_RX_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 0x2E4, 0x748), |
||||
MX35_PIN_FEC_RX_DV = _MXC_BUILD_GPIO_PIN(2, 8, 0x2E8, 0x74C), |
||||
MX35_PIN_FEC_COL = _MXC_BUILD_GPIO_PIN(2, 9, 0x2EC, 0x750), |
||||
MX35_PIN_FEC_RDATA0 = _MXC_BUILD_GPIO_PIN(2, 10, 0x2F0, 0x754), |
||||
MX35_PIN_FEC_TDATA0 = _MXC_BUILD_GPIO_PIN(2, 11, 0x2F4, 0x758), |
||||
MX35_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(2, 12, 0x2F8, 0x75C), |
||||
MX35_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(2, 13, 0x2FC, 0x760), |
||||
MX35_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(2, 14, 0x300, 0x764), |
||||
MX35_PIN_FEC_TX_ERR = _MXC_BUILD_GPIO_PIN(2, 15, 0x304, 0x768), |
||||
MX35_PIN_FEC_RX_ERR = _MXC_BUILD_GPIO_PIN(2, 16, 0x308, 0x76C), |
||||
MX35_PIN_FEC_CRS = _MXC_BUILD_GPIO_PIN(2, 17, 0x30C, 0x770), |
||||
MX35_PIN_FEC_RDATA1 = _MXC_BUILD_GPIO_PIN(2, 18, 0x310, 0x774), |
||||
MX35_PIN_FEC_TDATA1 = _MXC_BUILD_GPIO_PIN(2, 19, 0x314, 0x778), |
||||
MX35_PIN_FEC_RDATA2 = _MXC_BUILD_GPIO_PIN(2, 20, 0x318, 0x77C), |
||||
MX35_PIN_FEC_TDATA2 = _MXC_BUILD_GPIO_PIN(2, 21, 0x31C, 0x780), |
||||
MX35_PIN_FEC_RDATA3 = _MXC_BUILD_GPIO_PIN(2, 22, 0x320, 0x784), |
||||
MX35_PIN_FEC_TDATA3 = _MXC_BUILD_GPIO_PIN(2, 23, 0x324, 0x788), |
||||
} iomux_pin_name_t; |
||||
|
||||
#endif |
||||
#endif |
@ -0,0 +1,31 @@ |
||||
/*
|
||||
* (C) Copyright 2011 |
||||
* Stefano Babic, DENX Software Engineering, sbabic@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef _SYS_PROTO_H_ |
||||
#define _SYS_PROTO_H_ |
||||
|
||||
u32 get_cpu_rev(void); |
||||
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) |
||||
void sdelay(unsigned long); |
||||
|
||||
#endif |
@ -0,0 +1,42 @@ |
||||
/*
|
||||
* Copyright (C) 2010 Samsung Electronics |
||||
* Minkyu Kang <mk7.kang@samsung.com> |
||||
* MyungJoo Ham <myungjoo.ham@samsung.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARM_ARCH_ADC_H_ |
||||
#define __ASM_ARM_ARCH_ADC_H_ |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
struct s5p_adc { |
||||
unsigned int adccon; |
||||
unsigned int adctsc; |
||||
unsigned int adcdly; |
||||
unsigned int adcdat0; |
||||
unsigned int adcdat1; |
||||
unsigned int adcupdn; |
||||
unsigned int adcclrint; |
||||
unsigned int adcmux; |
||||
unsigned int adcclrintpndnup; |
||||
}; |
||||
#endif |
||||
|
||||
#endif /* __ASM_ARM_ARCH_ADC_H_ */ |
@ -0,0 +1,36 @@ |
||||
/*
|
||||
* (C) Copyright 2010 Samsung Electronics |
||||
* Minkyu Kang <mk7.kang@samsung.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARM_ARCH_CLK_H_ |
||||
#define __ASM_ARM_ARCH_CLK_H_ |
||||
|
||||
#define APLL 0 |
||||
#define MPLL 1 |
||||
#define EPLL 2 |
||||
#define HPLL 3 |
||||
#define VPLL 4 |
||||
|
||||
unsigned long get_pll_clk(int pllreg); |
||||
unsigned long get_arm_clk(void); |
||||
unsigned long get_pwm_clk(void); |
||||
unsigned long get_uart_clk(int dev_index); |
||||
|
||||
#endif |
@ -0,0 +1,255 @@ |
||||
/*
|
||||
* (C) Copyright 2010 Samsung Electronics |
||||
* Minkyu Kang <mk7.kang@samsung.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARM_ARCH_CLOCK_H_ |
||||
#define __ASM_ARM_ARCH_CLOCK_H_ |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
struct s5pc210_clock { |
||||
unsigned char res1[0x4200]; |
||||
unsigned int src_leftbus; |
||||
unsigned char res2[0x1fc]; |
||||
unsigned int mux_stat_leftbus; |
||||
unsigned char res4[0xfc]; |
||||
unsigned int div_leftbus; |
||||
unsigned char res5[0xfc]; |
||||
unsigned int div_stat_leftbus; |
||||
unsigned char res6[0x1fc]; |
||||
unsigned int gate_ip_leftbus; |
||||
unsigned char res7[0x1fc]; |
||||
unsigned int clkout_leftbus; |
||||
unsigned int clkout_leftbus_div_stat; |
||||
unsigned char res8[0x37f8]; |
||||
unsigned int src_rightbus; |
||||
unsigned char res9[0x1fc]; |
||||
unsigned int mux_stat_rightbus; |
||||
unsigned char res10[0xfc]; |
||||
unsigned int div_rightbus; |
||||
unsigned char res11[0xfc]; |
||||
unsigned int div_stat_rightbus; |
||||
unsigned char res12[0x1fc]; |
||||
unsigned int gate_ip_rightbus; |
||||
unsigned char res13[0x1fc]; |
||||
unsigned int clkout_rightbus; |
||||
unsigned int clkout_rightbus_div_stat; |
||||
unsigned char res14[0x3608]; |
||||
unsigned int epll_lock; |
||||
unsigned char res15[0xc]; |
||||
unsigned int vpll_lock; |
||||
unsigned char res16[0xec]; |
||||
unsigned int epll_con0; |
||||
unsigned int epll_con1; |
||||
unsigned char res17[0x8]; |
||||
unsigned int vpll_con0; |
||||
unsigned int vpll_con1; |
||||
unsigned char res18[0xe8]; |
||||
unsigned int src_top0; |
||||
unsigned int src_top1; |
||||
unsigned char res19[0x8]; |
||||
unsigned int src_cam; |
||||
unsigned int src_tv; |
||||
unsigned int src_mfc; |
||||
unsigned int src_g3d; |
||||
unsigned int src_image; |
||||
unsigned int src_lcd0; |
||||
unsigned int src_lcd1; |
||||
unsigned int src_maudio; |
||||
unsigned int src_fsys; |
||||
unsigned char res20[0xc]; |
||||
unsigned int src_peril0; |
||||
unsigned int src_peril1; |
||||
unsigned char res21[0xb8]; |
||||
unsigned int src_mask_top; |
||||
unsigned char res22[0xc]; |
||||
unsigned int src_mask_cam; |
||||
unsigned int src_mask_tv; |
||||
unsigned char res23[0xc]; |
||||
unsigned int src_mask_lcd0; |
||||
unsigned int src_mask_lcd1; |
||||
unsigned int src_mask_maudio; |
||||
unsigned int src_mask_fsys; |
||||
unsigned char res24[0xc]; |
||||
unsigned int src_mask_peril0; |
||||
unsigned int src_mask_peril1; |
||||
unsigned char res25[0xb8]; |
||||
unsigned int mux_stat_top; |
||||
unsigned char res26[0x14]; |
||||
unsigned int mux_stat_mfc; |
||||
unsigned int mux_stat_g3d; |
||||
unsigned int mux_stat_image; |
||||
unsigned char res27[0xdc]; |
||||
unsigned int div_top; |
||||
unsigned char res28[0xc]; |
||||
unsigned int div_cam; |
||||
unsigned int div_tv; |
||||
unsigned int div_mfc; |
||||
unsigned int div_g3d; |
||||
unsigned int div_image; |
||||
unsigned int div_lcd0; |
||||
unsigned int div_lcd1; |
||||
unsigned int div_maudio; |
||||
unsigned int div_fsys0; |
||||
unsigned int div_fsys1; |
||||
unsigned int div_fsys2; |
||||
unsigned int div_fsys3; |
||||
unsigned int div_peril0; |
||||
unsigned int div_peril1; |
||||
unsigned int div_peril2; |
||||
unsigned int div_peril3; |
||||
unsigned int div_peril4; |
||||
unsigned int div_peril5; |
||||
unsigned char res29[0x18]; |
||||
unsigned int div2_ratio; |
||||
unsigned char res30[0x8c]; |
||||
unsigned int div_stat_top; |
||||
unsigned char res31[0xc]; |
||||
unsigned int div_stat_cam; |
||||
unsigned int div_stat_tv; |
||||
unsigned int div_stat_mfc; |
||||
unsigned int div_stat_g3d; |
||||
unsigned int div_stat_image; |
||||
unsigned int div_stat_lcd0; |
||||
unsigned int div_stat_lcd1; |
||||
unsigned int div_stat_maudio; |
||||
unsigned int div_stat_fsys0; |
||||
unsigned int div_stat_fsys1; |
||||
unsigned int div_stat_fsys2; |
||||
unsigned int div_stat_fsys3; |
||||
unsigned int div_stat_peril0; |
||||
unsigned int div_stat_peril1; |
||||
unsigned int div_stat_peril2; |
||||
unsigned int div_stat_peril3; |
||||
unsigned int div_stat_peril4; |
||||
unsigned int div_stat_peril5; |
||||
unsigned char res32[0x18]; |
||||
unsigned int div2_stat; |
||||
unsigned char res33[0x29c]; |
||||
unsigned int gate_ip_cam; |
||||
unsigned int gate_ip_tv; |
||||
unsigned int gate_ip_mfc; |
||||
unsigned int gate_ip_g3d; |
||||
unsigned int gate_ip_image; |
||||
unsigned int gate_ip_lcd0; |
||||
unsigned int gate_ip_lcd1; |
||||
unsigned char res34[0x4]; |
||||
unsigned int gate_ip_fsys; |
||||
unsigned char res35[0x8]; |
||||
unsigned int gate_ip_gps; |
||||
unsigned int gate_ip_peril; |
||||
unsigned char res36[0xc]; |
||||
unsigned int gate_ip_perir; |
||||
unsigned char res37[0xc]; |
||||
unsigned int gate_block; |
||||
unsigned char res38[0x8c]; |
||||
unsigned int clkout_cmu_top; |
||||
unsigned int clkout_cmu_top_div_stat; |
||||
unsigned char res39[0x37f8]; |
||||
unsigned int src_dmc; |
||||
unsigned char res40[0xfc]; |
||||
unsigned int src_mask_dmc; |
||||
unsigned char res41[0xfc]; |
||||
unsigned int mux_stat_dmc; |
||||
unsigned char res42[0xfc]; |
||||
unsigned int div_dmc0; |
||||
unsigned int div_dmc1; |
||||
unsigned char res43[0xf8]; |
||||
unsigned int div_stat_dmc0; |
||||
unsigned int div_stat_dmc1; |
||||
unsigned char res44[0x2f8]; |
||||
unsigned int gate_ip_dmc; |
||||
unsigned char res45[0xfc]; |
||||
unsigned int clkout_cmu_dmc; |
||||
unsigned int clkout_cmu_dmc_div_stat; |
||||
unsigned char res46[0x5f8]; |
||||
unsigned int dcgidx_map0; |
||||
unsigned int dcgidx_map1; |
||||
unsigned int dcgidx_map2; |
||||
unsigned char res47[0x14]; |
||||
unsigned int dcgperf_map0; |
||||
unsigned int dcgperf_map1; |
||||
unsigned char res48[0x18]; |
||||
unsigned int dvcidx_map; |
||||
unsigned char res49[0x1c]; |
||||
unsigned int freq_cpu; |
||||
unsigned int freq_dpm; |
||||
unsigned char res50[0x18]; |
||||
unsigned int dvsemclk_en; |
||||
unsigned int maxperf; |
||||
unsigned char res51[0x2f78]; |
||||
unsigned int apll_lock; |
||||
unsigned char res52[0x4]; |
||||
unsigned int mpll_lock; |
||||
unsigned char res53[0xf4]; |
||||
unsigned int apll_con0; |
||||
unsigned int apll_con1; |
||||
unsigned int mpll_con0; |
||||
unsigned int mpll_con1; |
||||
unsigned char res54[0xf0]; |
||||
unsigned int src_cpu; |
||||
unsigned char res55[0x1fc]; |
||||
unsigned int mux_stat_cpu; |
||||
unsigned char res56[0xfc]; |
||||
unsigned int div_cpu0; |
||||
unsigned int div_cpu1; |
||||
unsigned char res57[0xf8]; |
||||
unsigned int div_stat_cpu0; |
||||
unsigned int div_stat_cpu1; |
||||
unsigned char res58[0x3f8]; |
||||
unsigned int clkout_cmu_cpu; |
||||
unsigned int clkout_cmu_cpu_div_stat; |
||||
unsigned char res59[0x5f8]; |
||||
unsigned int armclk_stopctrl; |
||||
unsigned int atclk_stopctrl; |
||||
unsigned char res60[0x8]; |
||||
unsigned int parityfail_status; |
||||
unsigned int parityfail_clear; |
||||
unsigned char res61[0xe8]; |
||||
unsigned int apll_con0_l8; |
||||
unsigned int apll_con0_l7; |
||||
unsigned int apll_con0_l6; |
||||
unsigned int apll_con0_l5; |
||||
unsigned int apll_con0_l4; |
||||
unsigned int apll_con0_l3; |
||||
unsigned int apll_con0_l2; |
||||
unsigned int apll_con0_l1; |
||||
unsigned int iem_control; |
||||
unsigned char res62[0xdc]; |
||||
unsigned int apll_con1_l8; |
||||
unsigned int apll_con1_l7; |
||||
unsigned int apll_con1_l6; |
||||
unsigned int apll_con1_l5; |
||||
unsigned int apll_con1_l4; |
||||
unsigned int apll_con1_l3; |
||||
unsigned int apll_con1_l2; |
||||
unsigned int apll_con1_l1; |
||||
unsigned char res63[0xe0]; |
||||
unsigned int div_iem_l8; |
||||
unsigned int div_iem_l7; |
||||
unsigned int div_iem_l6; |
||||
unsigned int div_iem_l5; |
||||
unsigned int div_iem_l4; |
||||
unsigned int div_iem_l3; |
||||
unsigned int div_iem_l2; |
||||
unsigned int div_iem_l1; |
||||
}; |
||||
#endif |
||||
|
||||
#endif |
@ -0,0 +1,103 @@ |
||||
/*
|
||||
* (C) Copyright 2010 Samsung Electronics |
||||
* Minkyu Kang <mk7.kang@samsung.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#ifndef _S5PC2XX_CPU_H |
||||
#define _S5PC2XX_CPU_H |
||||
|
||||
#define S5PC2XX_ADDR_BASE 0x10000000 |
||||
|
||||
/* S5PC210 */ |
||||
#define S5PC210_GPIO_PART3_BASE 0x03860000 |
||||
#define S5PC210_PRO_ID 0x10000000 |
||||
#define S5PC210_POWER_BASE 0x10020000 |
||||
#define S5PC210_SWRESET 0x10020400 |
||||
#define S5PC210_CLOCK_BASE 0x10030000 |
||||
#define S5PC210_SYSTIMER_BASE 0x10050000 |
||||
#define S5PC210_WATCHDOG_BASE 0x10060000 |
||||
#define S5PC210_MIU_BASE 0x10600000 |
||||
#define S5PC210_DMC0_BASE 0x10400000 |
||||
#define S5PC210_DMC1_BASE 0x10410000 |
||||
#define S5PC210_GPIO_PART2_BASE 0x11000000 |
||||
#define S5PC210_GPIO_PART1_BASE 0x11400000 |
||||
#define S5PC210_FIMD_BASE 0x11C00000 |
||||
#define S5PC210_USBOTG_BASE 0x12480000 |
||||
#define S5PC210_MMC_BASE 0x12510000 |
||||
#define S5PC210_SROMC_BASE 0x12570000 |
||||
#define S5PC210_USBPHY_BASE 0x125B0000 |
||||
#define S5PC210_UART_BASE 0x13800000 |
||||
#define S5PC210_ADC_BASE 0x13910000 |
||||
#define S5PC210_PWMTIMER_BASE 0x139D0000 |
||||
#define S5PC210_MODEM_BASE 0x13A00000 |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
#include <asm/io.h> |
||||
/* CPU detection macros */ |
||||
extern unsigned int s5p_cpu_id; |
||||
|
||||
static inline void s5p_set_cpu_id(void) |
||||
{ |
||||
s5p_cpu_id = readl(S5PC210_PRO_ID); |
||||
s5p_cpu_id = (0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12)); |
||||
|
||||
/*
|
||||
* 0xC200: S5PC210 EVT0 |
||||
* 0xC210: S5PC210 EVT1 |
||||
*/ |
||||
if (s5p_cpu_id == 0xC200) |
||||
s5p_cpu_id |= 0x10; |
||||
} |
||||
|
||||
#define IS_SAMSUNG_TYPE(type, id) \ |
||||
static inline int cpu_is_##type(void) \
|
||||
{ \
|
||||
return s5p_cpu_id == id ? 1 : 0; \
|
||||
} |
||||
|
||||
IS_SAMSUNG_TYPE(s5pc210, 0xc210) |
||||
|
||||
#define SAMSUNG_BASE(device, base) \ |
||||
static inline unsigned int samsung_get_base_##device(void) \
|
||||
{ \
|
||||
if (cpu_is_s5pc210()) \
|
||||
return S5PC210_##base; \
|
||||
else \
|
||||
return 0; \
|
||||
} |
||||
|
||||
SAMSUNG_BASE(adc, ADC_BASE) |
||||
SAMSUNG_BASE(clock, CLOCK_BASE) |
||||
SAMSUNG_BASE(fimd, FIMD_BASE) |
||||
SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE) |
||||
SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE) |
||||
SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE) |
||||
SAMSUNG_BASE(pro_id, PRO_ID) |
||||
SAMSUNG_BASE(mmc, MMC_BASE) |
||||
SAMSUNG_BASE(modem, MODEM_BASE) |
||||
SAMSUNG_BASE(sromc, SROMC_BASE) |
||||
SAMSUNG_BASE(swreset, SWRESET) |
||||
SAMSUNG_BASE(timer, PWMTIMER_BASE) |
||||
SAMSUNG_BASE(uart, UART_BASE) |
||||
SAMSUNG_BASE(usb_phy, USBPHY_BASE) |
||||
SAMSUNG_BASE(usb_otg, USBOTG_BASE) |
||||
SAMSUNG_BASE(watchdog, WATCHDOG_BASE) |
||||
#endif |
||||
|
||||
#endif /* _S5PC2XX_CPU_H */ |
@ -0,0 +1,112 @@ |
||||
/*
|
||||
* (C) Copyright 2010 Samsung Electronics |
||||
* Minkyu Kang <mk7.kang@samsung.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARCH_GPIO_H |
||||
#define __ASM_ARCH_GPIO_H |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
struct s5p_gpio_bank { |
||||
unsigned int con; |
||||
unsigned int dat; |
||||
unsigned int pull; |
||||
unsigned int drv; |
||||
unsigned int pdn_con; |
||||
unsigned int pdn_pull; |
||||
unsigned char res1[8]; |
||||
}; |
||||
|
||||
struct s5pc210_gpio_part1 { |
||||
struct s5p_gpio_bank a0; |
||||
struct s5p_gpio_bank a1; |
||||
struct s5p_gpio_bank b; |
||||
struct s5p_gpio_bank c0; |
||||
struct s5p_gpio_bank c1; |
||||
struct s5p_gpio_bank d0; |
||||
struct s5p_gpio_bank d1; |
||||
struct s5p_gpio_bank e0; |
||||
struct s5p_gpio_bank e1; |
||||
struct s5p_gpio_bank e2; |
||||
struct s5p_gpio_bank e3; |
||||
struct s5p_gpio_bank e4; |
||||
struct s5p_gpio_bank f0; |
||||
struct s5p_gpio_bank f1; |
||||
struct s5p_gpio_bank f2; |
||||
struct s5p_gpio_bank f3; |
||||
}; |
||||
|
||||
struct s5pc210_gpio_part2 { |
||||
struct s5p_gpio_bank j0; |
||||
struct s5p_gpio_bank j1; |
||||
struct s5p_gpio_bank k0; |
||||
struct s5p_gpio_bank k1; |
||||
struct s5p_gpio_bank k2; |
||||
struct s5p_gpio_bank k3; |
||||
struct s5p_gpio_bank l0; |
||||
struct s5p_gpio_bank l1; |
||||
struct s5p_gpio_bank l2; |
||||
struct s5p_gpio_bank y0; |
||||
struct s5p_gpio_bank y1; |
||||
struct s5p_gpio_bank y2; |
||||
struct s5p_gpio_bank y3; |
||||
struct s5p_gpio_bank y4; |
||||
struct s5p_gpio_bank y5; |
||||
struct s5p_gpio_bank y6; |
||||
struct s5p_gpio_bank res1[80]; |
||||
struct s5p_gpio_bank x0; |
||||
struct s5p_gpio_bank x1; |
||||
struct s5p_gpio_bank x2; |
||||
struct s5p_gpio_bank x3; |
||||
}; |
||||
|
||||
struct s5pc210_gpio_part3 { |
||||
struct s5p_gpio_bank z; |
||||
}; |
||||
|
||||
/* functions */ |
||||
void gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg); |
||||
void gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en); |
||||
void gpio_direction_input(struct s5p_gpio_bank *bank, int gpio); |
||||
void gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en); |
||||
unsigned int gpio_get_value(struct s5p_gpio_bank *bank, int gpio); |
||||
void gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode); |
||||
void gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode); |
||||
void gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); |
||||
#endif |
||||
|
||||
/* Pin configurations */ |
||||
#define GPIO_INPUT 0x0 |
||||
#define GPIO_OUTPUT 0x1 |
||||
#define GPIO_IRQ 0xf |
||||
#define GPIO_FUNC(x) (x) |
||||
|
||||
/* Pull mode */ |
||||
#define GPIO_PULL_NONE 0x0 |
||||
#define GPIO_PULL_DOWN 0x1 |
||||
#define GPIO_PULL_UP 0x2 |
||||
|
||||
/* Drive Strength level */ |
||||
#define GPIO_DRV_1X 0x0 |
||||
#define GPIO_DRV_2X 0x1 |
||||
#define GPIO_DRV_3X 0x2 |
||||
#define GPIO_DRV_4X 0x3 |
||||
#define GPIO_DRV_FAST 0x0 |
||||
#define GPIO_DRV_SLOW 0x1 |
||||
|
||||
#endif |
@ -0,0 +1,71 @@ |
||||
/*
|
||||
* (C) Copyright 2009 SAMSUNG Electronics |
||||
* Minkyu Kang <mk7.kang@samsung.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARCH_MMC_H_ |
||||
#define __ASM_ARCH_MMC_H_ |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
struct s5p_mmc { |
||||
unsigned int sysad; |
||||
unsigned short blksize; |
||||
unsigned short blkcnt; |
||||
unsigned int argument; |
||||
unsigned short trnmod; |
||||
unsigned short cmdreg; |
||||
unsigned int rspreg0; |
||||
unsigned int rspreg1; |
||||
unsigned int rspreg2; |
||||
unsigned int rspreg3; |
||||
unsigned int bdata; |
||||
unsigned int prnsts; |
||||
unsigned char hostctl; |
||||
unsigned char pwrcon; |
||||
unsigned char blkgap; |
||||
unsigned char wakcon; |
||||
unsigned short clkcon; |
||||
unsigned char timeoutcon; |
||||
unsigned char swrst; |
||||
unsigned int norintsts; /* errintsts */ |
||||
unsigned int norintstsen; /* errintstsen */ |
||||
unsigned int norintsigen; /* errintsigen */ |
||||
unsigned short acmd12errsts; |
||||
unsigned char res1[2]; |
||||
unsigned int capareg; |
||||
unsigned char res2[4]; |
||||
unsigned int maxcurr; |
||||
unsigned char res3[0x34]; |
||||
unsigned int control2; |
||||
unsigned int control3; |
||||
unsigned int control4; |
||||
unsigned char res4[0x6e]; |
||||
unsigned short hcver; |
||||
unsigned char res5[0xFF02]; |
||||
}; |
||||
|
||||
struct mmc_host { |
||||
struct s5p_mmc *reg; |
||||
unsigned int version; /* SDHCI spec. version */ |
||||
unsigned int clock; /* Current clock (MHz) */ |
||||
}; |
||||
|
||||
int s5p_mmc_init(int dev_index, int bus_width); |
||||
|
||||
#endif /* __ASSEMBLY__ */ |
||||
#endif |
@ -0,0 +1,55 @@ |
||||
/*
|
||||
* Copyright (C) 2009 Samsung Electronics |
||||
* Kyungmin Park <kyungmin.park@samsung.com> |
||||
* Minkyu Kang <mk7.kang@samsung.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARM_ARCH_PWM_H_ |
||||
#define __ASM_ARM_ARCH_PWM_H_ |
||||
|
||||
/* Interval mode(Auto Reload) of PWM Timer 4 */ |
||||
#define TCON4_AUTO_RELOAD (1 << 22) |
||||
/* Update TCNTB4 */ |
||||
#define TCON4_UPDATE (1 << 21) |
||||
/* start bit of PWM Timer 4 */ |
||||
#define TCON4_START (1 << 20) |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
struct s5p_timer { |
||||
unsigned int tcfg0; |
||||
unsigned int tcfg1; |
||||
unsigned int tcon; |
||||
unsigned int tcntb0; |
||||
unsigned int tcmpb0; |
||||
unsigned int tcnto0; |
||||
unsigned int tcntb1; |
||||
unsigned int tcmpb1; |
||||
unsigned int tcnto1; |
||||
unsigned int tcntb2; |
||||
unsigned int tcmpb2; |
||||
unsigned int tcnto2; |
||||
unsigned int tcntb3; |
||||
unsigned int res1; |
||||
unsigned int tcnto3; |
||||
unsigned int tcntb4; |
||||
unsigned int tcnto4; |
||||
unsigned int tintcstat; |
||||
}; |
||||
#endif /* __ASSEMBLY__ */ |
||||
|
||||
#endif |
@ -0,0 +1,32 @@ |
||||
/*
|
||||
* Copyright (C) 2010 Samsung Electrnoics |
||||
* Minkyu Kang <mk7.kang@samsung.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef _SYS_PROTO_H_ |
||||
#define _SYS_PROTO_H_ |
||||
|
||||
u32 get_device_type(void); |
||||
void invalidate_dcache(u32); |
||||
void l2_cache_disable(void); |
||||
void l2_cache_enable(void); |
||||
|
||||
#endif |
@ -0,0 +1,58 @@ |
||||
/*
|
||||
* (C) Copyright 2009 Samsung Electronics |
||||
* Minkyu Kang <mk7.kang@samsung.com> |
||||
* Heungjun Kim <riverful.kim@samsung.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARCH_UART_H_ |
||||
#define __ASM_ARCH_UART_H_ |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
/* baudrate rest value */ |
||||
union br_rest { |
||||
unsigned short slot; /* udivslot */ |
||||
unsigned char value; /* ufracval */ |
||||
}; |
||||
|
||||
struct s5p_uart { |
||||
unsigned int ulcon; |
||||
unsigned int ucon; |
||||
unsigned int ufcon; |
||||
unsigned int umcon; |
||||
unsigned int utrstat; |
||||
unsigned int uerstat; |
||||
unsigned int ufstat; |
||||
unsigned int umstat; |
||||
unsigned char utxh; |
||||
unsigned char res1[3]; |
||||
unsigned char urxh; |
||||
unsigned char res2[3]; |
||||
unsigned int ubrdiv; |
||||
union br_rest rest; |
||||
unsigned char res3[0xffd0]; |
||||
}; |
||||
|
||||
static inline int s5p_uart_divslot(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
#endif /* __ASSEMBLY__ */ |
||||
|
||||
#endif |
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,47 @@ |
||||
#
|
||||
# (C) Copyright 2000, 2001, 2002
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := cm_t35.o
|
||||
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) |
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean: |
||||
rm -f $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
@ -0,0 +1,371 @@ |
||||
/*
|
||||
* (C) Copyright 2010 |
||||
* CompuLab, Ltd. <www.compulab.co.il> |
||||
* |
||||
* Author: Mike Rapoport <mike@compulab.co.il> |
||||
* |
||||
* Derived from omap3evm and Beagle Board by |
||||
* Manikandan Pillai <mani.pillai@ti.com> |
||||
* Richard Woodruff <r-woodruff2@ti.com> |
||||
* Syed Mohammed Khasim <x0khasim@ti.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <netdev.h> |
||||
#include <net.h> |
||||
#include <i2c.h> |
||||
#include <twl4030.h> |
||||
|
||||
#include <asm/io.h> |
||||
#include <asm/arch/mem.h> |
||||
#include <asm/arch/mux.h> |
||||
#include <asm/arch/mmc_host_def.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/mach-types.h> |
||||
|
||||
const omap3_sysinfo sysinfo = { |
||||
DDR_DISCRETE, |
||||
"CM-T35 board", |
||||
"NAND", |
||||
}; |
||||
|
||||
static u32 gpmc_net_config[GPMC_MAX_REG] = { |
||||
NET_GPMC_CONFIG1, |
||||
NET_GPMC_CONFIG2, |
||||
NET_GPMC_CONFIG3, |
||||
NET_GPMC_CONFIG4, |
||||
NET_GPMC_CONFIG5, |
||||
NET_GPMC_CONFIG6, |
||||
0 |
||||
}; |
||||
|
||||
static u32 gpmc_nand_config[GPMC_MAX_REG] = { |
||||
SMNAND_GPMC_CONFIG1, |
||||
SMNAND_GPMC_CONFIG2, |
||||
SMNAND_GPMC_CONFIG3, |
||||
SMNAND_GPMC_CONFIG4, |
||||
SMNAND_GPMC_CONFIG5, |
||||
SMNAND_GPMC_CONFIG6, |
||||
0, |
||||
}; |
||||
|
||||
/*
|
||||
* Routine: board_init |
||||
* Description: Early hardware init. |
||||
*/ |
||||
int board_init(void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ |
||||
|
||||
enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0], |
||||
CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M); |
||||
|
||||
/* board id for Linux */ |
||||
gd->bd->bi_arch_number = MACH_TYPE_CM_T35; |
||||
/* boot param addr */ |
||||
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Routine: misc_init_r |
||||
* Description: Init I2C and display die ID |
||||
*/ |
||||
int misc_init_r(void) |
||||
{ |
||||
#ifdef CONFIG_DRIVER_OMAP34XX_I2C |
||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
||||
#endif |
||||
|
||||
dieid_num_r(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Routine: set_muxconf_regs |
||||
* Description: Setting up the configuration Mux registers specific to the |
||||
* hardware. Many pins need to be moved from protect to primary |
||||
* mode. |
||||
*/ |
||||
void set_muxconf_regs(void) |
||||
{ |
||||
/* SDRC */ |
||||
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/ |
||||
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/ |
||||
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/ |
||||
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/ |
||||
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/ |
||||
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/ |
||||
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/ |
||||
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/ |
||||
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/ |
||||
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/ |
||||
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/ |
||||
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/ |
||||
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/ |
||||
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/ |
||||
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/ |
||||
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/ |
||||
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/ |
||||
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/ |
||||
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/ |
||||
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/ |
||||
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/ |
||||
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/ |
||||
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/ |
||||
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/ |
||||
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/ |
||||
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/ |
||||
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/ |
||||
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/ |
||||
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/ |
||||
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/ |
||||
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/ |
||||
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/ |
||||
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/ |
||||
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/ |
||||
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/ |
||||
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/ |
||||
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/ |
||||
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/ |
||||
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/ |
||||
|
||||
/* GPMC */ |
||||
MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ |
||||
MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ |
||||
MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ |
||||
MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ |
||||
MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ |
||||
MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ |
||||
MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ |
||||
MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ |
||||
MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/ |
||||
MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/ |
||||
MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/ |
||||
MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/ |
||||
MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/ |
||||
MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/ |
||||
MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/ |
||||
MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/ |
||||
MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/ |
||||
MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/ |
||||
MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/ |
||||
MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/ |
||||
MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/ |
||||
MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/ |
||||
MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/ |
||||
MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/ |
||||
MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/ |
||||
MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/ |
||||
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/ |
||||
|
||||
/* SB-T35 Ethernet */ |
||||
MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/ |
||||
|
||||
/* CM-T35 Ethernet */ |
||||
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/ |
||||
MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/ |
||||
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*nADV_ALE*/ |
||||
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*nOE*/ |
||||
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*nWE*/ |
||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*nBE0_CLE*/ |
||||
MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); /*GPIO_61*/ |
||||
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*nWP*/ |
||||
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*WAIT0*/ |
||||
|
||||
/* DSS */ |
||||
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/ |
||||
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/ |
||||
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/ |
||||
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/ |
||||
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/ |
||||
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/ |
||||
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/ |
||||
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/ |
||||
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/ |
||||
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/ |
||||
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/ |
||||
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/ |
||||
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/ |
||||
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/ |
||||
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/ |
||||
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/ |
||||
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/ |
||||
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/ |
||||
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/ |
||||
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/ |
||||
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/ |
||||
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/ |
||||
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/ |
||||
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/ |
||||
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/ |
||||
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/ |
||||
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/ |
||||
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/ |
||||
|
||||
/* serial interface */ |
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX*/ |
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX*/ |
||||
|
||||
/* mUSB */ |
||||
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/ |
||||
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/ |
||||
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/ |
||||
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/ |
||||
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/ |
||||
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/ |
||||
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/ |
||||
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/ |
||||
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/ |
||||
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/ |
||||
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/ |
||||
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/ |
||||
|
||||
/* I2C1 */ |
||||
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/ |
||||
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/ |
||||
|
||||
/* control and debug */ |
||||
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/ |
||||
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/ |
||||
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/ |
||||
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/ |
||||
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/ |
||||
MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M4)); /*green LED*/ |
||||
MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); /*JTAG_nTRST*/ |
||||
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/ |
||||
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/ |
||||
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/ |
||||
} |
||||
|
||||
#ifdef CONFIG_GENERIC_MMC |
||||
int board_mmc_init(bd_t *bis) |
||||
{ |
||||
return omap_mmc_init(0); |
||||
} |
||||
#endif |
||||
|
||||
/*
|
||||
* Routine: setup_net_chip_gmpc |
||||
* Description: Setting up the configuration GPMC registers specific to the |
||||
* Ethernet hardware. |
||||
*/ |
||||
static void setup_net_chip_gmpc(void) |
||||
{ |
||||
struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; |
||||
|
||||
enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5], |
||||
CM_T35_SMC911X_BASE, GPMC_SIZE_16M); |
||||
enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4], |
||||
SB_T35_SMC911X_BASE, GPMC_SIZE_16M); |
||||
|
||||
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */ |
||||
writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); |
||||
|
||||
/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ |
||||
writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); |
||||
|
||||
/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ |
||||
writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, |
||||
&ctrl_base->gpmc_nadv_ale); |
||||
} |
||||
|
||||
#ifdef CONFIG_DRIVER_OMAP34XX_I2C |
||||
/*
|
||||
* Routine: reset_net_chip |
||||
* Description: reset the Ethernet controller via TPS65930 GPIO |
||||
*/ |
||||
static void reset_net_chip(void) |
||||
{ |
||||
/* Set GPIO1 of TPS65930 as output */ |
||||
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02, |
||||
TWL4030_BASEADD_GPIO+0x03); |
||||
/* Send a pulse on the GPIO pin */ |
||||
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02, |
||||
TWL4030_BASEADD_GPIO+0x0C); |
||||
udelay(1); |
||||
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02, |
||||
TWL4030_BASEADD_GPIO+0x09); |
||||
udelay(1); |
||||
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02, |
||||
TWL4030_BASEADD_GPIO+0x0C); |
||||
} |
||||
#else |
||||
static inline void reset_net_chip(void) {} |
||||
#endif |
||||
|
||||
/*
|
||||
* Routine: handle_mac_address |
||||
* Description: prepare MAC address for on-board Ethernet. |
||||
*/ |
||||
static int handle_mac_address(void) |
||||
{ |
||||
unsigned char enetaddr[6]; |
||||
int rc; |
||||
|
||||
rc = eth_getenv_enetaddr("ethaddr", enetaddr); |
||||
if (rc) |
||||
return 0; |
||||
|
||||
#ifdef CONFIG_DRIVER_OMAP34XX_I2C |
||||
rc = i2c_read(0x50, 0, 1, enetaddr, 6); |
||||
if (rc) |
||||
return rc; |
||||
#endif |
||||
|
||||
if (!is_valid_ether_addr(enetaddr)) |
||||
return -1; |
||||
|
||||
return eth_setenv_enetaddr("ethaddr", enetaddr); |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Routine: board_eth_init |
||||
* Description: initialize module and base-board Ethernet chips |
||||
*/ |
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
int rc = 0, rc1 = 0; |
||||
|
||||
#ifdef CONFIG_SMC911X |
||||
setup_net_chip_gmpc(); |
||||
reset_net_chip(); |
||||
|
||||
rc1 = handle_mac_address(); |
||||
if (rc1) |
||||
printf("CM-T35: No MAC address found\n"); |
||||
|
||||
rc1 = smc911x_initialize(0, CM_T35_SMC911X_BASE); |
||||
if (rc1 > 0) |
||||
rc++; |
||||
|
||||
rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE); |
||||
if (rc1 > 0) |
||||
rc++; |
||||
#endif |
||||
|
||||
return rc; |
||||
} |
@ -0,0 +1,52 @@ |
||||
#
|
||||
# Copyright (C) 2010, Marek Vasut <marek.vasut@gmail.com>
|
||||
#
|
||||
# BASED ON: imx51evk
|
||||
#
|
||||
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
|
||||
#
|
||||
# (C) Copyright 2009 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := efikamx.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
||||
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
@ -0,0 +1,689 @@ |
||||
/*
|
||||
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> |
||||
* |
||||
* (C) Copyright 2009 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/imx-regs.h> |
||||
#include <asm/arch/mx5x_pins.h> |
||||
#include <asm/arch/iomux.h> |
||||
#include <mxc_gpio.h> |
||||
#include <asm/errno.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/arch/crm_regs.h> |
||||
#include <i2c.h> |
||||
#include <mmc.h> |
||||
#include <fsl_esdhc.h> |
||||
#include <fsl_pmic.h> |
||||
#include <mc13892.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/*
|
||||
* Compile-time error checking |
||||
*/ |
||||
#ifndef CONFIG_MXC_SPI |
||||
#error "CONFIG_MXC_SPI not set, this is essential for board's operation!" |
||||
#endif |
||||
|
||||
/*
|
||||
* Shared variables / local defines |
||||
*/ |
||||
/* LED */ |
||||
#define EFIKAMX_LED_BLUE 0x1 |
||||
#define EFIKAMX_LED_GREEN 0x2 |
||||
#define EFIKAMX_LED_RED 0x4 |
||||
|
||||
void efikamx_toggle_led(uint32_t mask); |
||||
|
||||
/* Board revisions */ |
||||
#define EFIKAMX_BOARD_REV_11 0x1 |
||||
#define EFIKAMX_BOARD_REV_12 0x2 |
||||
#define EFIKAMX_BOARD_REV_13 0x3 |
||||
#define EFIKAMX_BOARD_REV_14 0x4 |
||||
|
||||
/*
|
||||
* Board identification |
||||
*/ |
||||
u32 get_efika_rev(void) |
||||
{ |
||||
u32 rev = 0; |
||||
/*
|
||||
* Retrieve board ID: |
||||
* rev1.1: 1,1,1 |
||||
* rev1.2: 1,1,0 |
||||
* rev1.3: 1,0,1 |
||||
* rev1.4: 1,0,0 |
||||
*/ |
||||
mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO); |
||||
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), |
||||
MXC_GPIO_DIRECTION_OUT); |
||||
/* set to 1 in order to get correct value on board rev1.1 */ |
||||
mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1); |
||||
|
||||
mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CS0, PAD_CTL_100K_PU); |
||||
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), |
||||
MXC_GPIO_DIRECTION_IN); |
||||
rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0; |
||||
|
||||
mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_GPIO); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CS1, PAD_CTL_100K_PU); |
||||
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1), |
||||
MXC_GPIO_DIRECTION_IN); |
||||
rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1; |
||||
|
||||
mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_GPIO); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, PAD_CTL_100K_PU); |
||||
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3), |
||||
MXC_GPIO_DIRECTION_IN); |
||||
rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2; |
||||
|
||||
return (~rev & 0x7) + 1; |
||||
} |
||||
|
||||
u32 get_board_rev(void) |
||||
{ |
||||
return get_cpu_rev() | (get_efika_rev() << 8); |
||||
} |
||||
|
||||
/*
|
||||
* DRAM initialization |
||||
*/ |
||||
int dram_init(void) |
||||
{ |
||||
/* dram_init must store complete ramsize in gd->ram_size */ |
||||
gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, |
||||
PHYS_SDRAM_1_SIZE); |
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* UART configuration |
||||
*/ |
||||
static void setup_iomux_uart(void) |
||||
{ |
||||
unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | |
||||
PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH; |
||||
|
||||
mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST); |
||||
mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST); |
||||
mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad); |
||||
mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad); |
||||
} |
||||
|
||||
/*
|
||||
* SPI configuration |
||||
*/ |
||||
#ifdef CONFIG_MXC_SPI |
||||
static void setup_iomux_spi(void) |
||||
{ |
||||
/* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */ |
||||
mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); |
||||
|
||||
/* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */ |
||||
mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); |
||||
|
||||
/* Configure SS0 as a GPIO */ |
||||
mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO); |
||||
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), |
||||
MXC_GPIO_DIRECTION_OUT); |
||||
mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0); |
||||
|
||||
/* Configure SS1 as a GPIO */ |
||||
mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO); |
||||
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), |
||||
MXC_GPIO_DIRECTION_OUT); |
||||
mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1); |
||||
|
||||
/* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */ |
||||
mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); |
||||
|
||||
/* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */ |
||||
mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); |
||||
} |
||||
#else |
||||
static inline void setup_iomux_spi(void) { } |
||||
#endif |
||||
|
||||
/*
|
||||
* PMIC configuration |
||||
*/ |
||||
#ifdef CONFIG_MXC_SPI |
||||
static void power_init(void) |
||||
{ |
||||
unsigned int val; |
||||
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; |
||||
|
||||
/* Write needed to Power Gate 2 register */ |
||||
val = pmic_reg_read(REG_POWER_MISC); |
||||
val &= ~PWGT2SPIEN; |
||||
pmic_reg_write(REG_POWER_MISC, val); |
||||
|
||||
/* Externally powered */ |
||||
val = pmic_reg_read(REG_CHARGE); |
||||
val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB; |
||||
pmic_reg_write(REG_CHARGE, val); |
||||
|
||||
/* power up the system first */ |
||||
pmic_reg_write(REG_POWER_MISC, PWUP); |
||||
|
||||
/* Set core voltage to 1.1V */ |
||||
val = pmic_reg_read(REG_SW_0); |
||||
val = (val & ~SWx_VOLT_MASK) | SWx_1_100V; |
||||
pmic_reg_write(REG_SW_0, val); |
||||
|
||||
/* Setup VCC (SW2) to 1.25 */ |
||||
val = pmic_reg_read(REG_SW_1); |
||||
val = (val & ~SWx_VOLT_MASK) | SWx_1_250V; |
||||
pmic_reg_write(REG_SW_1, val); |
||||
|
||||
/* Setup 1V2_DIG1 (SW3) to 1.25 */ |
||||
val = pmic_reg_read(REG_SW_2); |
||||
val = (val & ~SWx_VOLT_MASK) | SWx_1_250V; |
||||
pmic_reg_write(REG_SW_2, val); |
||||
udelay(50); |
||||
|
||||
/* Raise the core frequency to 800MHz */ |
||||
writel(0x0, &mxc_ccm->cacrr); |
||||
|
||||
/* Set switchers in Auto in NORMAL mode & STANDBY mode */ |
||||
/* Setup the switcher mode for SW1 & SW2*/ |
||||
val = pmic_reg_read(REG_SW_4); |
||||
val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | |
||||
(SWMODE_MASK << SWMODE2_SHIFT))); |
||||
val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | |
||||
(SWMODE_AUTO_AUTO << SWMODE2_SHIFT); |
||||
pmic_reg_write(REG_SW_4, val); |
||||
|
||||
/* Setup the switcher mode for SW3 & SW4 */ |
||||
val = pmic_reg_read(REG_SW_5); |
||||
val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) | |
||||
(SWMODE_MASK << SWMODE4_SHIFT))); |
||||
val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) | |
||||
(SWMODE_AUTO_AUTO << SWMODE4_SHIFT); |
||||
pmic_reg_write(REG_SW_5, val); |
||||
|
||||
/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */ |
||||
val = pmic_reg_read(REG_SETTING_0); |
||||
val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK); |
||||
val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6; |
||||
pmic_reg_write(REG_SETTING_0, val); |
||||
|
||||
/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ |
||||
val = pmic_reg_read(REG_SETTING_1); |
||||
val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK); |
||||
val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775; |
||||
pmic_reg_write(REG_SETTING_1, val); |
||||
|
||||
/* Configure VGEN3 and VCAM regulators to use external PNP */ |
||||
val = VGEN3CONFIG | VCAMCONFIG; |
||||
pmic_reg_write(REG_MODE_1, val); |
||||
udelay(200); |
||||
|
||||
/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ |
||||
val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | |
||||
VVIDEOEN | VAUDIOEN | VSDEN; |
||||
pmic_reg_write(REG_MODE_1, val); |
||||
|
||||
val = pmic_reg_read(REG_POWER_CTL2); |
||||
val |= WDIRESET; |
||||
pmic_reg_write(REG_POWER_CTL2, val); |
||||
|
||||
udelay(2500); |
||||
} |
||||
#else |
||||
static inline void power_init(void) { } |
||||
#endif |
||||
|
||||
/*
|
||||
* MMC configuration |
||||
*/ |
||||
#ifdef CONFIG_FSL_ESDHC |
||||
struct fsl_esdhc_cfg esdhc_cfg[2] = { |
||||
{MMC_SDHC1_BASE_ADDR, 1}, |
||||
{MMC_SDHC2_BASE_ADDR, 1}, |
||||
}; |
||||
|
||||
int board_mmc_getcd(u8 *absent, struct mmc *mmc) |
||||
{ |
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
||||
|
||||
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) |
||||
*absent = mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0)); |
||||
else |
||||
*absent = mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8)); |
||||
|
||||
return 0; |
||||
} |
||||
int board_mmc_init(bd_t *bis) |
||||
{ |
||||
int ret; |
||||
|
||||
/* SDHC1 is used on all revisions, setup control pins first */ |
||||
mxc_request_iomux(MX51_PIN_GPIO1_0, |
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); |
||||
mxc_iomux_set_pad(MX51_PIN_GPIO1_0, |
||||
PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | |
||||
PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU | |
||||
PAD_CTL_ODE_OPENDRAIN_NONE | |
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); |
||||
mxc_request_iomux(MX51_PIN_GPIO1_1, |
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); |
||||
mxc_iomux_set_pad(MX51_PIN_GPIO1_1, |
||||
PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | |
||||
PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | |
||||
PAD_CTL_SRE_FAST); |
||||
|
||||
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0), |
||||
MXC_GPIO_DIRECTION_IN); |
||||
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1), |
||||
MXC_GPIO_DIRECTION_IN); |
||||
|
||||
/* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */ |
||||
if (get_efika_rev() < EFIKAMX_BOARD_REV_12) { |
||||
/* SDHC1 IOMUX */ |
||||
mxc_request_iomux(MX51_PIN_SD1_CMD, |
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); |
||||
mxc_iomux_set_pad(MX51_PIN_SD1_CMD, |
||||
PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | |
||||
PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); |
||||
|
||||
mxc_request_iomux(MX51_PIN_SD1_CLK, |
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); |
||||
mxc_iomux_set_pad(MX51_PIN_SD1_CLK, |
||||
PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | |
||||
PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); |
||||
|
||||
mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, |
||||
PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | |
||||
PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); |
||||
|
||||
mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, |
||||
PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | |
||||
PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); |
||||
|
||||
mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, |
||||
PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | |
||||
PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); |
||||
|
||||
mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, |
||||
PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | |
||||
PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); |
||||
|
||||
/* SDHC2 IOMUX */ |
||||
mxc_request_iomux(MX51_PIN_SD2_CMD, |
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); |
||||
mxc_iomux_set_pad(MX51_PIN_SD2_CMD, |
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); |
||||
|
||||
mxc_request_iomux(MX51_PIN_SD2_CLK, |
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); |
||||
mxc_iomux_set_pad(MX51_PIN_SD2_CLK, |
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); |
||||
|
||||
mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX51_PIN_SD2_DATA0, |
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); |
||||
|
||||
mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX51_PIN_SD2_DATA1, |
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); |
||||
|
||||
mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX51_PIN_SD2_DATA2, |
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); |
||||
|
||||
mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX51_PIN_SD2_DATA3, |
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); |
||||
|
||||
/* SDHC2 Control lines IOMUX */ |
||||
mxc_request_iomux(MX51_PIN_GPIO1_7, |
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); |
||||
mxc_iomux_set_pad(MX51_PIN_GPIO1_7, |
||||
PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | |
||||
PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU | |
||||
PAD_CTL_ODE_OPENDRAIN_NONE | |
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); |
||||
mxc_request_iomux(MX51_PIN_GPIO1_8, |
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); |
||||
mxc_iomux_set_pad(MX51_PIN_GPIO1_8, |
||||
PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | |
||||
PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | |
||||
PAD_CTL_SRE_FAST); |
||||
|
||||
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8), |
||||
MXC_GPIO_DIRECTION_IN); |
||||
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7), |
||||
MXC_GPIO_DIRECTION_IN); |
||||
|
||||
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); |
||||
if (!ret) |
||||
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]); |
||||
} else { /* New boards use only SDHC1 */ |
||||
/* SDHC1 IOMUX */ |
||||
mxc_request_iomux(MX51_PIN_SD1_CMD, |
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); |
||||
mxc_iomux_set_pad(MX51_PIN_SD1_CMD, |
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); |
||||
|
||||
mxc_request_iomux(MX51_PIN_SD1_CLK, |
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); |
||||
mxc_iomux_set_pad(MX51_PIN_SD1_CLK, |
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); |
||||
|
||||
mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, |
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); |
||||
|
||||
mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, |
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); |
||||
|
||||
mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, |
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); |
||||
|
||||
mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, |
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); |
||||
|
||||
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); |
||||
} |
||||
return ret; |
||||
} |
||||
#endif |
||||
|
||||
/*
|
||||
* ATA |
||||
*/ |
||||
#ifdef CONFIG_MX51_PATA |
||||
#define ATA_PAD_CONFIG (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH) |
||||
void setup_iomux_ata(void) |
||||
{ |
||||
mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D0, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D1, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D2, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D3, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D4, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D5, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D6, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D7, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D8, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D9, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D10, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D11, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D12, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D13, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D14, ATA_PAD_CONFIG); |
||||
mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1); |
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D15, ATA_PAD_CONFIG); |
||||
} |
||||
#else |
||||
static inline void setup_iomux_ata(void) { } |
||||
#endif |
||||
|
||||
/*
|
||||
* LED configuration |
||||
*/ |
||||
void setup_iomux_led(void) |
||||
{ |
||||
/* Blue LED */ |
||||
mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3); |
||||
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), |
||||
MXC_GPIO_DIRECTION_OUT); |
||||
/* Green LED */ |
||||
mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3); |
||||
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), |
||||
MXC_GPIO_DIRECTION_OUT); |
||||
/* Red LED */ |
||||
mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3); |
||||
mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), |
||||
MXC_GPIO_DIRECTION_OUT); |
||||
} |
||||
|
||||
void efikamx_toggle_led(uint32_t mask) |
||||
{ |
||||
mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), |
||||
mask & EFIKAMX_LED_BLUE); |
||||
mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), |
||||
mask & EFIKAMX_LED_GREEN); |
||||
mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), |
||||
mask & EFIKAMX_LED_RED); |
||||
} |
||||
|
||||
/*
|
||||
* Board initialization |
||||
*/ |
||||
static void init_drive_strength(void) |
||||
{ |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS, |
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS, |
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM); |
||||
|
||||
/* Setting pad options */ |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE, |
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | |
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0, |
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | |
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1, |
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | |
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK, |
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | |
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0, |
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | |
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1, |
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | |
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2, |
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | |
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3, |
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | |
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0, |
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | |
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1, |
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | |
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0, |
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | |
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1, |
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | |
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2, |
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | |
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); |
||||
mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3, |
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | |
||||
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); |
||||
} |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
init_drive_strength(); |
||||
|
||||
setup_iomux_uart(); |
||||
setup_iomux_spi(); |
||||
setup_iomux_led(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
gd->bd->bi_arch_number = MACH_TYPE_MX51_LANGE51; |
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_late_init(void) |
||||
{ |
||||
setup_iomux_spi(); |
||||
|
||||
power_init(); |
||||
|
||||
setup_iomux_led(); |
||||
setup_iomux_ata(); |
||||
|
||||
efikamx_toggle_led(EFIKAMX_LED_BLUE); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
u32 system_rev = get_cpu_rev(); |
||||
u32 cause; |
||||
struct src *src_regs = (struct src *)SRC_BASE_ADDR; |
||||
|
||||
puts("Board: Efika MX "); |
||||
|
||||
switch (system_rev & 0xff) { |
||||
case CHIP_REV_3_0: |
||||
puts("3.0 ["); |
||||
break; |
||||
case CHIP_REV_2_5: |
||||
puts("2.5 ["); |
||||
break; |
||||
case CHIP_REV_2_0: |
||||
puts("2.0 ["); |
||||
break; |
||||
case CHIP_REV_1_1: |
||||
puts("1.1 ["); |
||||
break; |
||||
case CHIP_REV_1_0: |
||||
default: |
||||
puts("1.0 ["); |
||||
break; |
||||
} |
||||
|
||||
cause = src_regs->srsr; |
||||
switch (cause) { |
||||
case 0x0001: |
||||
puts("POR"); |
||||
break; |
||||
case 0x0009: |
||||
puts("RST"); |
||||
break; |
||||
case 0x0010: |
||||
case 0x0011: |
||||
puts("WDOG"); |
||||
break; |
||||
default: |
||||
printf("unknown 0x%x", cause); |
||||
} |
||||
puts("]\n"); |
||||
|
||||
return 0; |
||||
} |
@ -0,0 +1,122 @@ |
||||
# |
||||
# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> |
||||
# |
||||
# BASED ON: imx51evk |
||||
# |
||||
# (C) Copyright 2009 |
||||
# Stefano Babic DENX Software Engineering sbabic@denx.de. |
||||
# |
||||
# See file CREDITS for list of people who contributed to this |
||||
# project. |
||||
# |
||||
# This program is free software; you can redistribute it and/or |
||||
# modify it under the terms of the GNU General Public License as |
||||
# published by the Free Software Foundation; either version 2 of |
||||
# the License or (at your option) any later version. |
||||
# |
||||
# This program is distributed in the hope that it will be useful, |
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
# GNU General Public License for more details. |
||||
# |
||||
# You should have received a copy of the GNU General Public License |
||||
# along with this program; if not write to the Free Software |
||||
# Foundation Inc. 51 Franklin Street Fifth Floor Boston, |
||||
# MA 02110-1301 USA |
||||
# |
||||
# Refer docs/README.imxmage for more details about how-to configure |
||||
# and create imximage boot image |
||||
# |
||||
# The syntax is taken as close as possible with the kwbimage |
||||
|
||||
# Boot Device : one of |
||||
# spi, sd (the board has no nand neither onenand) |
||||
BOOT_FROM spi |
||||
|
||||
# Device Configuration Data (DCD) |
||||
# |
||||
# Each entry must have the format: |
||||
# Addr-type Address Value |
||||
# |
||||
# where: |
||||
# Addr-type register length (1,2 or 4 bytes) |
||||
# Address absolute address of the register |
||||
# value value to be stored in the register |
||||
|
||||
# Setting IOMUXC |
||||
DATA 4 0x73fa88a0 0x000 |
||||
DATA 4 0x73fa850c 0x20c5 |
||||
DATA 4 0x73fa8510 0x20c5 |
||||
DATA 4 0x73fa883c 0x5 |
||||
DATA 4 0x73fa8848 0x5 |
||||
DATA 4 0x73fa84b8 0xe7 |
||||
DATA 4 0x73fa84bc 0x45 |
||||
DATA 4 0x73fa84c0 0x45 |
||||
DATA 4 0x73fa84c4 0x45 |
||||
DATA 4 0x73fa84c8 0x45 |
||||
DATA 4 0x73fa8820 0x0 |
||||
DATA 4 0x73fa84a4 0x5 |
||||
DATA 4 0x73fa84a8 0x5 |
||||
DATA 4 0x73fa84ac 0xe5 |
||||
DATA 4 0x73fa84b0 0xe5 |
||||
DATA 4 0x73fa84b4 0xe5 |
||||
DATA 4 0x73fa84cc 0xe5 |
||||
DATA 4 0x73fa84d0 0xe4 |
||||
|
||||
DATA 4 0x73fa882c 0x4 |
||||
DATA 4 0x73fa88a4 0x4 |
||||
DATA 4 0x73fa88ac 0x4 |
||||
DATA 4 0x73fa88b8 0x4 |
||||
|
||||
# Setting DDR for micron |
||||
# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model |
||||
# CAS=3 BL=4 |
||||
# ESDCTL_ESDCTL0 |
||||
DATA 4 0x83fd9000 0x82a20000 |
||||
# ESDCTL_ESDCTL1 |
||||
DATA 4 0x83fd9008 0x82a20000 |
||||
# ESDCTL_ESDMISC |
||||
DATA 4 0x83fd9010 0xcaaaf6d0 |
||||
# ESDCTL_ESDCFG0 |
||||
DATA 4 0x83fd9004 0x3f3574aa |
||||
# ESDCTL_ESDCFG1 |
||||
DATA 4 0x83fd900c 0x3f3574aa |
||||
|
||||
# Init DRAM on CS0 |
||||
# ESDCTL_ESDSCR |
||||
DATA 4 0x83fd9014 0x04008008 |
||||
DATA 4 0x83fd9014 0x0000801a |
||||
DATA 4 0x83fd9014 0x0000801b |
||||
DATA 4 0x83fd9014 0x00448019 |
||||
DATA 4 0x83fd9014 0x07328018 |
||||
DATA 4 0x83fd9014 0x04008008 |
||||
DATA 4 0x83fd9014 0x00008010 |
||||
DATA 4 0x83fd9014 0x00008010 |
||||
DATA 4 0x83fd9014 0x06328018 |
||||
DATA 4 0x83fd9014 0x03808019 |
||||
DATA 4 0x83fd9014 0x00408019 |
||||
DATA 4 0x83fd9014 0x00008000 |
||||
|
||||
# Init DRAM on CS1 |
||||
DATA 4 0x83fd9014 0x0400800c |
||||
DATA 4 0x83fd9014 0x0000801e |
||||
DATA 4 0x83fd9014 0x0000801f |
||||
DATA 4 0x83fd9014 0x0000801d |
||||
DATA 4 0x83fd9014 0x0732801c |
||||
DATA 4 0x83fd9014 0x0400800c |
||||
DATA 4 0x83fd9014 0x00008014 |
||||
DATA 4 0x83fd9014 0x00008014 |
||||
DATA 4 0x83fd9014 0x0632801c |
||||
DATA 4 0x83fd9014 0x0380801d |
||||
DATA 4 0x83fd9014 0x0040801d |
||||
DATA 4 0x83fd9014 0x00008004 |
||||
|
||||
# Write to CTL0 |
||||
DATA 4 0x83fd9000 0xb2a20000 |
||||
# Write to CTL1 |
||||
DATA 4 0x83fd9008 0xb2a20000 |
||||
# ESDMISC |
||||
DATA 4 0x83fd9010 0x000ad6d0 |
||||
#ESDCTL_ESDCDLYGD |
||||
DATA 4 0x83fd9034 0x90000000 |
||||
DATA 4 0x83fd9014 0x00000000 |
@ -0,0 +1,49 @@ |
||||
#
|
||||
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
|
||||
#
|
||||
# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := mx35pdk.o
|
||||
SOBJS := lowlevel_init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
||||
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
@ -0,0 +1,363 @@ |
||||
/* |
||||
* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
|
||||
* |
||||
* (C) Copyright 2008-2010 Freescale Semiconductor, Inc. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <asm/arch/imx-regs.h> |
||||
#include <asm/arch/asm-offsets.h> |
||||
#include "mx35pdk.h" |
||||
|
||||
/* |
||||
* return soc version |
||||
* 0x10: TO1 |
||||
* 0x20: TO2 |
||||
* 0x30: TO3 |
||||
*/ |
||||
.macro check_soc_version ret, tmp |
||||
ldr \tmp, =IIM_BASE_ADDR |
||||
ldr \ret, [\tmp, #IIM_SREV] |
||||
cmp \ret, #0x00 |
||||
moveq \tmp, #ROMPATCH_REV |
||||
ldreq \ret, [\tmp] |
||||
moveq \ret, \ret, lsl #4 |
||||
addne \ret, \ret, #0x10 |
||||
.endm |
||||
|
||||
/* |
||||
* AIPS setup - Only setup MPROTx registers. |
||||
* The PACR default values are good. |
||||
*/ |
||||
.macro init_aips
|
||||
/* |
||||
* Set all MPROTx to be non-bufferable, trusted for R/W, |
||||
* not forced to user-mode. |
||||
*/ |
||||
ldr r0, =AIPS1_BASE_ADDR |
||||
ldr r1, =AIPS_MPR_CONFIG |
||||
str r1, [r0, #0x00] |
||||
str r1, [r0, #0x04] |
||||
ldr r0, =AIPS2_BASE_ADDR |
||||
str r1, [r0, #0x00] |
||||
str r1, [r0, #0x04] |
||||
|
||||
/* |
||||
* Clear the on and off peripheral modules Supervisor Protect bit |
||||
* for SDMA to access them. Did not change the AIPS control registers |
||||
* (offset 0x20) access type |
||||
*/ |
||||
ldr r0, =AIPS1_BASE_ADDR |
||||
ldr r1, =AIPS_OPACR_CONFIG |
||||
str r1, [r0, #0x40] |
||||
str r1, [r0, #0x44] |
||||
str r1, [r0, #0x48] |
||||
str r1, [r0, #0x4C] |
||||
str r1, [r0, #0x50] |
||||
ldr r0, =AIPS2_BASE_ADDR |
||||
str r1, [r0, #0x40] |
||||
str r1, [r0, #0x44] |
||||
str r1, [r0, #0x48] |
||||
str r1, [r0, #0x4C] |
||||
str r1, [r0, #0x50] |
||||
.endm |
||||
|
||||
/* MAX (Multi-Layer AHB Crossbar Switch) setup */ |
||||
.macro init_max
|
||||
ldr r0, =MAX_BASE_ADDR |
||||
/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ |
||||
ldr r1, =MAX_MPR_CONFIG |
||||
str r1, [r0, #0x000] /* for S0 */ |
||||
str r1, [r0, #0x100] /* for S1 */ |
||||
str r1, [r0, #0x200] /* for S2 */ |
||||
str r1, [r0, #0x300] /* for S3 */ |
||||
str r1, [r0, #0x400] /* for S4 */ |
||||
/* SGPCR - always park on last master */ |
||||
ldr r1, =MAX_SGPCR_CONFIG |
||||
str r1, [r0, #0x010] /* for S0 */ |
||||
str r1, [r0, #0x110] /* for S1 */ |
||||
str r1, [r0, #0x210] /* for S2 */ |
||||
str r1, [r0, #0x310] /* for S3 */ |
||||
str r1, [r0, #0x410] /* for S4 */ |
||||
/* MGPCR - restore default values */ |
||||
ldr r1, =MAX_MGPCR_CONFIG |
||||
str r1, [r0, #0x800] /* for M0 */ |
||||
str r1, [r0, #0x900] /* for M1 */ |
||||
str r1, [r0, #0xA00] /* for M2 */ |
||||
str r1, [r0, #0xB00] /* for M3 */ |
||||
str r1, [r0, #0xC00] /* for M4 */ |
||||
str r1, [r0, #0xD00] /* for M5 */ |
||||
.endm |
||||
|
||||
/* M3IF setup */ |
||||
.macro init_m3if
|
||||
/* Configure M3IF registers */ |
||||
ldr r1, =M3IF_BASE_ADDR |
||||
/* |
||||
* M3IF Control Register (M3IFCTL) |
||||
* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 |
||||
* MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 |
||||
* MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 |
||||
* MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 |
||||
* MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 |
||||
* MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 |
||||
* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 |
||||
* MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 |
||||
* ------------ |
||||
* 0x00000040 |
||||
*/ |
||||
ldr r0, =M3IF_CONFIG |
||||
str r0, [r1] /* M3IF control reg */ |
||||
.endm |
||||
|
||||
/* CPLD on CS5 setup */ |
||||
.macro init_debug_board
|
||||
ldr r0, =DBG_BASE_ADDR |
||||
ldr r1, =DBG_CSCR_U_CONFIG |
||||
str r1, [r0, #0x00] |
||||
ldr r1, =DBG_CSCR_L_CONFIG |
||||
str r1, [r0, #0x04] |
||||
ldr r1, =DBG_CSCR_A_CONFIG |
||||
str r1, [r0, #0x08] |
||||
.endm |
||||
|
||||
/* clock setup */ |
||||
.macro init_clock
|
||||
ldr r0, =CCM_BASE_ADDR |
||||
|
||||
/* default CLKO to 1/32 of the ARM core*/ |
||||
ldr r1, [r0, #CLKCTL_COSR] |
||||
bic r1, r1, #0x00000FF00 |
||||
bic r1, r1, #0x0000000FF |
||||
mov r2, #0x00006C00 |
||||
add r2, r2, #0x67 |
||||
orr r1, r1, r2 |
||||
str r1, [r0, #CLKCTL_COSR] |
||||
|
||||
ldr r2, =CCM_CCMR_CONFIG |
||||
str r2, [r0, #CLKCTL_CCMR] |
||||
|
||||
check_soc_version r1, r2 |
||||
cmp r1, #CHIP_REV_2_0 |
||||
ldrhs r3, =CCM_MPLL_532_HZ |
||||
bhs 1f |
||||
ldr r2, [r0, #CLKCTL_PDR0] |
||||
tst r2, #CLKMODE_CONSUMER |
||||
ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/ |
||||
ldreq r3, =CCM_MPLL_399_HZ /* auto path*/ |
||||
1: |
||||
str r3, [r0, #CLKCTL_MPCTL] |
||||
|
||||
ldr r1, =CCM_PPLL_300_HZ |
||||
str r1, [r0, #CLKCTL_PPCTL] |
||||
|
||||
ldr r1, =CCM_PDR0_CONFIG |
||||
bic r1, r1, #0x800000 |
||||
str r1, [r0, #CLKCTL_PDR0] |
||||
|
||||
ldr r1, [r0, #CLKCTL_CGR0] |
||||
orr r1, r1, #0x0C300000 |
||||
str r1, [r0, #CLKCTL_CGR0] |
||||
|
||||
ldr r1, [r0, #CLKCTL_CGR1] |
||||
orr r1, r1, #0x00000C00 |
||||
orr r1, r1, #0x00000003 |
||||
str r1, [r0, #CLKCTL_CGR1] |
||||
.endm |
||||
|
||||
.macro setup_sdram
|
||||
ldr r0, =ESDCTL_BASE_ADDR |
||||
mov r3, #0x2000 |
||||
str r3, [r0, #0x0] |
||||
str r3, [r0, #0x8] |
||||
|
||||
/*ip(r12) has used to save lr register in upper calling*/ |
||||
mov fp, lr |
||||
|
||||
mov r5, #0x00 |
||||
mov r2, #0x00 |
||||
mov r1, #CSD0_BASE_ADDR |
||||
bl setup_sdram_bank |
||||
cmp r3, #0x0 |
||||
orreq r5, r5, #1 |
||||
eorne r2, r2, #0x1 |
||||
blne setup_sdram_bank |
||||
|
||||
mov lr, fp |
||||
|
||||
1: |
||||
ldr r3, =ESDCTL_DELAY_LINE5 |
||||
str r3, [r0, #0x30] |
||||
.endm |
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init: |
||||
mov r10, lr |
||||
|
||||
mrc 15, 0, r1, c1, c0, 0 |
||||
|
||||
mrc 15, 0, r0, c1, c0, 1 |
||||
orr r0, r0, #7 |
||||
mcr 15, 0, r0, c1, c0, 1 |
||||
orr r1, r1, #(1<<11) |
||||
|
||||
/* Set unaligned access enable */ |
||||
orr r1, r1, #(1<<22) |
||||
|
||||
/* Set low int latency enable */ |
||||
orr r1, r1, #(1<<21) |
||||
|
||||
mcr 15, 0, r1, c1, c0, 0 |
||||
|
||||
mov r0, #0 |
||||
|
||||
/* Set branch prediction enable */ |
||||
mcr 15, 0, r0, c15, c2, 4 |
||||
|
||||
mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ |
||||
mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */ |
||||
mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */ |
||||
|
||||
/* |
||||
* initializes very early AIPS |
||||
* Then it also initializes Multi-Layer AHB Crossbar Switch, |
||||
* M3IF |
||||
* Also setup the Peripheral Port Remap register inside the core |
||||
*/ |
||||
ldr r0, =0x40000015 /* start from AIPS 2GB region */ |
||||
mcr p15, 0, r0, c15, c2, 4 |
||||
|
||||
init_aips |
||||
|
||||
init_max |
||||
|
||||
init_m3if |
||||
|
||||
init_clock |
||||
init_debug_board |
||||
|
||||
cmp pc, #PHYS_SDRAM_1 |
||||
blo init_sdram_start |
||||
cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) |
||||
blo skip_sdram_setup |
||||
|
||||
init_sdram_start: |
||||
/*init_sdram*/ |
||||
setup_sdram |
||||
|
||||
skip_sdram_setup: |
||||
mov lr, r10 |
||||
mov pc, lr |
||||
|
||||
|
||||
/* |
||||
* r0: ESDCTL control base, r1: sdram slot base |
||||
* r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base |
||||
*/ |
||||
setup_sdram_bank: |
||||
mov r3, #0xE |
||||
tst r2, #0x1 |
||||
orreq r3, r3, #0x300 /*DDR2*/ |
||||
str r3, [r0, #0x10] |
||||
bic r3, r3, #0x00A |
||||
str r3, [r0, #0x10] |
||||
beq 2f |
||||
|
||||
mov r3, #0x20000 |
||||
1: subs r3, r3, #1 |
||||
bne 1b |
||||
|
||||
2: tst r2, #0x1 |
||||
ldreq r3, =ESDCTL_DDR2_CONFIG |
||||
ldrne r3, =ESDCTL_MDDR_CONFIG |
||||
cmp r1, #CSD1_BASE_ADDR |
||||
strlo r3, [r0, #0x4] |
||||
strhs r3, [r0, #0xC] |
||||
|
||||
ldr r3, =ESDCTL_0x92220000 |
||||
strlo r3, [r0, #0x0] |
||||
strhs r3, [r0, #0x8] |
||||
mov r3, #0xDA |
||||
ldr r4, =ESDCTL_PRECHARGE |
||||
strb r3, [r1, r4] |
||||
|
||||
tst r2, #0x1 |
||||
bne skip_set_mode |
||||
|
||||
cmp r1, #CSD1_BASE_ADDR |
||||
ldr r3, =ESDCTL_0xB2220000 |
||||
strlo r3, [r0, #0x0] |
||||
strhs r3, [r0, #0x8] |
||||
mov r3, #0xDA |
||||
ldr r4, =ESDCTL_DDR2_EMR2 |
||||
strb r3, [r1, r4] |
||||
ldr r4, =ESDCTL_DDR2_EMR3 |
||||
strb r3, [r1, r4] |
||||
ldr r4, =ESDCTL_DDR2_EN_DLL |
||||
strb r3, [r1, r4] |
||||
ldr r4, =ESDCTL_DDR2_RESET_DLL |
||||
strb r3, [r1, r4] |
||||
|
||||
ldr r3, =ESDCTL_0x92220000 |
||||
strlo r3, [r0, #0x0] |
||||
strhs r3, [r0, #0x8] |
||||
mov r3, #0xDA |
||||
ldr r4, =ESDCTL_PRECHARGE |
||||
strb r3, [r1, r4] |
||||
|
||||
skip_set_mode: |
||||
cmp r1, #CSD1_BASE_ADDR |
||||
ldr r3, =ESDCTL_0xA2220000 |
||||
strlo r3, [r0, #0x0] |
||||
strhs r3, [r0, #0x8] |
||||
mov r3, #0xDA |
||||
strb r3, [r1] |
||||
strb r3, [r1] |
||||
|
||||
ldr r3, =ESDCTL_0xB2220000 |
||||
strlo r3, [r0, #0x0] |
||||
strhs r3, [r0, #0x8] |
||||
tst r2, #0x1 |
||||
ldreq r4, =ESDCTL_DDR2_MR |
||||
ldrne r4, =ESDCTL_MDDR_MR |
||||
mov r3, #0xDA |
||||
strb r3, [r1, r4] |
||||
ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT |
||||
streqb r3, [r1, r4] |
||||
ldreq r4, =ESDCTL_DDR2_EN_DLL |
||||
ldrne r4, =ESDCTL_MDDR_EMR |
||||
strb r3, [r1, r4] |
||||
|
||||
cmp r1, #CSD1_BASE_ADDR |
||||
ldr r3, =ESDCTL_0x82228080 |
||||
strlo r3, [r0, #0x0] |
||||
strhs r3, [r0, #0x8] |
||||
|
||||
tst r2, #0x1 |
||||
moveq r4, #0x20000 |
||||
movne r4, #0x200 |
||||
1: subs r4, r4, #1 |
||||
bne 1b |
||||
|
||||
str r3, [r1, #0x100] |
||||
ldr r4, [r1, #0x100] |
||||
cmp r3, r4 |
||||
movne r3, #1 |
||||
moveq r3, #0 |
||||
|
||||
mov pc, lr |
@ -0,0 +1,297 @@ |
||||
/*
|
||||
* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> |
||||
* |
||||
* (C) Copyright 2008-2010 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/errno.h> |
||||
#include <asm/arch/imx-regs.h> |
||||
#include <asm/arch/crm_regs.h> |
||||
#include <asm/arch/mx35_pins.h> |
||||
#include <asm/arch/iomux.h> |
||||
#include <i2c.h> |
||||
#include <fsl_pmic.h> |
||||
#include <mc9sdz60.h> |
||||
#include <mc13892.h> |
||||
#include <linux/types.h> |
||||
#include <mxc_gpio.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <netdev.h> |
||||
|
||||
#ifndef BOARD_LATE_INIT |
||||
#error "BOARD_LATE_INIT must be set for this board" |
||||
#endif |
||||
|
||||
#ifndef CONFIG_BOARD_EARLY_INIT_F |
||||
#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board" |
||||
#endif |
||||
|
||||
#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); }) |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, |
||||
PHYS_SDRAM_1_SIZE); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void setup_iomux_i2c(void) |
||||
{ |
||||
int pad; |
||||
|
||||
/* setup pins for I2C1 */ |
||||
mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION); |
||||
mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION); |
||||
|
||||
pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
|
||||
| PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain); |
||||
|
||||
mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad); |
||||
mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad); |
||||
} |
||||
|
||||
|
||||
static void setup_iomux_spi(void) |
||||
{ |
||||
mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION); |
||||
mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION); |
||||
mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION); |
||||
mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION); |
||||
mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION); |
||||
} |
||||
|
||||
static void setup_iomux_fec(void) |
||||
{ |
||||
int pad; |
||||
|
||||
/* setup pins for FEC */ |
||||
mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC); |
||||
mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC); |
||||
mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC); |
||||
mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC); |
||||
mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC); |
||||
mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC); |
||||
mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC); |
||||
mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC); |
||||
mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC); |
||||
mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC); |
||||
mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC); |
||||
mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC); |
||||
mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC); |
||||
mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC); |
||||
mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC); |
||||
mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC); |
||||
mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC); |
||||
mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC); |
||||
|
||||
pad = (PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD | PAD_CTL_ODE_CMOS | \
|
||||
PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW); |
||||
|
||||
mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); |
||||
mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); |
||||
mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, pad | PAD_CTL_HYS_SCHMITZ | \
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); |
||||
mxc_iomux_set_pad(MX35_PIN_FEC_COL, pad | PAD_CTL_HYS_SCHMITZ | \
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); |
||||
mxc_iomux_set_pad(MX35_PIN_FEC_RDATA0, pad | PAD_CTL_HYS_SCHMITZ | \
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); |
||||
mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0, pad | PAD_CTL_HYS_CMOS | \
|
||||
PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); |
||||
mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, pad | PAD_CTL_HYS_CMOS | \
|
||||
PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); |
||||
mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad | PAD_CTL_HYS_CMOS | \
|
||||
PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); |
||||
mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad | PAD_CTL_HYS_SCHMITZ | \
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU); |
||||
mxc_iomux_set_pad(MX35_PIN_FEC_TX_ERR, pad | PAD_CTL_HYS_CMOS | \
|
||||
PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); |
||||
mxc_iomux_set_pad(MX35_PIN_FEC_RX_ERR, pad | PAD_CTL_HYS_SCHMITZ | \
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); |
||||
mxc_iomux_set_pad(MX35_PIN_FEC_CRS, pad | PAD_CTL_HYS_SCHMITZ | \
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); |
||||
mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1, pad | PAD_CTL_HYS_SCHMITZ | \
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); |
||||
mxc_iomux_set_pad(MX35_PIN_FEC_TDATA1, pad | PAD_CTL_HYS_CMOS | \
|
||||
PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); |
||||
mxc_iomux_set_pad(MX35_PIN_FEC_RDATA2, pad | PAD_CTL_HYS_SCHMITZ | \
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); |
||||
mxc_iomux_set_pad(MX35_PIN_FEC_TDATA2, pad | PAD_CTL_HYS_CMOS | \
|
||||
PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); |
||||
mxc_iomux_set_pad(MX35_PIN_FEC_RDATA3, pad | PAD_CTL_HYS_SCHMITZ | \
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD); |
||||
mxc_iomux_set_pad(MX35_PIN_FEC_TDATA3, pad | PAD_CTL_HYS_CMOS | \
|
||||
PAD_CTL_PKE_NONE | PAD_CTL_100K_PD); |
||||
} |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
struct ccm_regs *ccm = |
||||
(struct ccm_regs *)IMX_CCM_BASE; |
||||
|
||||
/* enable clocks */ |
||||
writel(readl(&ccm->cgr0) | |
||||
MXC_CCM_CGR0_EMI_MASK | |
||||
MXC_CCM_CGR0_EDI0_MASK | |
||||
MXC_CCM_CGR0_EPIT1_MASK, |
||||
&ccm->cgr0); |
||||
|
||||
writel(readl(&ccm->cgr1) | |
||||
MXC_CCM_CGR1_FEC_MASK | |
||||
MXC_CCM_CGR1_GPIO1_MASK | |
||||
MXC_CCM_CGR1_GPIO2_MASK | |
||||
MXC_CCM_CGR1_GPIO3_MASK | |
||||
MXC_CCM_CGR1_I2C1_MASK | |
||||
MXC_CCM_CGR1_I2C2_MASK | |
||||
MXC_CCM_CGR1_IPU_MASK, |
||||
&ccm->cgr1); |
||||
|
||||
/* Setup NAND */ |
||||
__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); |
||||
|
||||
setup_iomux_i2c(); |
||||
setup_iomux_fec(); |
||||
setup_iomux_spi(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */ |
||||
/* address of boot parameters */ |
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static inline int pmic_detect(void) |
||||
{ |
||||
int id; |
||||
|
||||
id = pmic_reg_read(REG_IDENTIFICATION); |
||||
|
||||
id = (id >> 6) & 0x7; |
||||
if (id == 0x7) |
||||
return 1; |
||||
return 0; |
||||
} |
||||
|
||||
u32 get_board_rev(void) |
||||
{ |
||||
int rev; |
||||
|
||||
rev = pmic_detect(); |
||||
|
||||
return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; |
||||
} |
||||
|
||||
int board_late_init(void) |
||||
{ |
||||
u8 val; |
||||
u32 pmic_val; |
||||
|
||||
if (pmic_detect()) { |
||||
mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION | |
||||
MUX_CONFIG_ALT1); |
||||
|
||||
pmic_val = pmic_reg_read(REG_SETTING_0); |
||||
pmic_reg_write(REG_SETTING_0, pmic_val | VO_1_30V | VO_1_50V); |
||||
pmic_val = pmic_reg_read(REG_MODE_0); |
||||
pmic_reg_write(REG_MODE_0, pmic_val | VGEN3EN); |
||||
|
||||
mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO); |
||||
mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0); |
||||
|
||||
mxc_gpio_direction(37, MXC_GPIO_DIRECTION_OUT); |
||||
mxc_gpio_set(37, 1); |
||||
} |
||||
|
||||
val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04; |
||||
mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val); |
||||
mdelay(200); |
||||
|
||||
val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F; |
||||
mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val); |
||||
mdelay(200); |
||||
|
||||
val |= 0x80; |
||||
mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
struct ccm_regs *ccm = |
||||
(struct ccm_regs *)IMX_CCM_BASE; |
||||
u32 cpu_rev = get_cpu_rev(); |
||||
|
||||
/*
|
||||
* Be sure that I2C is initialized to check |
||||
* the board revision |
||||
*/ |
||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
||||
|
||||
/* Print board revision */ |
||||
printf("Board: MX35 PDK %d.0 ", ((get_board_rev() >> 8) + 1) & 0x0F); |
||||
|
||||
/* Print CPU revision */ |
||||
printf("i.MX35 %d.%d [", (cpu_rev & 0xF0) >> 4, cpu_rev & 0x0F); |
||||
|
||||
switch (readl(&ccm->rcsr) & 0x0F) { |
||||
case 0x0000: |
||||
puts("POR"); |
||||
break; |
||||
case 0x0002: |
||||
puts("JTAG"); |
||||
break; |
||||
case 0x0004: |
||||
puts("RST"); |
||||
break; |
||||
case 0x0008: |
||||
puts("WDT"); |
||||
break; |
||||
default: |
||||
puts("unknown"); |
||||
} |
||||
puts("]\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
int rc = -ENODEV; |
||||
#if defined(CONFIG_SMC911X) |
||||
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); |
||||
#endif |
||||
|
||||
cpu_eth_init(bis); |
||||
|
||||
return rc; |
||||
} |
@ -0,0 +1,101 @@ |
||||
/*
|
||||
* |
||||
* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> |
||||
* |
||||
* (C) Copyright 2008-2009 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __BOARD_MX35_3STACK_H |
||||
#define __BOARD_MX35_3STACK_H |
||||
|
||||
#define AIPS_MPR_CONFIG 0x77777777 |
||||
#define AIPS_OPACR_CONFIG 0x00000000 |
||||
|
||||
/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ |
||||
#define MAX_MPR_CONFIG 0x00302154 |
||||
/* SGPCR - always park on last master */ |
||||
#define MAX_SGPCR_CONFIG 0x00000010 |
||||
/* MGPCR - restore default values */ |
||||
#define MAX_MGPCR_CONFIG 0x00000000 |
||||
|
||||
/*
|
||||
* M3IF Control Register (M3IFCTL) |
||||
* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 |
||||
* MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 |
||||
* MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 |
||||
* MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 |
||||
* MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 |
||||
* MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 |
||||
* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 |
||||
* MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 |
||||
* ------------ |
||||
* 0x00000040 |
||||
*/ |
||||
#define M3IF_CONFIG 0x00000040 |
||||
|
||||
#define DBG_BASE_ADDR WEIM_CTRL_CS5 |
||||
#define DBG_CSCR_U_CONFIG 0x0000D843 |
||||
#define DBG_CSCR_L_CONFIG 0x22252521 |
||||
#define DBG_CSCR_A_CONFIG 0x22220A00 |
||||
|
||||
#define CCM_CCMR_CONFIG 0x003F4208 |
||||
#define CCM_PDR0_CONFIG 0x00801000 |
||||
|
||||
#define PLL_BRM_OFFSET 31 |
||||
#define PLL_PD_OFFSET 26 |
||||
#define PLL_MFD_OFFSET 16 |
||||
#define PLL_MFI_OFFSET 10 |
||||
|
||||
#define _PLL_BRM(x) ((x) << PLL_BRM_OFFSET) |
||||
#define _PLL_PD(x) (((x) - 1) << PLL_PD_OFFSET) |
||||
#define _PLL_MFD(x) (((x) - 1) << PLL_MFD_OFFSET) |
||||
#define _PLL_MFI(x) ((x) << PLL_MFI_OFFSET) |
||||
#define _PLL_MFN(x) (x) |
||||
#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \ |
||||
(_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
|
||||
_PLL_MFN(mfn)) |
||||
|
||||
#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1) |
||||
#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5) |
||||
#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1) |
||||
|
||||
/* MEMORY SETTING */ |
||||
#define ESDCTL_0x92220000 0x92220000 |
||||
#define ESDCTL_0xA2220000 0xA2220000 |
||||
#define ESDCTL_0xB2220000 0xB2220000 |
||||
#define ESDCTL_0x82228080 0x82228080 |
||||
|
||||
#define ESDCTL_PRECHARGE 0x00000400 |
||||
|
||||
#define ESDCTL_MDDR_CONFIG 0x007FFC3F |
||||
#define ESDCTL_MDDR_MR 0x00000033 |
||||
#define ESDCTL_MDDR_EMR 0x02000000 |
||||
|
||||
#define ESDCTL_DDR2_CONFIG 0x007FFC3F |
||||
#define ESDCTL_DDR2_EMR2 0x04000000 |
||||
#define ESDCTL_DDR2_EMR3 0x06000000 |
||||
#define ESDCTL_DDR2_EN_DLL 0x02000400 |
||||
#define ESDCTL_DDR2_RESET_DLL 0x00000333 |
||||
#define ESDCTL_DDR2_MR 0x00000233 |
||||
#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780 |
||||
|
||||
#define ESDCTL_DELAY_LINE5 0x00F49F00 |
||||
#endif /* __BOARD_MX35_3STACK_H */ |
@ -0,0 +1,48 @@ |
||||
#
|
||||
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
|
||||
#
|
||||
# (C) Copyright 2010 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := mx53evk.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
||||
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
@ -0,0 +1,24 @@ |
||||
#
|
||||
# Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg
|
||||
ALL += $(obj)u-boot.imx
|
@ -0,0 +1,112 @@ |
||||
# |
||||
# (C Copyright 2009 |
||||
# Stefano Babic DENX Software Engineering sbabic@denx.de. |
||||
# |
||||
# See file CREDITS for list of people who contributed to this |
||||
# project. |
||||
# |
||||
# This program is free software; you can redistribute it and/or |
||||
# modify it under the terms of the GNU General Public License as |
||||
# published by the Free Software Foundation; either version 2 of |
||||
# the License or (at your option) any later version. |
||||
# |
||||
# This program is distributed in the hope that it will be useful, |
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
# GNU General Public License for more details. |
||||
# |
||||
# You should have received a copy of the GNU General Public License |
||||
# along with this program; if not write to the Free Software |
||||
# Foundation Inc. 51 Franklin Street Fifth Floor Boston, |
||||
# MA 02110-1301 USA |
||||
# |
||||
# Refer docs/README.imxmage for more details about how-to configure |
||||
# and create imximage boot image |
||||
# |
||||
# The syntax is taken as close as possible with the kwbimage |
||||
|
||||
# image version |
||||
|
||||
IMAGE_VERSION 2 |
||||
|
||||
# Boot Device : one of |
||||
# spi, sd (the board has no nand neither onenand) |
||||
|
||||
BOOT_FROM sd |
||||
|
||||
# Device Configuration Data (DCD) |
||||
# |
||||
# Each entry must have the format: |
||||
# Addr-type Address Value |
||||
# |
||||
# where: |
||||
# Addr-type register length (1,2 or 4 bytes) |
||||
# Address absolute address of the register |
||||
# value value to be stored in the register |
||||
|
||||
# Setting IOMUXC |
||||
DATA 4 0x53fa8554 0x00200000 |
||||
DATA 4 0x53fa8560 0x00200000 |
||||
DATA 4 0x53fa8594 0x00200000 |
||||
DATA 4 0x53fa8584 0x00200000 |
||||
DATA 4 0x53fa8558 0x00200040 |
||||
DATA 4 0x53fa8568 0x00200040 |
||||
DATA 4 0x53fa8590 0x00200040 |
||||
DATA 4 0x53fa857c 0x00200040 |
||||
DATA 4 0x53fa8564 0x00200040 |
||||
DATA 4 0x53fa8580 0x00200040 |
||||
DATA 4 0x53fa8570 0x00200000 |
||||
DATA 4 0x53fa8578 0x00200000 |
||||
DATA 4 0x53fa872c 0x00200000 |
||||
DATA 4 0x53fa8728 0x00200000 |
||||
DATA 4 0x53fa871c 0x00200000 |
||||
DATA 4 0x53fa8718 0x00200000 |
||||
DATA 4 0x53fa8574 0x00280000 |
||||
DATA 4 0x53fa8588 0x00280000 |
||||
DATA 4 0x53fa86f0 0x00280000 |
||||
DATA 4 0x53fa8720 0x00280000 |
||||
DATA 4 0x53fa86fc 0x00000000 |
||||
DATA 4 0x53fa86f4 0x00000200 |
||||
DATA 4 0x53fa8714 0x00000000 |
||||
DATA 4 0x53fa8724 0x06000000 |
||||
DATA 4 0x63fd9088 0x34333936 |
||||
DATA 4 0x63fd9090 0x49434942 |
||||
DATA 4 0x63fd90F8 0x00000800 |
||||
DATA 4 0x63fd907c 0x01350138 |
||||
DATA 4 0x63fd9080 0x01380139 |
||||
DATA 4 0x63fd9018 0x00001710 |
||||
DATA 4 0x63fd9000 0xc4110000 |
||||
DATA 4 0x63fd900C 0x4d5122d2 |
||||
DATA 4 0x63fd9010 0x92d18a22 |
||||
DATA 4 0x63fd9014 0x00c70092 |
||||
DATA 4 0x63fd902c 0x000026d2 |
||||
DATA 4 0x63fd9030 0x009f000e |
||||
DATA 4 0x63fd9008 0x12272000 |
||||
DATA 4 0x63fd9004 0x00030012 |
||||
DATA 4 0x63fd901c 0x04008010 |
||||
DATA 4 0x63fd901c 0x00008032 |
||||
DATA 4 0x63fd901c 0x00008033 |
||||
DATA 4 0x63fd901c 0x00008031 |
||||
DATA 4 0x63fd901c 0x0b5280b0 |
||||
DATA 4 0x63fd901c 0x04008010 |
||||
DATA 4 0x63fd901c 0x00008020 |
||||
DATA 4 0x63fd901c 0x00008020 |
||||
DATA 4 0x63fd901c 0x0a528030 |
||||
DATA 4 0x63fd901c 0x03c68031 |
||||
DATA 4 0x63fd901c 0x00448031 |
||||
DATA 4 0x63fd901c 0x04008018 |
||||
DATA 4 0x63fd901c 0x0000803a |
||||
DATA 4 0x63fd901c 0x0000803b |
||||
DATA 4 0x63fd901c 0x00008039 |
||||
DATA 4 0x63fd901c 0x0b528138 |
||||
DATA 4 0x63fd901c 0x04008018 |
||||
DATA 4 0x63fd901c 0x00008028 |
||||
DATA 4 0x63fd901c 0x00008028 |
||||
DATA 4 0x63fd901c 0x0a528038 |
||||
DATA 4 0x63fd901c 0x03c68039 |
||||
DATA 4 0x63fd901c 0x00448039 |
||||
DATA 4 0x63fd9020 0x00005800 |
||||
DATA 4 0x63fd9058 0x00033335 |
||||
DATA 4 0x63fd901c 0x00000000 |
||||
DATA 4 0x63fd9040 0x04b80003 |
||||
DATA 4 0x53fa8004 0x00194005 |
@ -0,0 +1,397 @@ |
||||
/*
|
||||
* (C) Copyright 2010 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/imx-regs.h> |
||||
#include <asm/arch/mx5x_pins.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/arch/crm_regs.h> |
||||
#include <asm/arch/iomux.h> |
||||
#include <asm/errno.h> |
||||
#include <netdev.h> |
||||
#include <i2c.h> |
||||
#include <mmc.h> |
||||
#include <fsl_esdhc.h> |
||||
#include <fsl_pmic.h> |
||||
#include <mxc_gpio.h> |
||||
#include <mc13892.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
u32 get_board_rev(void) |
||||
{ |
||||
return get_cpu_rev(); |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
/* dram_init must store complete ramsize in gd->ram_size */ |
||||
gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, |
||||
PHYS_SDRAM_1_SIZE); |
||||
return 0; |
||||
} |
||||
|
||||
static void setup_iomux_uart(void) |
||||
{ |
||||
/* UART1 RXD */ |
||||
mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2); |
||||
mxc_iomux_set_pad(MX53_PIN_CSI0_D11, |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | |
||||
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | |
||||
PAD_CTL_ODE_OPENDRAIN_ENABLE); |
||||
mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1); |
||||
|
||||
/* UART1 TXD */ |
||||
mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2); |
||||
mxc_iomux_set_pad(MX53_PIN_CSI0_D10, |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | |
||||
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | |
||||
PAD_CTL_ODE_OPENDRAIN_ENABLE); |
||||
} |
||||
|
||||
static void setup_i2c(unsigned int port_number) |
||||
{ |
||||
switch (port_number) { |
||||
case 0: |
||||
/* i2c1 SDA */ |
||||
mxc_request_iomux(MX53_PIN_CSI0_D8, |
||||
IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); |
||||
mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT, |
||||
INPUT_CTL_PATH0); |
||||
mxc_iomux_set_pad(MX53_PIN_CSI0_D8, |
||||
PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | |
||||
PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | |
||||
PAD_CTL_ODE_OPENDRAIN_ENABLE); |
||||
/* i2c1 SCL */ |
||||
mxc_request_iomux(MX53_PIN_CSI0_D9, |
||||
IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); |
||||
mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT, |
||||
INPUT_CTL_PATH0); |
||||
mxc_iomux_set_pad(MX53_PIN_CSI0_D9, |
||||
PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | |
||||
PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | |
||||
PAD_CTL_ODE_OPENDRAIN_ENABLE); |
||||
break; |
||||
case 1: |
||||
/* i2c2 SDA */ |
||||
mxc_request_iomux(MX53_PIN_KEY_ROW3, |
||||
IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); |
||||
mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT, |
||||
INPUT_CTL_PATH0); |
||||
mxc_iomux_set_pad(MX53_PIN_KEY_ROW3, |
||||
PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | |
||||
PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | |
||||
PAD_CTL_ODE_OPENDRAIN_ENABLE); |
||||
|
||||
/* i2c2 SCL */ |
||||
mxc_request_iomux(MX53_PIN_KEY_COL3, |
||||
IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); |
||||
mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT, |
||||
INPUT_CTL_PATH0); |
||||
mxc_iomux_set_pad(MX53_PIN_KEY_COL3, |
||||
PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | |
||||
PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | |
||||
PAD_CTL_ODE_OPENDRAIN_ENABLE); |
||||
break; |
||||
default: |
||||
printf("Warning: Wrong I2C port number\n"); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
void power_init(void) |
||||
{ |
||||
unsigned int val; |
||||
|
||||
/* Set VDDA to 1.25V */ |
||||
val = pmic_reg_read(REG_SW_2); |
||||
val &= ~SWX_OUT_MASK; |
||||
val |= SWX_OUT_1_25; |
||||
pmic_reg_write(REG_SW_2, val); |
||||
|
||||
/*
|
||||
* Need increase VCC and VDDA to 1.3V |
||||
* according to MX53 IC TO2 datasheet. |
||||
*/ |
||||
if (is_soc_rev(CHIP_REV_2_0) == 0) { |
||||
/* Set VCC to 1.3V for TO2 */ |
||||
val = pmic_reg_read(REG_SW_1); |
||||
val &= ~SWX_OUT_MASK; |
||||
val |= SWX_OUT_1_30; |
||||
pmic_reg_write(REG_SW_1, val); |
||||
|
||||
/* Set VDDA to 1.3V for TO2 */ |
||||
val = pmic_reg_read(REG_SW_2); |
||||
val &= ~SWX_OUT_MASK; |
||||
val |= SWX_OUT_1_30; |
||||
pmic_reg_write(REG_SW_2, val); |
||||
} |
||||
} |
||||
|
||||
static void setup_iomux_fec(void) |
||||
{ |
||||
/*FEC_MDIO*/ |
||||
mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | |
||||
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | |
||||
PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE); |
||||
mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1); |
||||
|
||||
/*FEC_MDC*/ |
||||
mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH); |
||||
|
||||
/* FEC RXD1 */ |
||||
mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); |
||||
|
||||
/* FEC RXD0 */ |
||||
mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); |
||||
|
||||
/* FEC TXD1 */ |
||||
mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH); |
||||
|
||||
/* FEC TXD0 */ |
||||
mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH); |
||||
|
||||
/* FEC TX_EN */ |
||||
mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH); |
||||
|
||||
/* FEC TX_CLK */ |
||||
mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); |
||||
|
||||
/* FEC RX_ER */ |
||||
mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); |
||||
|
||||
/* FEC CRS */ |
||||
mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0); |
||||
mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); |
||||
} |
||||
|
||||
#ifdef CONFIG_FSL_ESDHC |
||||
struct fsl_esdhc_cfg esdhc_cfg[2] = { |
||||
{MMC_SDHC1_BASE_ADDR, 1}, |
||||
{MMC_SDHC3_BASE_ADDR, 1}, |
||||
}; |
||||
|
||||
int board_mmc_getcd(u8 *cd, struct mmc *mmc) |
||||
{ |
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
||||
|
||||
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) |
||||
*cd = mxc_gpio_get(77); /*GPIO3_13*/ |
||||
else |
||||
*cd = mxc_gpio_get(75); /*GPIO3_11*/ |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_mmc_init(bd_t *bis) |
||||
{ |
||||
u32 index; |
||||
s32 status = 0; |
||||
|
||||
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { |
||||
switch (index) { |
||||
case 0: |
||||
mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); |
||||
mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); |
||||
mxc_request_iomux(MX53_PIN_SD1_DATA0, |
||||
IOMUX_CONFIG_ALT0); |
||||
mxc_request_iomux(MX53_PIN_SD1_DATA1, |
||||
IOMUX_CONFIG_ALT0); |
||||
mxc_request_iomux(MX53_PIN_SD1_DATA2, |
||||
IOMUX_CONFIG_ALT0); |
||||
mxc_request_iomux(MX53_PIN_SD1_DATA3, |
||||
IOMUX_CONFIG_ALT0); |
||||
mxc_request_iomux(MX53_PIN_EIM_DA13, |
||||
IOMUX_CONFIG_ALT1); |
||||
|
||||
mxc_iomux_set_pad(MX53_PIN_SD1_CMD, |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | |
||||
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); |
||||
mxc_iomux_set_pad(MX53_PIN_SD1_CLK, |
||||
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | |
||||
PAD_CTL_DRV_HIGH); |
||||
mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | |
||||
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); |
||||
mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | |
||||
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); |
||||
mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | |
||||
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); |
||||
mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | |
||||
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); |
||||
break; |
||||
case 1: |
||||
mxc_request_iomux(MX53_PIN_ATA_RESET_B, |
||||
IOMUX_CONFIG_ALT2); |
||||
mxc_request_iomux(MX53_PIN_ATA_IORDY, |
||||
IOMUX_CONFIG_ALT2); |
||||
mxc_request_iomux(MX53_PIN_ATA_DATA8, |
||||
IOMUX_CONFIG_ALT4); |
||||
mxc_request_iomux(MX53_PIN_ATA_DATA9, |
||||
IOMUX_CONFIG_ALT4); |
||||
mxc_request_iomux(MX53_PIN_ATA_DATA10, |
||||
IOMUX_CONFIG_ALT4); |
||||
mxc_request_iomux(MX53_PIN_ATA_DATA11, |
||||
IOMUX_CONFIG_ALT4); |
||||
mxc_request_iomux(MX53_PIN_ATA_DATA0, |
||||
IOMUX_CONFIG_ALT4); |
||||
mxc_request_iomux(MX53_PIN_ATA_DATA1, |
||||
IOMUX_CONFIG_ALT4); |
||||
mxc_request_iomux(MX53_PIN_ATA_DATA2, |
||||
IOMUX_CONFIG_ALT4); |
||||
mxc_request_iomux(MX53_PIN_ATA_DATA3, |
||||
IOMUX_CONFIG_ALT4); |
||||
mxc_request_iomux(MX53_PIN_EIM_DA11, |
||||
IOMUX_CONFIG_ALT1); |
||||
|
||||
mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B, |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | |
||||
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); |
||||
mxc_iomux_set_pad(MX53_PIN_ATA_IORDY, |
||||
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | |
||||
PAD_CTL_DRV_HIGH); |
||||
mxc_iomux_set_pad(MX53_PIN_ATA_DATA8, |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | |
||||
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); |
||||
mxc_iomux_set_pad(MX53_PIN_ATA_DATA9, |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | |
||||
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); |
||||
mxc_iomux_set_pad(MX53_PIN_ATA_DATA10, |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | |
||||
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); |
||||
mxc_iomux_set_pad(MX53_PIN_ATA_DATA11, |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | |
||||
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); |
||||
mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | |
||||
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); |
||||
mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | |
||||
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); |
||||
mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | |
||||
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); |
||||
mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | |
||||
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | |
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); |
||||
|
||||
break; |
||||
default: |
||||
printf("Warning: you configured more ESDHC controller" |
||||
"(%d) as supported by the board(2)\n", |
||||
CONFIG_SYS_FSL_ESDHC_NUM); |
||||
return status; |
||||
} |
||||
status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); |
||||
} |
||||
|
||||
return status; |
||||
} |
||||
#endif |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
setup_iomux_uart(); |
||||
setup_iomux_fec(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
gd->bd->bi_arch_number = MACH_TYPE_MX53_EVK; |
||||
/* address of boot parameters */ |
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_late_init(void) |
||||
{ |
||||
setup_i2c(1); |
||||
power_init(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
u32 cause; |
||||
struct src *src_regs = (struct src *)SRC_BASE_ADDR; |
||||
|
||||
puts("Board: MX53EVK ["); |
||||
|
||||
cause = src_regs->srsr; |
||||
switch (cause) { |
||||
case 0x0001: |
||||
printf("POR"); |
||||
break; |
||||
case 0x0009: |
||||
printf("RST"); |
||||
break; |
||||
case 0x0010: |
||||
case 0x0011: |
||||
printf("WDOG"); |
||||
break; |
||||
default: |
||||
printf("unknown"); |
||||
} |
||||
printf("]\n"); |
||||
return 0; |
||||
} |
@ -0,0 +1,51 @@ |
||||
#
|
||||
# Copyright (C) 2010 Samsung Electronics
|
||||
# Minkyu Kang <mk7.kang@samsung.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS-y := universal.o onenand.o
|
||||
SOBJS := lowlevel_init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS-y))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(SOBJS) $(OBJS) |
||||
$(call cmd_link_o_target, $(SOBJS) $(OBJS))
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
@ -0,0 +1,395 @@ |
||||
/* |
||||
* Lowlevel setup for universal board based on S5PC210 |
||||
* |
||||
* Copyright (C) 2010 Samsung Electronics |
||||
* Kyungmin Park <kyungmin.park@samsung.com>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <version.h> |
||||
#include <asm/arch/cpu.h> |
||||
#include <asm/arch/clock.h> |
||||
|
||||
/* |
||||
* Register usages: |
||||
* |
||||
* r5 has zero always |
||||
* r7 has GPIO part1 base 0x11400000 |
||||
* r6 has GPIO part2 base 0x11000000 |
||||
*/ |
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init: |
||||
mov r11, lr |
||||
|
||||
/* r5 has always zero */ |
||||
mov r5, #0 |
||||
|
||||
ldr r7, =S5PC210_GPIO_PART1_BASE |
||||
ldr r6, =S5PC210_GPIO_PART2_BASE |
||||
|
||||
/* System Timer */ |
||||
ldr r0, =S5PC210_SYSTIMER_BASE |
||||
ldr r1, =0x5000 |
||||
str r1, [r0, #0x0] |
||||
ldr r1, =0xffffffff |
||||
str r1, [r0, #0x8] |
||||
ldr r1, =0x49 |
||||
str r1, [r0, #0x4] |
||||
|
||||
/* PMIC manual reset */ |
||||
/* nPOWER: XEINT_23: GPX2[7] */ |
||||
add r0, r6, #0xC40 @ S5PC210_GPIO_X2_OFFSET
|
||||
ldr r1, [r0, #0x0] |
||||
bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
|
||||
orr r1, r1, #(0x1 << 28) @ Output
|
||||
str r1, [r0, #0x0] |
||||
|
||||
ldr r1, [r0, #0x4] |
||||
orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
|
||||
str r1, [r0, #0x4] |
||||
|
||||
/* init system clock */ |
||||
bl system_clock_init |
||||
|
||||
/* Disable Watchdog */ |
||||
ldr r0, =S5PC210_WATCHDOG_BASE @0x10060000
|
||||
str r5, [r0] |
||||
|
||||
/* UART */ |
||||
bl uart_asm_init |
||||
|
||||
/* PMU init */ |
||||
bl system_power_init |
||||
|
||||
bl tzpc_init |
||||
|
||||
mov lr, r11 |
||||
mov pc, lr |
||||
nop |
||||
nop |
||||
nop |
||||
|
||||
/* |
||||
* uart_asm_init: Initialize UART's pins |
||||
*/ |
||||
uart_asm_init: |
||||
/* |
||||
* setup UART0-UART4 GPIOs (part1) |
||||
* GPA1CON[3] = I2C_3_SCL (3) |
||||
* GPA1CON[2] = I2C_3_SDA (3) |
||||
*/ |
||||
mov r0, r7 |
||||
ldr r1, =0x22222222 |
||||
str r1, [r0, #0x00] @ S5PC210_GPIO_A0_OFFSET
|
||||
ldr r1, =0x00223322 |
||||
str r1, [r0, #0x20] @ S5PC210_GPIO_A1_OFFSET
|
||||
|
||||
/* UART_SEL GPY4[7] (part2) at S5PC210 */ |
||||
add r0, r6, #0x1A0 @ S5PC210_GPIO_Y4_OFFSET
|
||||
ldr r1, [r0, #0x0] |
||||
bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
|
||||
orr r1, r1, #(0x1 << 28) |
||||
str r1, [r0, #0x0] |
||||
|
||||
ldr r1, [r0, #0x8] |
||||
bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit
|
||||
orr r1, r1, #(0x3 << 14) @ Pull-up enabled
|
||||
str r1, [r0, #0x8] |
||||
|
||||
ldr r1, [r0, #0x4] |
||||
orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
|
||||
str r1, [r0, #0x4] |
||||
|
||||
mov pc, lr |
||||
nop |
||||
nop |
||||
nop |
||||
|
||||
system_clock_init: |
||||
ldr r0, =S5PC210_CLOCK_BASE |
||||
|
||||
/* APLL(1), MPLL(1), CORE(0), HPM(0) */ |
||||
ldr r1, =0x0101 |
||||
ldr r2, =0x14200 @ CLK_SRC_CPU
|
||||
str r1, [r0, r2] |
||||
|
||||
/* wait ?us */ |
||||
mov r1, #0x10000 |
||||
1: subs r1, r1, #1 |
||||
bne 1b |
||||
|
||||
/* |
||||
* CLK_SRC_TOP0 |
||||
* MUX_ONENAND_SEL[28] 0: DOUT133, 1: DOUT166 |
||||
* MUX_VPLL_SEL[8] 0: FINPLL, 1: FOUTVPLL |
||||
* MUX_EPLL_SEL[4] 0: FINPLL, 1: FOUTEPLL |
||||
*/ |
||||
ldr r1, =0x10000110 |
||||
ldr r2, =0x0C210 @ CLK_SRC_TOP
|
||||
str r1, [r0, r2] |
||||
|
||||
/* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */ |
||||
ldr r1, =0x0066666 |
||||
ldr r2, =0x0C240 @ CLK_SRC_FSYS
|
||||
str r1, [r0, r2] |
||||
/* UART[0:5], PWM: SCLKMPLL(6) */ |
||||
ldr r1, =0x6666666 |
||||
ldr r2, =0x0C250 @ CLK_SRC_PERIL0_OFFSET
|
||||
str r1, [r0, r2] |
||||
|
||||
/* CPU0: CORE, COREM0, COREM1, PERI, ATB, PCLK_DBG, APLL */ |
||||
ldr r1, =0x0133730 |
||||
ldr r2, =0x14500 @ CLK_DIV_CPU0
|
||||
str r1, [r0, r2] |
||||
/* CPU1: COPY, HPM */ |
||||
ldr r1, =0x03 |
||||
ldr r2, =0x14504 @ CLK_DIV_CPU1
|
||||
str r1, [r0, r2] |
||||
/* DMC0: ACP, ACP_PCLK, DPHY, DMC, DMCD, DMCP, COPY2 CORE_TIMER */ |
||||
ldr r1, =0x13111113 |
||||
ldr r2, =0x10500 @ CLK_DIV_DMC0
|
||||
str r1, [r0, r2] |
||||
/* DMC1: PWI, DVSEM, DPM */ |
||||
ldr r1, =0x01010100 |
||||
ldr r2, =0x10504 @ CLK_DIV_DMC1
|
||||
str r1, [r0, r2] |
||||
/* LEFTBUS: GDL, GPL */ |
||||
ldr r1, =0x13 |
||||
ldr r2, =0x04500 @ CLK_DIV_LEFTBUS
|
||||
str r1, [r0, r2] |
||||
/* RIGHHTBUS: GDR, GPR */ |
||||
ldr r1, =0x13 |
||||
ldr r2, =0x08500 @ CLK_DIV_RIGHTBUS
|
||||
str r1, [r0, r2] |
||||
/* |
||||
* CLK_DIV_TOP |
||||
* ONENAND_RATIOD[18:16]: 0 SCLK_ONENAND = MOUTONENAND / (n + 1) |
||||
* ACLK_200, ACLK_100, ACLK_160, ACLK_133, |
||||
*/ |
||||
ldr r1, =0x00005473 |
||||
ldr r2, =0x0C510 @ CLK_DIV_TOP
|
||||
str r1, [r0, r2] |
||||
/* MMC[0:1] */ |
||||
ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */ |
||||
ldr r2, =0x0C544 @ CLK_DIV_FSYS1
|
||||
str r1, [r0, r2] |
||||
/* MMC[2:3] */ |
||||
ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */ |
||||
ldr r2, =0x0C548 @ CLK_DIV_FSYS2
|
||||
str r1, [r0, r2] |
||||
/* MMC4 */ |
||||
ldr r1, =0x000f /* 800(MPLL) / (15 + 1) */ |
||||
ldr r2, =0x0C54C @ CLK_DIV_FSYS3
|
||||
str r1, [r0, r2] |
||||
/* UART[0:5] */ |
||||
ldr r1, =0x774777 |
||||
ldr r2, =0x0C550 @ CLK_DIV_PERIL0
|
||||
str r1, [r0, r2] |
||||
/* SLIMBUS: ???, PWM */ |
||||
ldr r1, =0x8 |
||||
ldr r2, =0x0C55C @ CLK_DIV_PERIL3
|
||||
str r1, [r0, r2] |
||||
|
||||
/* PLL Setting */ |
||||
ldr r1, =0x1C20 |
||||
ldr r2, =0x14000 @ APLL_LOCK
|
||||
str r1, [r0, r2] |
||||
ldr r2, =0x14008 @ MPLL_LOCK
|
||||
str r1, [r0, r2] |
||||
ldr r2, =0x0C010 @ EPLL_LOCK
|
||||
str r1, [r0, r2] |
||||
ldr r2, =0x0C020 @ VPLL_LOCK
|
||||
str r1, [r0, r2] |
||||
|
||||
/* APLL */ |
||||
ldr r1, =0x8000001c |
||||
ldr r2, =0x14104 @ APLL_CON1
|
||||
str r1, [r0, r2] |
||||
ldr r1, =0x80c80601 @ 800MHz
|
||||
ldr r2, =0x14100 @ APLL_CON0
|
||||
str r1, [r0, r2] |
||||
/* MPLL */ |
||||
ldr r1, =0x8000001C |
||||
ldr r2, =0x1410C @ MPLL_CON1
|
||||
str r1, [r0, r2] |
||||
ldr r1, =0x80c80601 @ 800MHz
|
||||
ldr r2, =0x14108 @ MPLL_CON0
|
||||
str r1, [r0, r2] |
||||
/* EPLL */ |
||||
ldr r1, =0x0 |
||||
ldr r2, =0x0C114 @ EPLL_CON1
|
||||
str r1, [r0, r2] |
||||
ldr r1, =0x80300302 @ 96MHz
|
||||
ldr r2, =0x0C110 @ EPLL_CON0
|
||||
str r1, [r0, r2] |
||||
/* VPLL */ |
||||
ldr r1, =0x11000400 |
||||
ldr r2, =0x0C124 @ VPLL_CON1
|
||||
str r1, [r0, r2] |
||||
ldr r1, =0x80350302 @ 108MHz
|
||||
ldr r2, =0x0C120 @ VPLL_CON0
|
||||
str r1, [r0, r2] |
||||
|
||||
/* |
||||
* SMMUJPEG[11], JPEG[6], CSIS1[5] : 0111 1001 |
||||
* Turn off all |
||||
*/ |
||||
ldr r1, =0xFFF80000 |
||||
ldr r2, =0x0C920 @ CLK_GATE_IP_CAM
|
||||
str r1, [r0, r2] |
||||
|
||||
/* Turn off all */ |
||||
ldr r1, =0xFFFFFFC0 |
||||
ldr r2, =0x0C924 @ CLK_GATE_IP_VP
|
||||
str r1, [r0, r2] |
||||
|
||||
/* Turn off all */ |
||||
ldr r1, =0xFFFFFFE0 |
||||
ldr r2, =0x0C928 @ CLK_GATE_IP_MFC
|
||||
str r1, [r0, r2] |
||||
|
||||
/* Turn off all */ |
||||
ldr r1, =0xFFFFFFFC |
||||
ldr r2, =0x0C92C @ CLK_GATE_IP_G3D
|
||||
str r1, [r0, r2] |
||||
|
||||
/* Turn off all */ |
||||
ldr r1, =0xFFFFFC00 |
||||
ldr r2, =0x0C930 @ CLK_GATE_IP_IMAGE
|
||||
str r1, [r0, r2] |
||||
|
||||
/* DSIM0[3], MDNIE0[2], MIE0[1] : 0001 */ |
||||
ldr r1, =0xFFFFFFF1 |
||||
ldr r2, =0x0C934 @ CLK_GATE_IP_LCD0
|
||||
str r1, [r0, r2] |
||||
|
||||
/* Turn off all */ |
||||
ldr r1, =0xFFFFFFC0 |
||||
ldr r2, =0x0C938 @ CLK_GATE_IP_LCD1
|
||||
str r1, [r0, r2] |
||||
|
||||
/* |
||||
* SMMUPCIE[18], NFCON[16] : 1111 1010 |
||||
* PCIE[14], SATA[10], SDMMC43[9:8] : 1011 1000 |
||||
* SDMMC1[6], TSI[4], SATAPHY[3], PCIEPHY[2] : 1010 0011 |
||||
*/ |
||||
ldr r1, =0xFFFAB8A3 |
||||
ldr r2, =0x0C940 @ CLK_GATE_IP_FSYS
|
||||
str r1, [r0, r2] |
||||
|
||||
/* Turn off all */ |
||||
ldr r1, =0xFFFFFFFC |
||||
ldr r2, =0x0C94C @ CLK_GATE_IP_GPS
|
||||
str r1, [r0, r2] |
||||
|
||||
/* |
||||
* AC97[27], SPDIF[26], SLIMBUS[25] : 1111 0001 |
||||
* I2C2[8] : 1111 1110 |
||||
*/ |
||||
ldr r1, =0xF1FFFEFF |
||||
ldr r2, =0x0C950 @ CLK_GATE_IP_PERIL
|
||||
str r1, [r0, r2] |
||||
|
||||
/* |
||||
* KEYIF[16] : 1111 1110 |
||||
*/ |
||||
ldr r1, =0xFFFEFFFF |
||||
ldr r2, =0x0C960 @ CLK_GATE_IP_PERIR
|
||||
str r1, [r0, r2] |
||||
|
||||
/* LCD1[5], G3D[3], MFC[2], TV[1] : 1101 0001 */ |
||||
ldr r1, =0xFFFFFFD1 |
||||
ldr r2, =0x0C970 @ CLK_GATE_BLOCK
|
||||
str r1, [r0, r2] |
||||
mov pc, lr |
||||
nop |
||||
nop |
||||
nop |
||||
|
||||
system_power_init: |
||||
ldr r0, =S5PC210_POWER_BASE @ 0x10020000
|
||||
|
||||
ldr r2, =0x330C @ PS_HOLD_CONTROL
|
||||
ldr r1, [r0, r2] |
||||
orr r1, r1, #(0x3 << 8) @ Data High, Output En
|
||||
str r1, [r0, r2] |
||||
|
||||
/* Power Down */ |
||||
add r2, r0, #0x3000 |
||||
str r5, [r2, #0xC20] @ TV_CONFIGURATION
|
||||
str r5, [r2, #0xC40] @ MFC_CONFIGURATION
|
||||
str r5, [r2, #0xC60] @ G3D_CONFIGURATION
|
||||
str r5, [r2, #0xCA0] @ LCD1_CONFIGURATION
|
||||
str r5, [r2, #0xCE0] @ GPS_CONFIGURATION
|
||||
|
||||
mov pc, lr |
||||
nop |
||||
nop |
||||
nop |
||||
|
||||
tzpc_init: |
||||
ldr r0, =0x10110000 |
||||
mov r1, #0x0 |
||||
str r1, [r0] |
||||
mov r1, #0xff |
||||
str r1, [r0, #0x0804] |
||||
str r1, [r0, #0x0810] |
||||
str r1, [r0, #0x081C] |
||||
str r1, [r0, #0x0828] |
||||
|
||||
ldr r0, =0x10120000 |
||||
mov r1, #0x0 |
||||
str r1, [r0] |
||||
mov r1, #0xff |
||||
str r1, [r0, #0x0804] |
||||
str r1, [r0, #0x0810] |
||||
str r1, [r0, #0x081C] |
||||
str r1, [r0, #0x0828] |
||||
|
||||
ldr r0, =0x10130000 |
||||
mov r1, #0x0 |
||||
str r1, [r0] |
||||
mov r1, #0xff |
||||
str r1, [r0, #0x0804] |
||||
str r1, [r0, #0x0810] |
||||
str r1, [r0, #0x081C] |
||||
str r1, [r0, #0x0828] |
||||
|
||||
ldr r0, =0x10140000 |
||||
mov r1, #0x0 |
||||
str r1, [r0] |
||||
mov r1, #0xff |
||||
str r1, [r0, #0x0804] |
||||
str r1, [r0, #0x0810] |
||||
str r1, [r0, #0x081C] |
||||
str r1, [r0, #0x0828] |
||||
|
||||
ldr r0, =0x10150000 |
||||
mov r1, #0x0 |
||||
str r1, [r0] |
||||
mov r1, #0xff |
||||
str r1, [r0, #0x0804] |
||||
str r1, [r0, #0x0810] |
||||
str r1, [r0, #0x081C] |
||||
str r1, [r0, #0x0828] |
||||
|
||||
mov pc, lr |
@ -0,0 +1,34 @@ |
||||
/*
|
||||
* Copyright (C) 2010 Samsung Electronics |
||||
* Kyungmin Park <kyungmin.park@samsung.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <linux/mtd/mtd.h> |
||||
#include <linux/mtd/onenand.h> |
||||
|
||||
void onenand_board_init(struct mtd_info *mtd) |
||||
{ |
||||
struct onenand_chip *this = mtd->priv; |
||||
|
||||
this->base = (void *)CONFIG_SYS_ONENAND_BASE; |
||||
this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK; |
||||
} |
@ -0,0 +1,250 @@ |
||||
/*
|
||||
* Copyright (C) 2010 Samsung Electronics |
||||
* Minkyu Kang <mk7.kang@samsung.com> |
||||
* Kyungmin Park <kyungmin.park@samsung.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/adc.h> |
||||
#include <asm/arch/gpio.h> |
||||
#include <asm/arch/mmc.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
struct s5pc210_gpio_part1 *gpio1; |
||||
struct s5pc210_gpio_part2 *gpio2; |
||||
unsigned int board_rev; |
||||
|
||||
u32 get_board_rev(void) |
||||
{ |
||||
return board_rev; |
||||
} |
||||
|
||||
static int get_hwrev(void) |
||||
{ |
||||
return board_rev & 0xFF; |
||||
} |
||||
|
||||
static void check_hw_revision(void); |
||||
|
||||
int board_init(void) |
||||
{ |
||||
gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE; |
||||
gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE; |
||||
|
||||
gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210; |
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; |
||||
|
||||
check_hw_revision(); |
||||
printf("HW Revision:\t0x%x\n", board_rev); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + |
||||
get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void dram_init_banksize(void) |
||||
{ |
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
||||
gd->bd->bi_dram[1].start = PHYS_SDRAM_2; |
||||
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; |
||||
} |
||||
|
||||
static unsigned short get_adc_value(int channel) |
||||
{ |
||||
struct s5p_adc *adc = (struct s5p_adc *)samsung_get_base_adc(); |
||||
unsigned short ret = 0; |
||||
unsigned int reg; |
||||
unsigned int loop = 0; |
||||
|
||||
writel(channel & 0xF, &adc->adcmux); |
||||
writel((1 << 14) | (49 << 6), &adc->adccon); |
||||
writel(1000 & 0xffff, &adc->adcdly); |
||||
writel(readl(&adc->adccon) | (1 << 16), &adc->adccon); /* 12 bit */ |
||||
udelay(10); |
||||
writel(readl(&adc->adccon) | (1 << 0), &adc->adccon); /* Enable */ |
||||
udelay(10); |
||||
|
||||
do { |
||||
udelay(1); |
||||
reg = readl(&adc->adccon); |
||||
} while (!(reg & (1 << 15)) && (loop++ < 1000)); |
||||
|
||||
ret = readl(&adc->adcdat0) & 0xFFF; |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static unsigned int get_hw_revision(void) |
||||
{ |
||||
int hwrev, mode0, mode1; |
||||
|
||||
mode0 = get_adc_value(1); /* HWREV_MODE0 */ |
||||
mode1 = get_adc_value(2); /* HWREV_MODE1 */ |
||||
|
||||
/*
|
||||
* XXX Always set the default hwrev as the latest board |
||||
* ADC = (voltage) / 3.3 * 4096 |
||||
*/ |
||||
hwrev = 3; |
||||
|
||||
#define IS_RANGE(x, min, max) ((x) > (min) && (x) < (max)) |
||||
if (IS_RANGE(mode0, 80, 200) && IS_RANGE(mode1, 80, 200)) |
||||
hwrev = 0x0; /* 0.01V 0.01V */ |
||||
if (IS_RANGE(mode0, 750, 1000) && IS_RANGE(mode1, 80, 200)) |
||||
hwrev = 0x1; /* 610mV 0.01V */ |
||||
if (IS_RANGE(mode0, 1300, 1700) && IS_RANGE(mode1, 80, 200)) |
||||
hwrev = 0x2; /* 1.16V 0.01V */ |
||||
if (IS_RANGE(mode0, 2000, 2400) && IS_RANGE(mode1, 80, 200)) |
||||
hwrev = 0x3; /* 1.79V 0.01V */ |
||||
#undef IS_RANGE |
||||
|
||||
debug("mode0: %d, mode1: %d, hwrev 0x%x\n", mode0, mode1, hwrev); |
||||
|
||||
return hwrev; |
||||
} |
||||
|
||||
static void check_hw_revision(void) |
||||
{ |
||||
int hwrev; |
||||
|
||||
hwrev = get_hw_revision(); |
||||
|
||||
board_rev |= hwrev; |
||||
} |
||||
|
||||
#ifdef CONFIG_DISPLAY_BOARDINFO |
||||
int checkboard(void) |
||||
{ |
||||
puts("Board:\tUniversal C210\n"); |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_GENERIC_MMC |
||||
int board_mmc_init(bd_t *bis) |
||||
{ |
||||
int i, err; |
||||
|
||||
switch (get_hwrev()) { |
||||
case 0: |
||||
/*
|
||||
* Set the low to enable LDO_EN |
||||
* But when you use the test board for eMMC booting |
||||
* you should set it HIGH since it removes the inverter |
||||
*/ |
||||
/* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */ |
||||
gpio_direction_output(&gpio1->e3, 6, 0); |
||||
break; |
||||
default: |
||||
/*
|
||||
* Default reset state is High and there's no inverter |
||||
* But set it as HIGH to ensure |
||||
*/ |
||||
/* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */ |
||||
gpio_direction_output(&gpio1->e1, 3, 1); |
||||
break; |
||||
} |
||||
|
||||
/*
|
||||
* eMMC GPIO: |
||||
* SDR 8-bit@48MHz at MMC0 |
||||
* GPK0[0] SD_0_CLK(2) |
||||
* GPK0[1] SD_0_CMD(2) |
||||
* GPK0[2] SD_0_CDn -> Not used |
||||
* GPK0[3:6] SD_0_DATA[0:3](2) |
||||
* GPK1[3:6] SD_0_DATA[0:3](3) |
||||
* |
||||
* DDR 4-bit@26MHz at MMC4 |
||||
* GPK0[0] SD_4_CLK(3) |
||||
* GPK0[1] SD_4_CMD(3) |
||||
* GPK0[2] SD_4_CDn -> Not used |
||||
* GPK0[3:6] SD_4_DATA[0:3](3) |
||||
* GPK1[3:6] SD_4_DATA[4:7](4) |
||||
*/ |
||||
for (i = 0; i < 7; i++) { |
||||
if (i == 2) |
||||
continue; |
||||
/* GPK0[0:6] special function 2 */ |
||||
gpio_cfg_pin(&gpio2->k0, i, 0x2); |
||||
/* GPK0[0:6] pull disable */ |
||||
gpio_set_pull(&gpio2->k0, i, GPIO_PULL_NONE); |
||||
/* GPK0[0:6] drv 4x */ |
||||
gpio_set_drv(&gpio2->k0, i, GPIO_DRV_4X); |
||||
} |
||||
|
||||
for (i = 3; i < 7; i++) { |
||||
/* GPK1[3:6] special function 3 */ |
||||
gpio_cfg_pin(&gpio2->k1, i, 0x3); |
||||
/* GPK1[3:6] pull disable */ |
||||
gpio_set_pull(&gpio2->k1, i, GPIO_PULL_NONE); |
||||
/* GPK1[3:6] drv 4x */ |
||||
gpio_set_drv(&gpio2->k1, i, GPIO_DRV_4X); |
||||
} |
||||
|
||||
/* T-flash detect */ |
||||
gpio_cfg_pin(&gpio2->x3, 4, 0xf); |
||||
gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP); |
||||
|
||||
/*
|
||||
* MMC device init |
||||
* mmc0 : eMMC (8-bit buswidth) |
||||
* mmc2 : SD card (4-bit buswidth) |
||||
*/ |
||||
err = s5p_mmc_init(0, 8); |
||||
|
||||
/*
|
||||
* Check the T-flash detect pin |
||||
* GPX3[4] T-flash detect pin |
||||
*/ |
||||
if (!gpio_get_value(&gpio2->x3, 4)) { |
||||
/*
|
||||
* SD card GPIO: |
||||
* GPK2[0] SD_2_CLK(2) |
||||
* GPK2[1] SD_2_CMD(2) |
||||
* GPK2[2] SD_2_CDn -> Not used |
||||
* GPK2[3:6] SD_2_DATA[0:3](2) |
||||
*/ |
||||
for (i = 0; i < 7; i++) { |
||||
if (i == 2) |
||||
continue; |
||||
/* GPK2[0:6] special function 2 */ |
||||
gpio_cfg_pin(&gpio2->k2, i, 0x2); |
||||
/* GPK2[0:6] pull disable */ |
||||
gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); |
||||
/* GPK2[0:6] drv 4x */ |
||||
gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); |
||||
} |
||||
err = s5p_mmc_init(2, 4); |
||||
} |
||||
|
||||
return err; |
||||
|
||||
} |
||||
#endif |
@ -0,0 +1,188 @@ |
||||
Overview |
||||
-------------- |
||||
|
||||
mx35pdk (known als as mx35_3stack) is a development board by Freescale. |
||||
It consists of three pluggable board: |
||||
- CPU module, with CPU, RAM, flash |
||||
- Personality board, with most interfaces (USB, Network,..) |
||||
- Debug board with JTAG header. |
||||
|
||||
The board is usually delivered with redboot. This howto explains how to boot |
||||
a linux kernel and how to replace the original bootloader with U-Boot. |
||||
|
||||
The board is delivered with Redboot on the NAND flash. It is possible to |
||||
switch the boot device with the switches SW1-SW2 on the Personality board, |
||||
and with SW5-SW10 on the Debug board. |
||||
|
||||
Delivered Redboot script to start the kernel |
||||
--------------------------------------------------- |
||||
|
||||
In redboot the following script is stored: |
||||
|
||||
fis load kernel |
||||
exec -c "noinitrd console=ttymxc0,115200 root=/dev/mtdblock8 rw rootfstype=jffs2 ip=dhcp fec_mac=00:04:9F:00:E7:76" |
||||
|
||||
Kernel is taken from flash. The image is in zImage format. |
||||
|
||||
Booting from NET, rootfs on NFS: |
||||
----------------------------------- |
||||
|
||||
To change the script in redboot: |
||||
|
||||
load -r -b 0x100000 <path_to_zImage> |
||||
exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/armVFP rw ip=dhcp" |
||||
|
||||
If the ip address is not set, you can set it with : |
||||
|
||||
ip_address -l <board_ip/netmask> -h <server_ip> |
||||
|
||||
Linux partitions: |
||||
--------------------------- |
||||
|
||||
As default, the board is shipped with these partition tables for NAND |
||||
and for NOR: |
||||
|
||||
Creating 5 MTD partitions on "NAND 2GiB 3,3V 8-bit": |
||||
0x00000000-0x00100000 : "nand.bootloader" |
||||
0x00100000-0x00600000 : "nand.kernel" |
||||
0x00600000-0x06600000 : "nand.rootfs" |
||||
0x06600000-0x06e00000 : "nand.configure" |
||||
0x06e00000-0x80000000 : "nand.userfs" |
||||
|
||||
Creating 6 MTD partitions on "mxc_nor_flash.0": |
||||
0x00000000-0x00080000 : "Bootloader" |
||||
0x00080000-0x00480000 : "nor.Kernel" |
||||
0x00480000-0x02280000 : "nor.userfs" |
||||
0x02280000-0x03e80000 : "nor.rootfs" |
||||
0x01fe0000-0x01fe3000 : "FIS directory" |
||||
0x01fff000-0x04000000 : "Redboot config" |
||||
|
||||
NAND partitions can be recognized enabling in kernel CONFIG_MTD_REDBOOT_PARTS. |
||||
For this board, CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK should be set to 2. |
||||
|
||||
However, the setup in redboot is not correct and does not use the whole flash. |
||||
|
||||
Better solution is to use the kernel parameter mtdparts. |
||||
Here the resulting script to be defined in RedBoot with fconfig: |
||||
|
||||
load -r -b 0x100000 sbabic/mx35pdk/zImage.2.6.37 |
||||
exec -c "noinitrd console=ttymxc0,115200 root=/dev/nfsroot rootfstype=nfsroot nfsroot=192.168.1.1:/opt/eldk-4.2-arm/arm rw ip=dhcp mtdparts=mxc_nand:1m(boot),5m(linux),96m(root),8m(cfg),1938m(user);physmap-flash.0:512k(b),4m(k),30m(u),28m(r)" |
||||
|
||||
Flashing U-Boot |
||||
-------------------------------- |
||||
|
||||
There are two options: the original bootloader in NAND can be replaced with |
||||
u-boot, or u-boot can be stored on the NOR flash without erasing |
||||
the delivered bootloader. |
||||
The boot storage can be select using the switches on the personality board |
||||
(SW1-SW2) and on the DEBUG board (SW4-SW10). |
||||
|
||||
The second option is to be preferred if you have not a JTAG debugger. |
||||
If something goes wrong flashing the bootloader, it is always possible to |
||||
recover the board booting from the other device. |
||||
|
||||
Replacing the bootloader on the NAND |
||||
-------------------------------------- |
||||
To replace RedBoot with U-Boot, the easy way is to do this in linux. |
||||
Start the kernel with the suggested options. Make sure to have set the |
||||
mtdparts exactly as described, because this matches the layout on the |
||||
mx35pdk. |
||||
|
||||
You should see in your boot log the following entries for the NAND |
||||
flash: |
||||
|
||||
5 cmdlinepart partitions found on MTD device mxc_nand |
||||
Creating 5 MTD partitions on "mxc_nand": |
||||
0x000000000000-0x000000100000 : "boot" |
||||
0x000000100000-0x000000600000 : "linux" |
||||
0x000000600000-0x000006600000 : "root" |
||||
0x000006600000-0x000006e00000 : "cfg" |
||||
0x000006e00000-0x000080000000 : "user" |
||||
|
||||
You can use the utilities flash_eraseall and nandwrite to put |
||||
u-boot on the NAND. The bootloader is marked as "boot", and 1MB is |
||||
reserved. If everything is correct, this partition is accessed as |
||||
/dev/mtd4. However, check if it is correct with "cat /proc/mtd" and |
||||
get the device node from the partition name: |
||||
|
||||
$ cat /proc/mtd | grep boot |
||||
|
||||
I suggest you try the utilities on a different partition to be sure |
||||
if everything works correctly. If not, and you remove RedBoot, you have to |
||||
reinstall it using the ATK tool as suggested by Freescale, or using a |
||||
JTAG debugger. |
||||
|
||||
I report the versions of the utilities I used (they are provided with ELDK): |
||||
|
||||
-bash-3.2# nandwrite --version |
||||
nandwrite $Revision: 1.32 $ |
||||
|
||||
flash_eraseall --version |
||||
flash_eraseall $Revision: 1.22 $ |
||||
|
||||
nandwrite reports a warning if the file to be saved is not sector aligned. |
||||
This should have no consequences, but I preferred to pad u-boot.bin |
||||
to get no problem at all. |
||||
$ dd if=/dev/zero of=zeros bs=1 count=74800 |
||||
$ cat u-boot.bin zeros > u-boot-padded.bin |
||||
|
||||
To erase the partition: |
||||
$ flash_eraseall /dev/mtd4 |
||||
|
||||
Writing u-boot: |
||||
|
||||
$ nandwrite /dev/mtd4 u-boot-padded.bin |
||||
|
||||
Now U-Boot is stored on the booting partition. |
||||
|
||||
To boot from NAND, you have to select the switches as follows: |
||||
|
||||
Personality board |
||||
SW2 1, 4, 5 on |
||||
2, 3, 6, 7, 8 off |
||||
SW1 all off |
||||
|
||||
Debug Board: |
||||
SW5 0 |
||||
SW6 0 |
||||
SW7 0 |
||||
SW8 1 |
||||
SW9 1 |
||||
SW10 0 |
||||
|
||||
|
||||
Saving U-Boot in the NOR flash |
||||
--------------------------------- |
||||
|
||||
The procedure to save in the NOR flash is quite the same as to write into the NAND. |
||||
|
||||
Check the partition for boot in the NOR flash. Setting the mtdparts as reported, |
||||
the boot partition should be /dev/mtd0. |
||||
|
||||
Creating 6 MTD partitions on "mxc_nor_flash.0": |
||||
0x00000000-0x00080000 : "Bootloader" |
||||
0x00080000-0x00480000 : "nor.Kernel" |
||||
0x00480000-0x02280000 : "nor.userfs" |
||||
0x02280000-0x03e80000 : "nor.rootfs" |
||||
0x01fe0000-0x01fe3000 : "FIS directory" |
||||
0x01fff000-0x04000000 : "Redboot config" |
||||
|
||||
To erase the whole partition: |
||||
$ flash_eraseall /dev/mtd0 |
||||
|
||||
Writing u-boot: |
||||
dd if=u-boot.bin of=/dev/mtd0 |
||||
|
||||
To boot from NOR, you have to select the switches as follows: |
||||
|
||||
Personality board |
||||
SW2 all off |
||||
SW1 all off |
||||
|
||||
Debug Board: |
||||
SW5 0 |
||||
SW6 0 |
||||
SW7 0 |
||||
SW8 1 |
||||
SW9 1 |
||||
SW10 0 |
@ -0,0 +1,146 @@ |
||||
/*
|
||||
* Freescale iMX51 ATA driver |
||||
* |
||||
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> |
||||
* |
||||
* Based on code by: |
||||
* Mahesh Mahadevan <mahesh.mahadevan@freescale.com> |
||||
* |
||||
* Based on code from original FSL ATA driver, which is |
||||
* part of eCos, the Embedded Configurable Operating System. |
||||
* Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <config.h> |
||||
#include <asm/byteorder.h> |
||||
#include <asm/io.h> |
||||
#include <ide.h> |
||||
|
||||
#include <asm/arch/imx-regs.h> |
||||
#include <asm/arch/clock.h> |
||||
|
||||
/* MXC ATA register offsets */ |
||||
struct mxc_ata_config_regs { |
||||
u8 time_off; /* 0x00 */ |
||||
u8 time_on; |
||||
u8 time_1; |
||||
u8 time_2w; |
||||
u8 time_2r; |
||||
u8 time_ax; |
||||
u8 time_pio_rdx; |
||||
u8 time_4; |
||||
u8 time_9; |
||||
u8 time_m; |
||||
u8 time_jn; |
||||
u8 time_d; |
||||
u8 time_k; |
||||
u8 time_ack; |
||||
u8 time_env; |
||||
u8 time_udma_rdx; |
||||
u8 time_zah; /* 0x10 */ |
||||
u8 time_mlix; |
||||
u8 time_dvh; |
||||
u8 time_dzfs; |
||||
u8 time_dvs; |
||||
u8 time_cvh; |
||||
u8 time_ss; |
||||
u8 time_cyc; |
||||
u32 fifo_data_32; /* 0x18 */ |
||||
u32 fifo_data_16; |
||||
u32 fifo_fill; |
||||
u32 ata_control; |
||||
u32 interrupt_pending; |
||||
u32 interrupt_enable; |
||||
u32 interrupt_clear; |
||||
u32 fifo_alarm; |
||||
}; |
||||
|
||||
struct mxc_data_hdd_regs { |
||||
u32 drive_data; /* 0xa0 */ |
||||
u32 drive_features; |
||||
u32 drive_sector_count; |
||||
u32 drive_sector_num; |
||||
u32 drive_cyl_low; |
||||
u32 drive_cyl_high; |
||||
u32 drive_dev_head; |
||||
u32 command; |
||||
u32 status; |
||||
u32 alt_status; |
||||
}; |
||||
|
||||
/* PIO timing table */ |
||||
#define NR_PIO_SPECS 5 |
||||
static uint16_t pio_t1[NR_PIO_SPECS] = { 70, 50, 30, 30, 25 }; |
||||
static uint16_t pio_t2_8[NR_PIO_SPECS] = { 290, 290, 290, 80, 70 }; |
||||
static uint16_t pio_t4[NR_PIO_SPECS] = { 30, 20, 15, 10, 10 }; |
||||
static uint16_t pio_t9[NR_PIO_SPECS] = { 20, 15, 10, 10, 10 }; |
||||
static uint16_t pio_tA[NR_PIO_SPECS] = { 50, 50, 50, 50, 50 }; |
||||
|
||||
#define REG2OFF(reg) ((((uint32_t)reg) & 0x3) * 8) |
||||
static void set_ata_bus_timing(unsigned char mode) |
||||
{ |
||||
uint32_t val; |
||||
uint32_t T = 1000000000 / mxc_get_clock(MXC_IPG_CLK); |
||||
|
||||
struct mxc_ata_config_regs *ata_regs; |
||||
ata_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR; |
||||
|
||||
if (mode >= NR_PIO_SPECS) |
||||
return; |
||||
|
||||
/* Write TIME_OFF/ON/1/2W */ |
||||
val = (3 << REG2OFF(&ata_regs->time_off)) | |
||||
(3 << REG2OFF(&ata_regs->time_on)) | |
||||
(((pio_t1[mode] + T) / T) << REG2OFF(&ata_regs->time_1)) | |
||||
(((pio_t2_8[mode] + T) / T) << REG2OFF(&ata_regs->time_2w)); |
||||
writel(val, &ata_regs->time_off); |
||||
|
||||
/* Write TIME_2R/AX/RDX/4 */ |
||||
val = (((pio_t2_8[mode] + T) / T) << REG2OFF(&ata_regs->time_2r)) | |
||||
(((pio_tA[mode] + T) / T + 2) << REG2OFF(&ata_regs->time_ax)) | |
||||
(1 << REG2OFF(&ata_regs->time_pio_rdx)) | |
||||
(((pio_t4[mode] + T) / T) << REG2OFF(&ata_regs->time_4)); |
||||
writel(val, &ata_regs->time_2r); |
||||
|
||||
/* Write TIME_9 ; the rest of timing registers is irrelevant for PIO */ |
||||
val = (((pio_t9[mode] + T) / T) << REG2OFF(&ata_regs->time_9)); |
||||
writel(val, &ata_regs->time_9); |
||||
} |
||||
|
||||
int ide_preinit(void) |
||||
{ |
||||
struct mxc_ata_config_regs *ata_regs; |
||||
ata_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR; |
||||
|
||||
/* 46.3.3.4 @ FSL iMX51 manual */ |
||||
/* FIFO normal op., drive reset */ |
||||
writel(0x80, &ata_regs->ata_control); |
||||
/* FIFO normal op., drive not reset */ |
||||
writel(0xc0, &ata_regs->ata_control); |
||||
|
||||
/* Configure the PIO timing */ |
||||
set_ata_bus_timing(CONFIG_MXC_ATA_PIO_MODE); |
||||
|
||||
/* 46.3.3.4 @ FSL iMX51 manual */ |
||||
/* Drive not reset, IORDY handshake */ |
||||
writel(0x41, &ata_regs->ata_control); |
||||
|
||||
return 0; |
||||
} |
Some files were not shown because too many files have changed in this diff Show More
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Reference in new issue