Adding the following data: -> Prcm structure -> Base addresses -> Pin mux structure. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>master
Lokesh Vutla
12 years ago
committed by
Tom Rini
parent
fbf2728da3
commit
c06e498a16
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/*
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* hardware_am43xx.h |
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* |
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* AM43xx hardware specific header |
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* |
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* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __AM43XX_HARDWARE_AM43XX_H |
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#define __AM43XX_HARDWARE_AM43XX_H |
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/* Module base addresses */ |
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/* UART Base Address */ |
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#define UART0_BASE 0x44E09000 |
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/* GPIO Base address */ |
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#define GPIO2_BASE 0x481AC000 |
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/* Watchdog Timer */ |
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#define WDT_BASE 0x44E35000 |
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/* Control Module Base Address */ |
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#define CTRL_BASE 0x44E10000 |
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#define CTRL_DEVICE_BASE 0x44E10600 |
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/* PRCM Base Address */ |
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#define PRCM_BASE 0x44DF0000 |
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#define CM_WKUP 0x44DF2800 |
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#define CM_PER 0x44DF8800 |
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#define PRM_RSTCTRL (PRCM_BASE + 0x4000) |
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#define PRM_RSTST (PRM_RSTCTRL + 4) |
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/* VTP Base address */ |
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#define VTP0_CTRL_ADDR 0x44E10E0C |
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/* DDR Base address */ |
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#define DDR_PHY_CMD_ADDR 0x44E12000 |
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#define DDR_PHY_DATA_ADDR 0x44E120C8 |
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#define DDR_DATA_REGS_NR 2 |
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/* CPSW Config space */ |
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#define CPSW_MDIO_BASE 0x4A101000 |
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/* RTC base address */ |
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#define RTC_BASE 0x44E3E000 |
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#endif /* __AM43XX_HARDWARE_AM43XX_H */ |
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/*
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* mux_am43xx.h |
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* |
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _MUX_AM43XX_H_ |
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#define _MUX_AM43XX_H_ |
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#include <common.h> |
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#include <asm/io.h> |
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#define MUX_CFG(value, offset) \ |
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__raw_writel(value, (CTRL_BASE + offset)); |
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/* PAD Control Fields */ |
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#define SLEWCTRL (0x1 << 19) |
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#define RXACTIVE (0x1 << 18) |
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#define PULLDOWN_EN (0x0 << 17) /* Pull Down Selection */ |
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#define PULLUP_EN (0x1 << 17) /* Pull Up Selection */ |
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#define PULLUDEN (0x0 << 16) /* Pull up/down enable */ |
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#define PULLUDDIS (0x1 << 16) /* Pull up/down disable */ |
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#define MODE(val) val /* used for Readability */ |
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/*
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* PAD CONTROL OFFSETS |
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* Field names corresponds to the pad signal name |
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*/ |
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struct pad_signals { |
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int gpmc_ad0; |
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int gpmc_ad1; |
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int gpmc_ad2; |
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int gpmc_ad3; |
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int gpmc_ad4; |
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int gpmc_ad5; |
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int gpmc_ad6; |
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int gpmc_ad7; |
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int gpmc_ad8; |
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int gpmc_ad9; |
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int gpmc_ad10; |
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int gpmc_ad11; |
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int gpmc_ad12; |
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int gpmc_ad13; |
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int gpmc_ad14; |
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int gpmc_ad15; |
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int gpmc_a0; |
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int gpmc_a1; |
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int gpmc_a2; |
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int gpmc_a3; |
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int gpmc_a4; |
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int gpmc_a5; |
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int gpmc_a6; |
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int gpmc_a7; |
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int gpmc_a8; |
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int gpmc_a9; |
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int gpmc_a10; |
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int gpmc_a11; |
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int gpmc_wait0; |
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int gpmc_wpn; |
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int gpmc_be1n; |
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int gpmc_csn0; |
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int gpmc_csn1; |
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int gpmc_csn2; |
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int gpmc_csn3; |
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int gpmc_clk; |
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int gpmc_advn_ale; |
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int gpmc_oen_ren; |
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int gpmc_wen; |
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int gpmc_be0n_cle; |
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int lcd_data0; |
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int lcd_data1; |
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int lcd_data2; |
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int lcd_data3; |
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int lcd_data4; |
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int lcd_data5; |
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int lcd_data6; |
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int lcd_data7; |
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int lcd_data8; |
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int lcd_data9; |
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int lcd_data10; |
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int lcd_data11; |
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int lcd_data12; |
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int lcd_data13; |
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int lcd_data14; |
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int lcd_data15; |
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int lcd_vsync; |
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int lcd_hsync; |
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int lcd_pclk; |
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int lcd_ac_bias_en; |
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int mmc0_dat3; |
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int mmc0_dat2; |
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int mmc0_dat1; |
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int mmc0_dat0; |
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int mmc0_clk; |
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int mmc0_cmd; |
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int mii1_col; |
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int mii1_crs; |
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int mii1_rxerr; |
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int mii1_txen; |
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int mii1_rxdv; |
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int mii1_txd3; |
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int mii1_txd2; |
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int mii1_txd1; |
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int mii1_txd0; |
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int mii1_txclk; |
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int mii1_rxclk; |
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int mii1_rxd3; |
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int mii1_rxd2; |
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int mii1_rxd1; |
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int mii1_rxd0; |
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int rmii1_refclk; |
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int mdio_data; |
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int mdio_clk; |
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int spi0_sclk; |
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int spi0_d0; |
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int spi0_d1; |
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int spi0_cs0; |
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int spi0_cs1; |
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int ecap0_in_pwm0_out; |
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int uart0_ctsn; |
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int uart0_rtsn; |
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int uart0_rxd; |
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int uart0_txd; |
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int uart1_ctsn; |
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int uart1_rtsn; |
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int uart1_rxd; |
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int uart1_txd; |
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int i2c0_sda; |
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int i2c0_scl; |
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int mcasp0_aclkx; |
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int mcasp0_fsx; |
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int mcasp0_axr0; |
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int mcasp0_ahclkr; |
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int mcasp0_aclkr; |
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int mcasp0_fsr; |
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int mcasp0_axr1; |
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int mcasp0_ahclkx; |
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}; |
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#endif /* _MUX_AM43XX_H_ */ |
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