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usb: s3c-otg: Rename struct s3c_plat_otg_data

Browse Source 
The driver is actually for the Designware DWC2 controller.
This patch is the first to rename global symbol, the struct
s3c_plat_otg_data.

The rename is done automatically:
	$ sed -i "s/s3c_plat_otg_data/dwc2_plat_otg_data/g" \
		`git grep s3c_plat_otg_data | cut -d : -f 1`

Signed-off-by: Marek Vasut <marex@denx.de>
master
Marek Vasut 9 years ago
parent e30824f439
commit c0982871df
14 changed files with 16 additions and 16 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 2
      board/altera/arria5-socdk/socfpga.c
  2. 2
      board/altera/cyclone5-socdk/socfpga.c
  3. 2
      board/broadcom/bcm28155_ap/bcm28155_ap.c
  4. 2
      board/denx/mcvevk/socfpga.c
  5. 2
      board/ebv/socrates/socfpga.c
  6. 2
      board/samsung/goni/goni.c
  7. 2
      board/samsung/odroid/odroid.c
  8. 4
      board/samsung/trats/trats.c
  9. 2
      board/samsung/trats2/trats2.c
  10. 2
      board/samsung/universal_c210/universal.c
  11. 2
      board/terasic/sockit/socfpga.c
  12. 2
      drivers/usb/gadget/dwc2_udc_otg.c
  13. 2
      drivers/usb/gadget/dwc2_udc_otg_priv.h
  14. 4
      include/usb/s3c_udc.h

2
board/altera/arria5-socdk/socfpga.c
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@ -68,7 +68,7 @@ int board_phy_config(struct phy_device *phydev)
#endif
#ifdef CONFIG_USB_GADGET
struct s3c_plat_otg_data socfpga_otg_data = {
struct dwc2_plat_otg_data socfpga_otg_data = {
.regs_otg = CONFIG_USB_DWC2_REG_ADDR,
.usb_gusbcfg = 0x1417,
};

2
board/altera/cyclone5-socdk/socfpga.c
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@ -68,7 +68,7 @@ int board_phy_config(struct phy_device *phydev)
#endif
#ifdef CONFIG_USB_GADGET
struct s3c_plat_otg_data socfpga_otg_data = {
struct dwc2_plat_otg_data socfpga_otg_data = {
.regs_otg = CONFIG_USB_DWC2_REG_ADDR,
.usb_gusbcfg = 0x1417,
};

2
board/broadcom/bcm28155_ap/bcm28155_ap.c
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@ -95,7 +95,7 @@ int board_mmc_init(bd_t *bis)
#endif
#ifdef CONFIG_USB_GADGET
static struct s3c_plat_otg_data bcm_otg_data = {
static struct dwc2_plat_otg_data bcm_otg_data = {
.regs_otg = HSOTG_BASE_ADDR
};

2
board/denx/mcvevk/socfpga.c
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@ -28,7 +28,7 @@ int board_init(void)
}
#ifdef CONFIG_USB_GADGET
struct s3c_plat_otg_data socfpga_otg_data = {
struct dwc2_plat_otg_data socfpga_otg_data = {
.regs_otg = CONFIG_USB_DWC2_REG_ADDR,
.usb_gusbcfg = 0x1417,
};

2
board/ebv/socrates/socfpga.c
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@ -68,7 +68,7 @@ int board_phy_config(struct phy_device *phydev)
#endif
#ifdef CONFIG_USB_GADGET
struct s3c_plat_otg_data socfpga_otg_data = {
struct dwc2_plat_otg_data socfpga_otg_data = {
.regs_otg = CONFIG_USB_DWC2_REG_ADDR,
.usb_gusbcfg = 0x1417,
};

2
board/samsung/goni/goni.c
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@ -183,7 +183,7 @@ static int s5pc1xx_phy_control(int on)
return 0;
}
struct s3c_plat_otg_data s5pc110_otg_data = {
struct dwc2_plat_otg_data s5pc110_otg_data = {
.phy_control = s5pc1xx_phy_control,
.regs_phy = S5PC110_PHY_BASE,
.regs_otg = S5PC110_OTG_BASE,

2
board/samsung/odroid/odroid.c
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@ -452,7 +452,7 @@ static int s5pc210_phy_control(int on)
return regulator_set_mode(dev, OPMODE_LPM);
}
struct s3c_plat_otg_data s5pc210_otg_data = {
struct dwc2_plat_otg_data s5pc210_otg_data = {
.phy_control = s5pc210_phy_control,
.regs_phy = EXYNOS4X12_USBPHY_BASE,
.regs_otg = EXYNOS4X12_USBOTG_BASE,

4
board/samsung/trats/trats.c
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@ -41,7 +41,7 @@ u32 get_board_rev(void)
#endif
static void check_hw_revision(void);
struct s3c_plat_otg_data s5pc210_otg_data;
struct dwc2_plat_otg_data s5pc210_otg_data;
int exynos_init(void)
{
@ -419,7 +419,7 @@ static int s5pc210_phy_control(int on)
return 0;
}
struct s3c_plat_otg_data s5pc210_otg_data = {
struct dwc2_plat_otg_data s5pc210_otg_data = {
.phy_control = s5pc210_phy_control,
.regs_phy = EXYNOS4_USBPHY_BASE,
.regs_otg = EXYNOS4_USBOTG_BASE,

2
board/samsung/trats2/trats2.c
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@ -303,7 +303,7 @@ static int s5pc210_phy_control(int on)
return 0;
}
struct s3c_plat_otg_data s5pc210_otg_data = {
struct dwc2_plat_otg_data s5pc210_otg_data = {
.phy_control = s5pc210_phy_control,
.regs_phy = EXYNOS4X12_USBPHY_BASE,
.regs_otg = EXYNOS4X12_USBOTG_BASE,

2
board/samsung/universal_c210/universal.c
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@ -179,7 +179,7 @@ static int s5pc210_phy_control(int on)
return 0;
}
struct s3c_plat_otg_data s5pc210_otg_data = {
struct dwc2_plat_otg_data s5pc210_otg_data = {
.phy_control = s5pc210_phy_control,
.regs_phy = EXYNOS4_USBPHY_BASE,
.regs_otg = EXYNOS4_USBOTG_BASE,

2
board/terasic/sockit/socfpga.c
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@ -68,7 +68,7 @@ int board_phy_config(struct phy_device *phydev)
#endif
#ifdef CONFIG_USB_GADGET
struct s3c_plat_otg_data socfpga_otg_data = {
struct dwc2_plat_otg_data socfpga_otg_data = {
.regs_otg = CONFIG_USB_DWC2_REG_ADDR,
.usb_gusbcfg = 0x1417,
};

2
drivers/usb/gadget/dwc2_udc_otg.c
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@ -797,7 +797,7 @@ static struct dwc2_udc memory = {
* probe - binds to the platform device
*/
int s3c_udc_probe(struct s3c_plat_otg_data *pdata)
int s3c_udc_probe(struct dwc2_plat_otg_data *pdata)
{
struct dwc2_udc *dev = &memory;
int retval = 0;

2
drivers/usb/gadget/dwc2_udc_otg_priv.h
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@ -78,7 +78,7 @@ struct dwc2_udc {
struct usb_gadget gadget;
struct usb_gadget_driver *driver;
struct s3c_plat_otg_data *pdata;
struct dwc2_plat_otg_data *pdata;
int ep0state;
struct dwc2_ep ep[DWC2_MAX_ENDPOINTS];

4
include/usb/s3c_udc.h
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@ -11,7 +11,7 @@
#define PHY0_SLEEP (1 << 5)
struct s3c_plat_otg_data {
struct dwc2_plat_otg_data {
int (*phy_control)(int on);
unsigned int regs_phy;
unsigned int regs_otg;
@ -20,6 +20,6 @@ struct s3c_plat_otg_data {
unsigned int usb_gusbcfg;
};
int s3c_udc_probe(struct s3c_plat_otg_data *pdata);
int s3c_udc_probe(struct dwc2_plat_otg_data *pdata);
#endif

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