@ -1,5 +1,6 @@
/*
* Copyright 2008 - 2014 Freescale Semiconductor , Inc .
* Copyright 2008 - 2016 Freescale Semiconductor , Inc .
* Copyright 2017 - 2018 NXP Semiconductor
*
* SPDX - License - Identifier : GPL - 2.0 +
*/
@ -492,7 +493,7 @@ static void set_timing_cfg_3(const unsigned int ctrl_num,
| ( ( ext_pretoact & 0x1 ) < < 28 )
| ( ( ext_acttopre & 0x3 ) < < 24 )
| ( ( ext_acttorw & 0x1 ) < < 22 )
| ( ( ext_refrec & 0x1 F ) < < 16 )
| ( ( ext_refrec & 0x3 F ) < < 16 )
| ( ( ext_caslat & 0x3 ) < < 12 )
| ( ( ext_add_lat & 0x1 ) < < 10 )
| ( ( ext_wrrec & 0x1 ) < < 8 )
@ -885,7 +886,7 @@ static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
}
}
sr_ie = popts - > self_refresh_interrupt_en ;
num_pr = 1 ; /* Make this configurable */
num_pr = popts - > package_3ds + 1 ;
/*
* 8572 manual says
@ -1193,7 +1194,7 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
* need 0x500 to park .
*/
debug ( " FSLDDR: ddr_sdram_mode_9) = 0x%08x \n " , ddr - > ddr_sdram_mode_9 ) ;
debug ( " FSLDDR: ddr_sdram_mode_9 = 0x%08x \n " , ddr - > ddr_sdram_mode_9 ) ;
if ( unq_mrs_en ) { /* unique mode registers are supported */
for ( i = 1 ; i < CONFIG_CHIP_SELECTS_PER_CTRL ; i + + ) {
if ( ! rtt_park & &
@ -1270,7 +1271,7 @@ static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
| ( ( esdmode6 & 0xffff ) < < 16 )
| ( ( esdmode7 & 0xffff ) < < 0 )
) ;
debug ( " FSLDDR: ddr_sdram_mode_10) = 0x%08x \n " , ddr - > ddr_sdram_mode_10 ) ;
debug ( " FSLDDR: ddr_sdram_mode_10 = 0x%08x \n " , ddr - > ddr_sdram_mode_10 ) ;
if ( unq_mrs_en ) { /* unique mode registers are supported */
for ( i = 1 ; i < CONFIG_CHIP_SELECTS_PER_CTRL ; i + + ) {
switch ( i ) {
@ -1992,7 +1993,7 @@ static void set_timing_cfg_7(const unsigned int ctrl_num,
if ( ddr - > ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN & &
CONFIG_FSL_SDRAM_TYPE = = SDRAM_TYPE_DDR4 ) {
/* for DDR4 only */
par_lat = ( popts - > rcw_2 & 0xf ) + 1 ;
par_lat = ( ddr - > ddr_sdram_ rcw_2 & 0xf ) + 1 ;
debug ( " PAR_LAT = %u for mclk_ps = %d \n " , par_lat , mclk_ps ) ;
}
@ -2079,9 +2080,23 @@ static void set_timing_cfg_8(const unsigned int ctrl_num,
debug ( " FSLDDR: timing_cfg_8 = 0x%08x \n " , ddr - > timing_cfg_8 ) ;
}
static void set_timing_cfg_9 ( fsl_ddr_cfg_regs_t * ddr )
static void set_timing_cfg_9 ( const unsigned int ctrl_num ,
fsl_ddr_cfg_regs_t * ddr ,
const memctl_options_t * popts ,
const common_timing_params_t * common_dimm )
{
ddr - > timing_cfg_9 = 0 ;
unsigned int refrec_cid_mclk = 0 ;
unsigned int acttoact_cid_mclk = 0 ;
if ( popts - > package_3ds ) {
refrec_cid_mclk =
picos_to_mclk ( ctrl_num , common_dimm - > trfc_slr_ps ) ;
acttoact_cid_mclk = 4U ; /* tRRDS_slr */
}
ddr - > timing_cfg_9 = ( refrec_cid_mclk & 0x3ff ) < < 16 |
( acttoact_cid_mclk & 0xf ) < < 8 ;
debug ( " FSLDDR: timing_cfg_9 = 0x%08x \n " , ddr - > timing_cfg_9 ) ;
}
@ -2142,6 +2157,16 @@ static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr,
/* Disable MRS on parity error for RDIMMs */
ddr - > ddr_sdram_cfg_3 | = popts - > registered_dimm_en ? 1 : 0 ;
if ( popts - > package_3ds ) { /* only 2,4,8 are supported */
if ( ( popts - > package_3ds + 1 ) & 0x1 ) {
printf ( " Error: Unsupported 3DS DIMM with %d die \n " ,
popts - > package_3ds + 1 ) ;
} else {
ddr - > ddr_sdram_cfg_3 | = ( ( popts - > package_3ds + 1 ) > > 1 )
< < 4 ;
}
}
debug ( " FSLDDR: ddr_sdram_cfg_3 = 0x%08x \n " , ddr - > ddr_sdram_cfg_3 ) ;
}
# endif /* CONFIG_SYS_FSL_DDR4 */
@ -2548,7 +2573,7 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
set_timing_cfg_6 ( ddr ) ;
set_timing_cfg_7 ( ctrl_num , ddr , popts , common_dimm ) ;
set_timing_cfg_8 ( ctrl_num , ddr , popts , common_dimm , cas_latency ) ;
set_timing_cfg_9 ( ddr ) ;
set_timing_cfg_9 ( ctrl_num , ddr , popts , common_dimm ) ;
set_ddr_dq_mapping ( ddr , dimm_params ) ;
# endif