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@ -217,35 +217,57 @@ static void mctl_zq_calibration(struct dram_para *para) |
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struct sunxi_mctl_ctl_reg * const mctl_ctl = |
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; |
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int i; |
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u16 zq_val[6]; |
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u8 val; |
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if ((readl(SUNXI_SRAMC_BASE + 0x24) & 0xff) == 0 && |
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(readl(SUNXI_SRAMC_BASE + 0xf0) & 0x1) == 0) { |
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u32 reg_val; |
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writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]); |
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for (i = 0; i < 6; i++) { |
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u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf; |
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writel((zq << 20) | (zq << 16) | (zq << 12) | |
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(zq << 8) | (zq << 4) | (zq << 0), |
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&mctl_ctl->zqcr); |
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clrsetbits_le32(&mctl_ctl->zqcr, 0xffff, |
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CONFIG_DRAM_ZQ & 0xffff); |
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writel(PIR_CLRSR, &mctl_ctl->pir); |
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mctl_phy_init(PIR_ZCAL); |
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zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff; |
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writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]); |
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reg_val = readl(&mctl_ctl->zqdr[0]); |
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reg_val &= (0x1f << 16) | (0x1f << 0); |
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reg_val |= reg_val << 8; |
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writel(reg_val, &mctl_ctl->zqdr[0]); |
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writel(PIR_CLRSR, &mctl_ctl->pir); |
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mctl_phy_init(PIR_ZCAL); |
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reg_val = readl(&mctl_ctl->zqdr[1]); |
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reg_val &= (0x1f << 16) | (0x1f << 0); |
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reg_val |= reg_val << 8; |
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writel(reg_val, &mctl_ctl->zqdr[1]); |
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writel(reg_val, &mctl_ctl->zqdr[2]); |
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} else { |
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int i; |
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u16 zq_val[6]; |
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u8 val; |
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val = readl(&mctl_ctl->zqdr[0]) >> 24; |
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zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8; |
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} |
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writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]); |
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for (i = 0; i < 6; i++) { |
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u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf; |
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writel((zq << 20) | (zq << 16) | (zq << 12) | |
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(zq << 8) | (zq << 4) | (zq << 0), |
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&mctl_ctl->zqcr); |
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writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]); |
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writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]); |
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writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]); |
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writel(PIR_CLRSR, &mctl_ctl->pir); |
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mctl_phy_init(PIR_ZCAL); |
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zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff; |
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writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]); |
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writel(PIR_CLRSR, &mctl_ctl->pir); |
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mctl_phy_init(PIR_ZCAL); |
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val = readl(&mctl_ctl->zqdr[0]) >> 24; |
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zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8; |
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} |
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writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]); |
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writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]); |
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writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]); |
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} |
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} |
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static void mctl_set_cr(struct dram_para *para) |
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