@ -16,13 +16,15 @@ void lowlevel_init(void)
int arch_cpu_init ( void )
int arch_cpu_init ( void )
{
{
zynq_slcr_unlock ( ) ;
zynq_slcr_unlock ( ) ;
/* remap DDR to zero, FILTERSTART */
writel ( 0 , & scu_base - > filter_start ) ;
/* Device config APB, unlock the PCAP */
/* Device config APB, unlock the PCAP */
writel ( 0x757BDF0D , & devcfg_base - > unlock ) ;
writel ( 0x757BDF0D , & devcfg_base - > unlock ) ;
writel ( 0xFFFFFFFF , & devcfg_base - > rom_shadow ) ;
writel ( 0xFFFFFFFF , & devcfg_base - > rom_shadow ) ;
# if (CONFIG_SYS_SDRAM_BASE == 0)
/* remap DDR to zero, FILTERSTART */
writel ( 0 , & scu_base - > filter_start ) ;
/* OCM_CFG, Mask out the ROM, map ram into upper addresses */
/* OCM_CFG, Mask out the ROM, map ram into upper addresses */
writel ( 0x1F , & slcr_base - > ocm_cfg ) ;
writel ( 0x1F , & slcr_base - > ocm_cfg ) ;
/* FPGA_RST_CTRL, clear resets on AXI fabric ports */
/* FPGA_RST_CTRL, clear resets on AXI fabric ports */
@ -33,6 +35,7 @@ int arch_cpu_init(void)
writel ( 0x0 , & slcr_base - > ddr_urgent_sel ) ;
writel ( 0x0 , & slcr_base - > ddr_urgent_sel ) ;
/* Urgent write, ports S2/S3 */
/* Urgent write, ports S2/S3 */
writel ( 0xC , & slcr_base - > ddr_urgent ) ;
writel ( 0xC , & slcr_base - > ddr_urgent ) ;
# endif
zynq_slcr_lock ( ) ;
zynq_slcr_lock ( ) ;