From 8baa17832fa2406dc8dc36174d5ca5b06d39cb33 Mon Sep 17 00:00:00 2001 From: Stephen Arnold Date: Thu, 23 Mar 2017 18:58:08 -0700 Subject: [PATCH 01/17] ARM: socfpga: add fpga build and bsp handoff instructions to readme This patch adds the steps to manually (re)build a Quartus FPGA project, generate the required BSP glue, and update u-boot handoff files for mainline SPL support. Requires Quartus toolchain and current U-Boot. Signed-off-by: Steve Arnold Cc: Dinh Nguyen Cc: Stefan Roese Cc: Marek Vasut --- doc/README.socfpga | 141 +++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 136 insertions(+), 5 deletions(-) diff --git a/doc/README.socfpga b/doc/README.socfpga index cb805cf..cae0ef1 100644 --- a/doc/README.socfpga +++ b/doc/README.socfpga @@ -1,18 +1,149 @@ - --------------------------------------------- +---------------------------------------- SOCFPGA Documentation for U-Boot and SPL --------------------------------------------- +---------------------------------------- This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore based SOCFPGA. To know more about the hardware itself, please refer to www.altera.com. --------------------------------------------- socfpga_dw_mmc --------------------------------------------- +-------------- + Here are macro and detailed configuration required to enable DesignWare SDMMC controller support within SOCFPGA #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 -> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM + +-------------------------------------------------- +Generating the handoff header files for U-Boot SPL +-------------------------------------------------- + +This text is assuming quartus 16.1, but newer versions will probably work just fine too; +verified with DE1_SOC_Linux_FB demo project (https://github.com/VCTLabs/DE1_SOC_Linux_FB). +Updated/working projects should build using either process below. + +Note: it *should* work from Quartus 14.0.200 onwards, however, the current vendor demo +projects must have the IP cores updated as shown below. + +Rebuilding your Quartus project +------------------------------- + +Choose one of the follwing methods, either command line or GUI. + +Using the comaand line +~~~~~~~~~~~~~~~~~~~~~~ + +First run the embedded command shell, using your path to the Quartus install: + + $ /path/to/intelFPGA/16.1/embedded/embedded_command_shell.sh + +Then (if necessary) update the IP cores in the project, generate HDL code, and +build the project: + + $ cd path/to/project/dir + $ qsys-generate soc_system.qsys --upgrade-ip-cores + $ qsys-generate soc_system.qsys --synthesis=[VERILOG|VHDL] + $ quartus_sh --flow compile + +Convert the resulting .sof file (SRAM object file) to .rbf file (Raw bit file): + + $ quartus_cpf -c .sof soc_system.rbf + + +Generate BSP handoff files +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +You can run the bsp editor GUI below, or run the following command from the +project directory: + + $ /path/to/bsb/tools/bsp-create-settings --type spl --bsp-dir build \ + --preloader-settings-dir hps_isw_handoff/soc_system_hps_0/ \ + --settings build/settings.bsp + +You should use the bsp "build" directory above (ie, where the settings.bsp file is) +in the following u-boot command to update the board headers. Once these headers +are updated for a given project build, u-boot should be configured for the +project board (eg, de0-nano-sockit) and then build the normal spl build. + +Now you can skip the GUI section. + + +Using the Qsys GUI +~~~~~~~~~~~~~~~~~~ + +1. Navigate to your project directory +2. Run Quartus II +3. Open Project (Ctrl+J), select .qpf +4. Run QSys [Tools->QSys] + 4.1 In the Open dialog, select '.qsys' + 4.2 In the Open System dialog, wait until completion and press 'Close' + 4.3 In the Qsys window, click on 'Generate HDL...' in bottom right corner + 4.3.1 In the 'Generation' window, click 'Generate' + 4.3.2 In the 'Generate' dialog, wait until completion and click 'Close' + 4.4 In the QSys window, click 'Finish' + 4.4.1 In the 'Quartus II' pop up window, click 'OK' +5. Back in Quartus II main window, do the following + 5.1 Use Processing -> Start -> Start Analysis & Synthesis (Ctrl+K) + 5.2 Use Processing -> Start Compilation (Ctrl+L) + + ... this may take some time, have patience ... + +6. Start the embedded command shell as shown in the previous section + 6.1 Change directory to 'software/spl_bsp' + 6.2 Prepare BSP by launching the BSP editor from ECS + => bsp-editor + 6.3 In BSP editor + 6.3.1 Use File -> Open + 6.3.2 Select 'settings.bsp' file + 6.3.3 Click Generate + 6.3.4 Click Exit + + +Post handoff generation +~~~~~~~~~~~~~~~~~~~~~~~ + +Now that the handoff files are generated, U-Boot can be used to process +the handoff files generated by the bsp-editor. For this, please use the +following script from the u-boot source tree: + + $ ./arch/arm/mach-socfpga/qts-filter.sh \ + \ + \ + \ + + +Process QTS-generated files into U-Boot compatible ones. + + soc_type - Type of SoC, either 'cyclone5' or 'arria5'. + input_qts_dir - Directory with compiled Quartus project + and containing the Quartus project file (QPF). + input_bsp_dir - Directory with generated bsp containing + the settings.bsp file. + output_dir - Directory to store the U-Boot compatible + headers. + +This will generate (or update) the following 4 files: + + iocsr_config.h + pinmux_config.h + pll_config.h + sdram_config.h + +These files should be copied into "qts" directory in the board directory +(see output argument of qts-filter.sh command above). + +Here is an example for the DE-0 Nano SoC after the above rebuild process: + + $ ll board/terasic/de0-nano-soc/qts/ + total 36 + -rw-r--r-- 1 sarnold sarnold 8826 Mar 21 18:11 iocsr_config.h + -rw-r--r-- 1 sarnold sarnold 4398 Mar 21 18:11 pinmux_config.h + -rw-r--r-- 1 sarnold sarnold 3190 Mar 21 18:11 pll_config.h + -rw-r--r-- 1 sarnold sarnold 9022 Mar 21 18:11 sdram_config.h + +Note: file sizes will differ slightly depending on the selected board. + +Now your board is ready for full mainline support including U-Boot SPL. +The Preloader will not be needed any more. From 45fa6f1dd59bc6d213c6051d4ab45b0cb449eb5b Mon Sep 17 00:00:00 2001 From: Georges Savoundararadj Date: Mon, 27 Mar 2017 22:56:04 -0700 Subject: [PATCH 02/17] ARM: socfpga: cyclone5-socdk: Enable ports A & C With the port C enabled, we can read the GPI input state of: * the DIP switches (USER_DIPSW_HPS[3:0]/HPS_GPI[7:4]) * the push buttons (USER_PB_HPS[3:0]/HPS_GPI[11:8]) Signed-off-by: Georges Savoundararadj Signed-off by: Sid-Ali Teir Cc: Dinh Nguyen Cc: Marek Vasut --- arch/arm/dts/socfpga_cyclone5_socdk.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index d4df1a1..f175ef2 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -54,10 +54,18 @@ rxc-skew-ps = <2000>; }; +&gpio0 { + status = "okay"; +}; + &gpio1 { status = "okay"; }; +&gpio2 { + status = "okay"; +}; + &i2c0 { status = "okay"; From 4c0f3e7f7b7fc29d0bdbef20e849e3360c432891 Mon Sep 17 00:00:00 2001 From: "Chee, Tien Fong" Date: Wed, 29 Mar 2017 11:49:16 +0800 Subject: [PATCH 03/17] ARM: socfpga: boot0 hook: remove macro from boot0 header file Commit ce62e57fc571 ("ARM: boot0 hook: remove macro, include whole header file") miss out cleaning macro in this header file, and this has broken implementation of a boot header capability in socfpga SPL. Remove the macro in this file, and recovering it back to proper functioning. Fixes: ce62e57fc571 ("ARM: boot0 hook: remove macro, include whole header file") Signed-off-by: Chee, Tien Fong --- arch/arm/mach-socfpga/include/mach/boot0.h | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h b/arch/arm/mach-socfpga/include/mach/boot0.h index aaada31..22d9e7f 100644 --- a/arch/arm/mach-socfpga/include/mach/boot0.h +++ b/arch/arm/mach-socfpga/include/mach/boot0.h @@ -8,21 +8,17 @@ #define __BOOT0_H #ifdef CONFIG_SPL_BUILD -#define ARM_SOC_BOOT0_HOOK \ - .balignl 64,0xf33db33f; \ - \ - .word 0x1337c0d3; /* SoCFPGA preloader validation word */ \ - .word 0xc01df00d; /* Version, flags, length */ \ - .word 0xcafec0d3; /* Checksum, zero-pad */ \ - nop; \ - \ - b reset; /* SoCFPGA jumps here */ \ - nop; \ - nop; \ + .balignl 64,0xf33db33f; + + .word 0x1337c0d3; /* SoCFPGA preloader validation word */ + .word 0xc01df00d; /* Version, flags, length */ + .word 0xcafec0d3; /* Checksum, zero-pad */ nop; -#else -#define ARM_SOC_BOOT0_HOOK -#endif + b reset; /* SoCFPGA jumps here */ + nop; + nop; + nop; +#endif #endif /* __BOOT0_H */ From a548bc511f425c9f1213791d020be217221cbe4f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 5 Apr 2017 13:17:03 +0200 Subject: [PATCH 04/17] ARM: socfpga: Rename MCVEVK The board is now manufactured by Aries Embedded GmbH , rename it. Signed-off-by: Marek Vasut --- arch/arm/dts/socfpga_cyclone5_mcvevk.dts | 2 +- arch/arm/mach-socfpga/Kconfig | 10 +++++----- board/{denx => aries}/mcvevk/MAINTAINERS | 4 ++-- board/{denx => aries}/mcvevk/Makefile | 0 board/{denx => aries}/mcvevk/qts/iocsr_config.h | 0 board/{denx => aries}/mcvevk/qts/pinmux_config.h | 0 board/{denx => aries}/mcvevk/qts/pll_config.h | 0 board/{denx => aries}/mcvevk/qts/sdram_config.h | 0 board/{denx => aries}/mcvevk/socfpga.c | 0 configs/socfpga_mcvevk_defconfig | 2 +- include/configs/socfpga_mcvevk.h | 6 +++--- 11 files changed, 12 insertions(+), 12 deletions(-) rename board/{denx => aries}/mcvevk/MAINTAINERS (59%) rename board/{denx => aries}/mcvevk/Makefile (100%) rename board/{denx => aries}/mcvevk/qts/iocsr_config.h (100%) rename board/{denx => aries}/mcvevk/qts/pinmux_config.h (100%) rename board/{denx => aries}/mcvevk/qts/pll_config.h (100%) rename board/{denx => aries}/mcvevk/qts/sdram_config.h (100%) rename board/{denx => aries}/mcvevk/socfpga.c (100%) diff --git a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts index 7d3f989..1462f08 100644 --- a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts +++ b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts @@ -7,7 +7,7 @@ #include "socfpga_cyclone5.dtsi" / { - model = "DENX MCVEVK"; + model = "Aries MCVEVK"; compatible = "altr,socfpga-cyclone5", "altr,socfpga"; chosen { diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index e56b3db..18bb6dc 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -56,8 +56,8 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK bool "Altera SOCFPGA SoCDK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 -config TARGET_SOCFPGA_DENX_MCVEVK - bool "DENX MCVEVK (Cyclone V)" +config TARGET_SOCFPGA_ARIES_MCVEVK + bool "Aries MCVEVK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_EBV_SOCRATES @@ -97,7 +97,7 @@ config SYS_BOARD default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC default "is1" if TARGET_SOCFPGA_IS1 - default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK + default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "sr1500" if TARGET_SOCFPGA_SR1500 @@ -106,7 +106,7 @@ config SYS_BOARD config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK - default "denx" if TARGET_SOCFPGA_DENX_MCVEVK + default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO @@ -122,7 +122,7 @@ config SYS_CONFIG_NAME default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC default "socfpga_is1" if TARGET_SOCFPGA_IS1 - default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK + default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 diff --git a/board/denx/mcvevk/MAINTAINERS b/board/aries/mcvevk/MAINTAINERS similarity index 59% rename from board/denx/mcvevk/MAINTAINERS rename to board/aries/mcvevk/MAINTAINERS index 6787727..c3a3a2b 100644 --- a/board/denx/mcvevk/MAINTAINERS +++ b/board/aries/mcvevk/MAINTAINERS @@ -1,5 +1,5 @@ -SOCKIT BOARD -M: Marek Vasut +Aries MCVEVK BOARD +M: Marek Vasut S: Maintained F: include/configs/socfpga_mcvevk.h F: configs/socfpga_mcvevk_defconfig diff --git a/board/denx/mcvevk/Makefile b/board/aries/mcvevk/Makefile similarity index 100% rename from board/denx/mcvevk/Makefile rename to board/aries/mcvevk/Makefile diff --git a/board/denx/mcvevk/qts/iocsr_config.h b/board/aries/mcvevk/qts/iocsr_config.h similarity index 100% rename from board/denx/mcvevk/qts/iocsr_config.h rename to board/aries/mcvevk/qts/iocsr_config.h diff --git a/board/denx/mcvevk/qts/pinmux_config.h b/board/aries/mcvevk/qts/pinmux_config.h similarity index 100% rename from board/denx/mcvevk/qts/pinmux_config.h rename to board/aries/mcvevk/qts/pinmux_config.h diff --git a/board/denx/mcvevk/qts/pll_config.h b/board/aries/mcvevk/qts/pll_config.h similarity index 100% rename from board/denx/mcvevk/qts/pll_config.h rename to board/aries/mcvevk/qts/pll_config.h diff --git a/board/denx/mcvevk/qts/sdram_config.h b/board/aries/mcvevk/qts/sdram_config.h similarity index 100% rename from board/denx/mcvevk/qts/sdram_config.h rename to board/aries/mcvevk/qts/sdram_config.h diff --git a/board/denx/mcvevk/socfpga.c b/board/aries/mcvevk/socfpga.c similarity index 100% rename from board/denx/mcvevk/socfpga.c rename to board/aries/mcvevk/socfpga.c diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index b16ee1c..627b90f 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_TARGET_SOCFPGA_DENX_MCVEVK=y +CONFIG_TARGET_SOCFPGA_ARIES_MCVEVK=y CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk" CONFIG_FIT=y diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h index 3c9ba6d..604ea20 100644 --- a/include/configs/socfpga_mcvevk.h +++ b/include/configs/socfpga_mcvevk.h @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_DENX_MCVEVK_H__ -#define __CONFIG_DENX_MCVEVK_H__ +#ifndef __CONFIG_ARIES_MCVEVK_H__ +#define __CONFIG_ARIES_MCVEVK_H__ #include @@ -105,4 +105,4 @@ /* The rest of the configuration is shared */ #include -#endif /* __CONFIG_DENX_MCVEVK_H__ */ +#endif /* __CONFIG_ARIES_MCVEVK_H__ */ From 55ce55faaa2f8cb267fa1346f31079a0befca1a8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 29 Oct 2016 21:15:56 +0200 Subject: [PATCH 05/17] ARM: socfpga: Reduce the DFU buffer size There is no point in having such gargantuan buffer, it only requires huge malloc area. Reduce the DFU buffer size. Signed-off-by: Marek Vasut --- include/configs/socfpga_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 8472b52..8057b88 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -230,7 +230,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) #define CONFIG_USB_FUNCTION_MASS_STORAGE -#define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024) +#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) #define DFU_DEFAULT_POLL_TIMEOUT 300 /* USB IDs */ From d70b338ec670764e4a69598efb7dec0dc5c7a753 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 29 Oct 2016 22:08:39 +0200 Subject: [PATCH 06/17] ARM: socfpga: mcvevk: Add default dfu_alt_info Add default DFU altinfo for eMMC. Signed-off-by: Marek Vasut --- include/configs/socfpga_mcvevk.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h index 604ea20..2d36702 100644 --- a/include/configs/socfpga_mcvevk.h +++ b/include/configs/socfpga_mcvevk.h @@ -37,6 +37,7 @@ "netdev=eth0\0" \ "hostname=mcvevk\0" \ "kernel_addr_r=0x10000000\0" \ + "dfu_alt_info=mmc raw 0 3867148288\0" \ "update_filename=u-boot-with-spl.sfp\0" \ "update_sd_offset=0x800\0" \ "update_sd=" /* Update the SD firmware partition */ \ From cc62ac7578917b0a518c2e56111046c820d6cfa5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 5 Dec 2016 18:17:52 +0100 Subject: [PATCH 07/17] ARM: socfpga: Disable OC on MCVEVK Disable the OC test on MCVEVK as the old PHY version does not provide this information. This fixes the USB OTG operation. Signed-off-by: Marek Vasut --- arch/arm/dts/socfpga_cyclone5_mcvevk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts index 1462f08..833a87d 100644 --- a/arch/arm/dts/socfpga_cyclone5_mcvevk.dts +++ b/arch/arm/dts/socfpga_cyclone5_mcvevk.dts @@ -54,5 +54,6 @@ }; &usb1 { + disable-over-current; status = "okay"; }; From e11b5e8d6ef72f2e83e680d132a0617a4540f0aa Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Wed, 5 Apr 2017 17:32:47 +0800 Subject: [PATCH 08/17] fdt: Add compatible strings for Arria 10 Add compatible strings for Intel Arria 10 SoCFPGA device. Signed-off-by: Tien Fong Chee Signed-off-by: Ley Foon Tan --- include/fdtdec.h | 8 ++++++++ lib/fdtdec.c | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/include/fdtdec.h b/include/fdtdec.h index d074478..2134701 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -155,6 +155,14 @@ enum fdt_compat_id { COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */ COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */ COMPAT_SUNXI_NAND, /* SUNXI NAND controller */ + COMPAT_ALTERA_SOCFPGA_CLK, /* SoCFPGA Clock initialization */ + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE, /* SoCFPGA pinctrl-single */ + COMPAT_ALTERA_SOCFPGA_H2F_BRG, /* SoCFPGA hps2fpga bridge */ + COMPAT_ALTERA_SOCFPGA_LWH2F_BRG, /* SoCFPGA lwhps2fpga bridge */ + COMPAT_ALTERA_SOCFPGA_F2H_BRG, /* SoCFPGA fpga2hps bridge */ + COMPAT_ALTERA_SOCFPGA_F2SDR0, /* SoCFPGA fpga2SDRAM0 bridge */ + COMPAT_ALTERA_SOCFPGA_F2SDR1, /* SoCFPGA fpga2SDRAM1 bridge */ + COMPAT_ALTERA_SOCFPGA_F2SDR2, /* SoCFPGA fpga2SDRAM2 bridge */ COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 1edfbf2..94372cc 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -66,6 +66,14 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"), COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"), COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"), + COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"), + COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"), + COMPAT(ALTERA_SOCFPGA_H2F_BRG, "altr,socfpga-hps2fpga-bridge"), + COMPAT(ALTERA_SOCFPGA_LWH2F_BRG, "altr,socfpga-lwhps2fpga-bridge"), + COMPAT(ALTERA_SOCFPGA_F2H_BRG, "altr,socfpga-fpga2hps-bridge"), + COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"), + COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"), + COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) From 707cd012e2e1dbed7150f7908727abb7bdc4c1a7 Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Wed, 5 Apr 2017 17:32:51 +0800 Subject: [PATCH 09/17] arm: socfpga: Convert Altera DDR SDRAM driver to use Kconfig Convert Altera DDR SDRAM driver to use Kconfig method. Enable ALTERA_SDRAM by default if it is on Gen5 target. Arria 10 will have different driver. Signed-off-by: Tien Fong Chee Signed-off-by: Ley Foon Tan --- arch/arm/mach-socfpga/Kconfig | 1 + drivers/Kconfig | 2 ++ drivers/ddr/Kconfig | 1 + drivers/ddr/altera/Kconfig | 5 +++++ drivers/ddr/altera/Makefile | 4 +++- include/configs/socfpga_common.h | 5 ----- 6 files changed, 12 insertions(+), 6 deletions(-) create mode 100644 drivers/ddr/Kconfig create mode 100644 drivers/ddr/altera/Kconfig diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 18bb6dc..9bfee04 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -43,6 +43,7 @@ config TARGET_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_GEN5 bool + select ALTERA_SDRAM choice prompt "Altera SOCFPGA board select" diff --git a/drivers/Kconfig b/drivers/Kconfig index 0e5d97d..3e6bbac 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -14,6 +14,8 @@ source "drivers/cpu/Kconfig" source "drivers/crypto/Kconfig" +source "drivers/ddr/Kconfig" + source "drivers/demo/Kconfig" source "drivers/ddr/fsl/Kconfig" diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig new file mode 100644 index 0000000..b764add --- /dev/null +++ b/drivers/ddr/Kconfig @@ -0,0 +1 @@ +source "drivers/ddr/altera/Kconfig" diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig new file mode 100644 index 0000000..021ec1d --- /dev/null +++ b/drivers/ddr/altera/Kconfig @@ -0,0 +1,5 @@ +config ALTERA_SDRAM + bool "SoCFPGA DDR SDRAM driver" + depends on TARGET_SOCFPGA_GEN5 + help + Enable DDR SDRAM controller for the SoCFPGA devices. diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index 1ca7058..bdd2872 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -8,4 +8,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_ALTERA_SDRAM) += sdram.o sequencer.o +ifdef CONFIG_ALTERA_SDRAM +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram.o sequencer.o +endif diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 8057b88..d4d72fa 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -72,11 +72,6 @@ #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS /* - * SDRAM controller - */ -#define CONFIG_ALTERA_SDRAM - -/* * EPCS/EPCQx1 Serial Flash Controller */ #ifdef CONFIG_ALTERA_SPI From 451e8241259d83a50ee8f240842a05731499d2e1 Mon Sep 17 00:00:00 2001 From: Dalon Westergreen Date: Thu, 13 Apr 2017 07:30:29 -0700 Subject: [PATCH 10/17] arm: socfpga: Add distro boot to socfpga common header This adds a common environment and support for distro boot in the common socfpga header. Signed-off-by: Dalon Westergreen Acked-by: Marek Vasut -- Changes in v5: - Per Frank, to support OpenSuse the ENV must be after the GPT Changes in v4: - Move env back to being right after the MBR Changes in v3: - fix spacing between asterix - remove verify=n as a default setting Changes in v2: - Remove unneeded CONFIG_BOOTFILE and fdt_addr - cleanup spacing in MMC env size common Signed-off-by: Dalon Westergreen --- include/configs/socfpga_common.h | 52 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 48 insertions(+), 4 deletions(-) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index d4d72fa..107c6d5 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -65,6 +65,9 @@ #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD #endif +#define CONFIG_CMD_PXE +#define CONFIG_MENU + /* * Cache */ @@ -237,13 +240,13 @@ unsigned int cm_get_qspi_controller_clk_hz(void); * U-Boot environment */ #if !defined(CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_SIZE (8 * 1024) #endif /* Environment for SDMMC boot */ #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) -#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ -#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */ #endif /* Environment for QSPI boot */ @@ -300,8 +303,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#endif +#else +#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 #endif #endif @@ -323,4 +330,41 @@ unsigned int cm_get_qspi_controller_clk_hz(void); */ #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +/* Extra Environment */ +#ifndef CONFIG_SPL_BUILD +#include + +#ifdef CONFIG_CMD_PXE +#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) +#else +#define BOOT_TARGET_DEVICES_PXE(func) +#endif + +#ifdef CONFIG_CMD_MMC +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_PXE(func) \ + func(DHCP, dhcp, na) + +#include + +#ifndef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "bootm_size=0xa000000\0" \ + "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ + "fdt_addr_r=0x02000000\0" \ + "scriptaddr=0x02100000\0" \ + "pxefile_addr_r=0x02200000\0" \ + "ramdisk_addr_r=0x02300000\0" \ + BOOTENV + +#endif +#endif + #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ From 29c06551737449c94bcc142e01f753d94893c83d Mon Sep 17 00:00:00 2001 From: Dalon Westergreen Date: Thu, 13 Apr 2017 07:30:30 -0700 Subject: [PATCH 11/17] arm: socfpga: DE0 use environment in common header This removes the default environment from the de0 headers and instead uses the common environment provided in socfpga_common.h which now uses distro boot. In addition to the above, add support to boot from the custom a2 type partition Signed-off-by: Dalon Westergreen Acked-by: Marek Vasut -- Changes in v2: - Remove unneeded CONFIG_BOOTFILE --- configs/socfpga_de0_nano_soc_defconfig | 3 +++ include/configs/socfpga_de0_nano_soc.h | 20 -------------------- 2 files changed, 3 insertions(+), 20 deletions(-) diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index af41e1e..b122135 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc" +CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de0_nano_soc.dtb" CONFIG_FIT=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y @@ -58,3 +59,5 @@ CONFIG_G_DNL_MANUFACTURER="terasic" CONFIG_G_DNL_VENDOR_NUM=0x0525 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 CONFIG_USE_TINY_PRINTF=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE=0xa2 \ No newline at end of file diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h index f655972..dd5933d 100644 --- a/include/configs/socfpga_de0_nano_soc.h +++ b/include/configs/socfpga_de0_nano_soc.h @@ -16,9 +16,6 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ /* Booting Linux */ -#define CONFIG_BOOTFILE "fitImage" -#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) -#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR @@ -30,23 +27,6 @@ #define CONFIG_ENV_IS_IN_MMC -/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "bootimage=zImage\0" \ - "fdt_addr=100\0" \ - "fdtimage=socfpga.dtb\0" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "mmcroot=/dev/mmcblk0p2\0" \ - "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${mmcroot} rw rootwait;" \ - "bootz ${loadaddr} - ${fdt_addr}\0" \ - "mmcload=mmc rescan;" \ - "load mmc 0:1 ${loadaddr} ${bootimage};" \ - "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ - /* The rest of the configuration is shared */ #include From 57b6b62f56fb56584067d81f77f72d8baee50a95 Mon Sep 17 00:00:00 2001 From: Dalon Westergreen Date: Thu, 13 Apr 2017 07:30:31 -0700 Subject: [PATCH 12/17] arm: socfpga: A5 SoCDK use environment in common header This removes the default environment from the A5 socdk headers and instead uses the common environment provided in socfpga_common.h which now uses distro boot. Add support to boot from the custom a2 type partition. Change default devicetree name to match devicetree name in upstream kernel source. Signed-off-by: Dalon Westergreen Acked-by: Marek Vasut -- Changes in v3: - Fix small typo in defconfig, missing "C" Changes in v2: - Remove unneeded CONFIG_BOOTFILE - Fix dtb name a5config test Signed-off-by: Dalon Westergreen --- configs/socfpga_arria5_defconfig | 3 +++ include/configs/socfpga_arria5_socdk.h | 32 -------------------------------- 2 files changed, 3 insertions(+), 32 deletions(-) diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index 43c51fe..5aa8e25 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk" +CONFIG_DEFAULT_FDT_FILE="socfpga_arria5_socdk.dtb" CONFIG_FIT=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y @@ -64,3 +65,5 @@ CONFIG_G_DNL_MANUFACTURER="altera" CONFIG_G_DNL_VENDOR_NUM=0x0525 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 CONFIG_USE_TINY_PRINTF=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE=0xa2 diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h index 9b1f753..b60d007 100644 --- a/include/configs/socfpga_arria5_socdk.h +++ b/include/configs/socfpga_arria5_socdk.h @@ -16,13 +16,6 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ /* Booting Linux */ -#define CONFIG_BOOTFILE "zImage" -#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_BOOTCOMMAND "run ramboot" -#else -#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" -#endif #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR @@ -34,31 +27,6 @@ #define CONFIG_ENV_IS_IN_MMC -/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=n\0" \ - "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "bootimage=zImage\0" \ - "fdt_addr=100\0" \ - "fdtimage=socfpga.dtb\0" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "mmcroot=/dev/mmcblk0p2\0" \ - "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${mmcroot} rw rootwait;" \ - "bootz ${loadaddr} - ${fdt_addr}\0" \ - "mmcload=mmc rescan;" \ - "load mmc 0:1 ${loadaddr} ${bootimage};" \ - "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ - "qspiload=sf probe && mtdparts default && run ubiload\0" \ - "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ - " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\ - "bootz ${loadaddr} - ${fdt_addr}\0" \ - "ubiload=ubi part UBI && ubifsmount ubi0 && " \ - "ubifsload ${loadaddr} /boot/${bootimage} && " \ - "ubifsload ${fdt_addr} /boot/${fdtimage}\0" - /* The rest of the configuration is shared */ #include From 5e7ae1afb2cc05ed84218216d0cba17625e6fc4f Mon Sep 17 00:00:00 2001 From: Dalon Westergreen Date: Thu, 13 Apr 2017 07:30:32 -0700 Subject: [PATCH 13/17] arm: socfpga: C5 SoCDK use environment in common header This removes the default environment from the C5 SoCDK headers and instead uses the common environment provided in socfpga_common.h which now uses distro boot. In addition to the above, add support to boot from the custom a2 type partition. Change default devicetree name to match devicetree name in upstream kernel source. Signed-off-by: Dalon Westergreen Acked-by: Marek Vasut -- Changes in v2: - Remove unneeded CONFIG_BOOTFILE --- configs/socfpga_cyclone5_defconfig | 3 +++ include/configs/socfpga_cyclone5_socdk.h | 32 -------------------------------- 2 files changed, 3 insertions(+), 32 deletions(-) diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 8b050b9..c8b8084 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk" +CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_socdk.dtb" CONFIG_FIT=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y @@ -64,3 +65,5 @@ CONFIG_G_DNL_MANUFACTURER="altera" CONFIG_G_DNL_VENDOR_NUM=0x0525 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 CONFIG_USE_TINY_PRINTF=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE=0xa2 diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h index 4100ef9..dfe4980 100644 --- a/include/configs/socfpga_cyclone5_socdk.h +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -16,13 +16,6 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ /* Booting Linux */ -#define CONFIG_BOOTFILE "zImage" -#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_BOOTCOMMAND "run ramboot" -#else -#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" -#endif #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR @@ -34,31 +27,6 @@ #define CONFIG_ENV_IS_IN_MMC -/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=n\0" \ - "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "bootimage=zImage\0" \ - "fdt_addr=100\0" \ - "fdtimage=socfpga.dtb\0" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "mmcroot=/dev/mmcblk0p2\0" \ - "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${mmcroot} rw rootwait;" \ - "bootz ${loadaddr} - ${fdt_addr}\0" \ - "mmcload=mmc rescan;" \ - "load mmc 0:1 ${loadaddr} ${bootimage};" \ - "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ - "qspiload=sf probe && mtdparts default && run ubiload\0" \ - "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ - " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\ - "bootz ${loadaddr} - ${fdt_addr}\0" \ - "ubiload=ubi part UBI && ubifsmount ubi0 && " \ - "ubifsload ${loadaddr} /boot/${bootimage} && " \ - "ubifsload ${fdt_addr} /boot/${fdtimage}\0" - /* The rest of the configuration is shared */ #include From 9e41d225ca55f21f2801137d5d041d54f44dc3cd Mon Sep 17 00:00:00 2001 From: Dalon Westergreen Date: Thu, 13 Apr 2017 07:30:33 -0700 Subject: [PATCH 14/17] arm: socfpga: DE1 use environment in common header This removes the default environment from the de1 headers and instead uses the common environment provided in socfpga_common.h which now uses distro boot. This board does not have a devicetree in the upstream kernel source so set devicetree to socfpga_cyclone5_de1_soc.dtb. Signed-off-by: Dalon Westergreen Acked-by: Marek Vasut -- Changes in V2: - Remove unneeded CONFIG_BOOTFILE - set devicetree name to match socfpga_{fpga model}_{board model}.dts pattern --- configs/socfpga_de1_soc_defconfig | 1 + include/configs/socfpga_de1_soc.h | 20 -------------------- 2 files changed, 1 insertion(+), 20 deletions(-) diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig index 135dfac..211ea41 100644 --- a/configs/socfpga_de1_soc_defconfig +++ b/configs/socfpga_de1_soc_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_SOCFPGA_TERASIC_DE1_SOC=y CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc" +CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de1_soc.dtb" CONFIG_FIT=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y diff --git a/include/configs/socfpga_de1_soc.h b/include/configs/socfpga_de1_soc.h index c6e8d81..014828b 100644 --- a/include/configs/socfpga_de1_soc.h +++ b/include/configs/socfpga_de1_soc.h @@ -16,9 +16,6 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ /* Booting Linux */ -#define CONFIG_BOOTFILE "fitImage" -#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) -#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR @@ -30,23 +27,6 @@ #define CONFIG_ENV_IS_IN_MMC -/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ - "bootm ${loadaddr} - ${fdtaddr}\0" \ - "bootimage=zImage\0" \ - "fdtaddr=100\0" \ - "fdtimage=socfpga.dtb\0" \ - "bootm ${loadaddr} - ${fdtaddr}\0" \ - "mmcroot=/dev/mmcblk0p2\0" \ - "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${mmcroot} rw rootwait;" \ - "bootz ${loadaddr} - ${fdtaddr}\0" \ - "mmcload=mmc rescan;" \ - "load mmc 0:1 ${loadaddr} ${bootimage};" \ - "load mmc 0:1 ${fdtaddr} ${fdtimage}\0" \ - /* The rest of the configuration is shared */ #include From b52acd8f9793bd23d5c3a1844c5f311ad6fad82e Mon Sep 17 00:00:00 2001 From: Dalon Westergreen Date: Thu, 13 Apr 2017 07:30:34 -0700 Subject: [PATCH 15/17] arm: socfpga: SoCKit use environment in common header This removes the default environment from the SoCKit headers and instead uses the common environment provided in socfpga_common.h which now uses distro boot. Change default devicetree name to match devicetree name in upstream kernel source. Signed-off-by: Dalon Westergreen Acked-by: Marek Vasut -- Changes in v2: - Remove unneeded CONFIG_BOOTFILE --- configs/socfpga_sockit_defconfig | 1 + include/configs/socfpga_sockit.h | 28 ---------------------------- 2 files changed, 1 insertion(+), 28 deletions(-) diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index d0c2bda..bf60783 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit" +CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_sockit.dtb" CONFIG_FIT=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h index 326310b..c9fc5c9 100644 --- a/include/configs/socfpga_sockit.h +++ b/include/configs/socfpga_sockit.h @@ -16,9 +16,6 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ /* Booting Linux */ -#define CONFIG_BOOTFILE "fitImage" -#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) -#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR @@ -30,31 +27,6 @@ #define CONFIG_ENV_IS_IN_MMC -/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=n\0" \ - "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "bootimage=zImage\0" \ - "fdt_addr=100\0" \ - "fdtimage=socfpga.dtb\0" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "mmcroot=/dev/mmcblk0p2\0" \ - "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${mmcroot} rw rootwait;" \ - "bootz ${loadaddr} - ${fdt_addr}\0" \ - "mmcload=mmc rescan;" \ - "load mmc 0:1 ${loadaddr} ${bootimage};" \ - "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ - "qspiload=sf probe && mtdparts default && run ubiload\0" \ - "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ - " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\ - "bootz ${loadaddr} - ${fdt_addr}\0" \ - "ubiload=ubi part UBI && ubifsmount ubi0 && " \ - "ubifsload ${loadaddr} /boot/${bootimage} && " \ - "ubifsload ${fdt_addr} /boot/${fdtimage}\0" - /* The rest of the configuration is shared */ #include From 19a8fed57cd988cffa0beefcf4fce9a6512a162d Mon Sep 17 00:00:00 2001 From: Dalon Westergreen Date: Thu, 13 Apr 2017 07:30:35 -0700 Subject: [PATCH 16/17] arm: socfpga: Socrates use environment in common header This removes the default environment from the socrates headers and instead uses the common environment provided in socfpga_common.h which now uses distro boot. Change default devicetree name to match devicetree name in upstream kernel source. Signed-off-by: Dalon Westergreen Acked-by: Marek Vasut -- Changes in v2: - Remove unneeded CONFIG_BOOTFILE --- configs/socfpga_socrates_defconfig | 1 + include/configs/socfpga_socrates.h | 26 -------------------------- 2 files changed, 1 insertion(+), 26 deletions(-) diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index e9276f9..4246ad6 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates" +CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_socrates.dtb" CONFIG_FIT=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h index 90343b7..5dc9298 100644 --- a/include/configs/socfpga_socrates.h +++ b/include/configs/socfpga_socrates.h @@ -16,9 +16,6 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCrates */ /* Booting Linux */ -#define CONFIG_BOOTFILE "zImage" -#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) -#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR @@ -30,29 +27,6 @@ #define CONFIG_ENV_IS_IN_MMC -/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=n\0" \ - "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "bootimage=zImage\0" \ - "fdt_addr=100\0" \ - "fdtimage=socfpga.dtb\0" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "mmcroot=/dev/mmcblk0p2\0" \ - "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${mmcroot} rw rootwait;" \ - "bootz ${loadaddr} - ${fdt_addr}\0" \ - "mmcload=mmc rescan;" \ - "load mmc 0:1 ${loadaddr} ${bootimage};" \ - "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ - "qspiroot=/dev/mtdblock0\0" \ - "qspirootfstype=jffs2\0" \ - "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ - "bootm ${loadaddr} - ${fdt_addr}\0" - /* The rest of the configuration is shared */ #include From 09397d99edb402c04d1e20b32989b5b2ecbb037a Mon Sep 17 00:00:00 2001 From: Dalon Westergreen Date: Thu, 13 Apr 2017 07:30:36 -0700 Subject: [PATCH 17/17] arm: socfpga: sr1500 use environment in common header This removes the default environment from the sr1500 header and instead uses the common environment provided in socfpga_common.h which now uses distro boot. This board has no upstream devicetree in the kernel source, so set to socfpga_cyclone5_sr1500.dtb. Signed-off-by: Dalon Westergreen Acked-by: Marek Vasut -- Changes in v2: - Remove unneeded CONFIG_BOOTFILE - set devicetree name to match socfpga_{fpga model}_{board model}.dts pattern --- configs/socfpga_sr1500_defconfig | 1 + include/configs/socfpga_sr1500.h | 28 ---------------------------- 2 files changed, 1 insertion(+), 28 deletions(-) diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index 981600b..ac1ed53 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_SOCFPGA_SR1500=y CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500" +CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_sr1500.dtb" CONFIG_FIT=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h index f67fafd..64e1595 100644 --- a/include/configs/socfpga_sr1500.h +++ b/include/configs/socfpga_sr1500.h @@ -16,9 +16,6 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */ /* Booting Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) -#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR @@ -28,31 +25,6 @@ #define CONFIG_PHY_MARVELL #define PHY_ANEG_TIMEOUT 8000 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=n\0" \ - "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "bootimage=zImage\0" \ - "fdt_addr=100\0" \ - "fdtimage=socfpga.dtb\0" \ - "fsloadcmd=ext2load\0" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "mmcroot=/dev/mmcblk0p2\0" \ - "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${mmcroot} rw rootwait;" \ - "bootz ${loadaddr} - ${fdt_addr}\0" \ - "mmcload=mmc rescan;" \ - "load mmc 0:1 ${loadaddr} ${bootimage};" \ - "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ - "qspiload=sf probe && mtdparts default && run ubiload\0" \ - "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ - " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\ - "bootz ${loadaddr} - ${fdt_addr}\0" \ - "ubiload=ubi part UBI && ubifsmount ubi0 && " \ - "ubifsload ${loadaddr} /boot/${bootimage} && " \ - "ubifsload ${fdt_addr} /boot/${fdtimage}\0" - /* Environment */ #define CONFIG_ENV_IS_IN_SPI_FLASH