Tom Rini
7 years ago
commit
c1b62ba9ca
@ -0,0 +1,34 @@ |
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/* |
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* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH |
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* |
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* SPDX-License-Identifier: GPL-2.0+ X11 |
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*/ |
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|
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&pinctrl { |
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u-boot,dm-pre-reloc; |
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}; |
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|
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&service_msch { |
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u-boot,dm-pre-reloc; |
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}; |
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|
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&dmc { |
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u-boot,dm-pre-reloc; |
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status = "okay"; |
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}; |
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|
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&pmugrf { |
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u-boot,dm-pre-reloc; |
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}; |
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|
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&cru { |
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u-boot,dm-pre-reloc; |
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}; |
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|
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&grf { |
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u-boot,dm-pre-reloc; |
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}; |
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|
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&uart2 { |
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u-boot,dm-pre-reloc; |
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}; |
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@ -0,0 +1,93 @@ |
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/* |
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* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH |
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* |
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* SPDX-License-Identifier: GPL-2.0+ X11 |
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*/ |
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|
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/ { |
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config { |
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u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */ |
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u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */ |
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}; |
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|
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chosen { |
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stdout-path = "serial0:115200n8"; |
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u-boot,spl-boot-order = &emmc, &sdmmc; |
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}; |
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|
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}; |
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|
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&pinctrl { |
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u-boot,dm-pre-reloc; |
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}; |
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|
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&service_msch { |
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u-boot,dm-pre-reloc; |
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}; |
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|
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&dmc { |
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u-boot,dm-pre-reloc; |
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|
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/* |
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* Validation of throughput using SPEC2000 shows the following |
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* relative performance for the different memory schedules: |
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* - CBDR: 30.1 |
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* - CBRD: 29.8 |
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* - CRBD: 29.9 |
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* Note that the best performance for any given application workload |
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* may vary from the default configured here (e.g. 164.gzip is fastest |
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* with CBRD, whereas 252.eon and 186.crafty are fastest with CRBD). |
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* |
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* See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for |
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* details on the 'rockchip,memory-schedule' property and how it |
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* affects the physical-address to device-address mapping. |
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*/ |
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rockchip,memory-schedule = <DMC_MSCH_CBDR>; |
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rockchip,ddr-frequency = <800000000>; |
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rockchip,ddr-speed-bin = <DDR3_1600K>; |
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status = "okay"; |
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}; |
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|
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&pmugrf { |
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u-boot,dm-pre-reloc; |
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}; |
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|
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&sgrf { |
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u-boot,dm-pre-reloc; |
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}; |
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|
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&cru { |
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u-boot,dm-pre-reloc; |
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}; |
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|
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&grf { |
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u-boot,dm-pre-reloc; |
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}; |
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|
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&uart0 { |
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u-boot,dm-pre-reloc; |
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}; |
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|
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&emmc { |
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u-boot,dm-pre-reloc; |
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}; |
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&sdmmc { |
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u-boot,dm-pre-reloc; |
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}; |
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|
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&spi1 { |
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u-boot,dm-pre-reloc; |
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|
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spiflash: w25q32dw@0 { |
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u-boot,dm-pre-reloc; |
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}; |
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}; |
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|
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&timer0 { |
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u-boot,dm-pre-reloc; |
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clock-frequency = <24000000>; |
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}; |
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|
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@ -0,0 +1,195 @@ |
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/* |
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* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH |
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* |
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* SPDX-License-Identifier: GPL-2.0+ X11 |
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*/ |
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|
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/dts-v1/; |
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#include "rk3368.dtsi" |
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#include "rk3368-lion-u-boot.dtsi" |
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#include <dt-bindings/input/input.h> |
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|
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/ { |
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model = "Theobroma Systems RK3368-uQ7 SoM"; |
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compatible = "tsd,rk3368-uq7", "tsd,lion", "rockchip,rk3368"; |
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|
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aliases { |
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mmc0 = &emmc; |
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mmc1 = &sdmmc; |
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}; |
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memory@0 { |
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device_type = "memory"; |
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reg = <0x0 0x0 0x0 0x80000000>; |
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}; |
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ext_gmac: gmac-clk { |
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compatible = "fixed-clock"; |
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clock-frequency = <125000000>; |
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clock-output-names = "ext_gmac"; |
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#clock-cells = <0>; |
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}; |
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vcc_sys: vcc-sys-regulator { |
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compatible = "regulator-fixed"; |
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regulator-name = "vcc_sys"; |
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regulator-min-microvolt = <5000000>; |
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regulator-max-microvolt = <5000000>; |
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regulator-always-on; |
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regulator-boot-on; |
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}; |
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}; |
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|
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&uart0 { |
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status = "okay"; |
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}; |
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&emmc { |
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status = "okay"; |
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bus-width = <8>; |
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cap-mmc-highspeed; |
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clock-frequency = <150000000>; |
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disable-wp; |
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keep-power-in-suspend; |
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non-removable; |
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num-slots = <1>; |
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vmmc-supply = <&vcc33_io>; |
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vqmmc-supply = <&vcc18_io>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; |
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}; |
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&sdmmc { |
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status = "okay"; |
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}; |
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&gmac { |
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status = "okay"; |
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phy-supply = <&vcc33_io>; |
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phy-mode = "rgmii"; |
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clock_in_out = "input"; |
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snps,reset-gpio = <&gpio3 11 GPIO_ACTIVE_LOW>; |
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snps,reset-active-low; |
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snps,reset-delays-us = <2 10000 50000>; |
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assigned-clocks = <&cru SCLK_MAC>; |
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assigned-clock-parents = <&ext_gmac>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&rgmii_pins>; |
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tx_delay = <0x10>; |
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rx_delay = <0x10>; |
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}; |
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&i2c0 { |
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status = "okay"; |
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rk808: pmic@1b { |
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compatible = "rockchip,rk808"; |
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reg = <0x1b>; |
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interrupt-parent = <&gpio0>; |
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interrupts = <5 IRQ_TYPE_LEVEL_LOW>; |
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rockchip,system-power-controller; |
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vcc1-supply = <&vcc_sys>; |
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vcc2-supply = <&vcc_sys>; |
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vcc3-supply = <&vcc_sys>; |
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vcc4-supply = <&vcc_sys>; |
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vcc6-supply = <&vcc_sys>; |
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vcc7-supply = <&vcc_sys>; |
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vcc8-supply = <&vcc_sys>; |
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vcc9-supply = <&vcc_sys>; |
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vcc10-supply = <&vcc_sys>; |
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vcc11-supply = <&vcc_sys>; |
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vcc12-supply = <&vcc_sys>; |
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clock-output-names = "xin32k", "rk808-clkout2"; |
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#clock-cells = <1>; |
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regulators { |
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vdd_cpu: DCDC_REG1 { |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-min-microvolt = <700000>; |
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regulator-max-microvolt = <1500000>; |
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regulator-name = "vdd_cpu"; |
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}; |
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vdd_log: DCDC_REG2 { |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-min-microvolt = <700000>; |
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regulator-max-microvolt = <1500000>; |
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regulator-name = "vdd_log"; |
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}; |
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vcc_ddr: DCDC_REG3 { |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-name = "vcc_ddr"; |
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}; |
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vcc33_io: DCDC_REG4 { |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-name = "vcc33_io"; |
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}; |
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vcc33_video: LDO_REG2 { |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-name = "vcc33_video"; |
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}; |
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vdd10_pll: LDO_REG3 { |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-min-microvolt = <1000000>; |
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regulator-max-microvolt = <1000000>; |
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regulator-name = "vdd10_pll"; |
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}; |
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vcc18_io: LDO_REG4 { |
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regulator-boot-on; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <1800000>; |
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regulator-name = "vcc18_io"; |
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}; |
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vdd10_video: LDO_REG6 { |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-min-microvolt = <1000000>; |
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regulator-max-microvolt = <1000000>; |
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regulator-name = "vdd10_video"; |
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}; |
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vcc18_video: LDO_REG8 { |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <1800000>; |
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regulator-name = "vcc18_video"; |
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}; |
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}; |
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}; |
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}; |
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&uart0 { |
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status = "okay"; |
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}; |
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&spi1 { |
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status = "okay"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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spiflash: w25q32dw@0 { |
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compatible = "spi-flash"; |
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reg = <0>; |
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spi-max-frequency = <49500000>; |
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spi-cpol; |
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spi-cpha; |
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}; |
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}; |
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@ -0,0 +1,34 @@ |
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/* |
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* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH |
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* |
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* SPDX-License-Identifier: GPL-2.0+ X11 |
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*/ |
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&pinctrl { |
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u-boot,dm-pre-reloc; |
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}; |
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&service_msch { |
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u-boot,dm-pre-reloc; |
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}; |
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&dmc { |
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u-boot,dm-pre-reloc; |
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status = "okay"; |
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}; |
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&pmugrf { |
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u-boot,dm-pre-reloc; |
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}; |
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&cru { |
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u-boot,dm-pre-reloc; |
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}; |
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&grf { |
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u-boot,dm-pre-reloc; |
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}; |
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&uart4 { |
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u-boot,dm-pre-reloc; |
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}; |
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@ -0,0 +1,34 @@ |
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/* |
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* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH |
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* |
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* SPDX-License-Identifier: GPL-2.0+ X11 |
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*/ |
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&pinctrl { |
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u-boot,dm-pre-reloc; |
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}; |
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&service_msch { |
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u-boot,dm-pre-reloc; |
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}; |
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&dmc { |
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u-boot,dm-pre-reloc; |
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status = "okay"; |
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}; |
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|
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&pmugrf { |
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u-boot,dm-pre-reloc; |
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}; |
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|
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&cru { |
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u-boot,dm-pre-reloc; |
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}; |
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|
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&grf { |
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u-boot,dm-pre-reloc; |
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}; |
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|
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&uart2 { |
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u-boot,dm-pre-reloc; |
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}; |
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@ -0,0 +1,187 @@ |
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/*
|
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* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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|
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#ifndef __ASM_ARCH_DDR_RK3368_H__ |
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#define __ASM_ARCH_DDR_RK3368_H__ |
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|
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/*
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* The RK3368 DDR PCTL differs from the incarnation in the RK3288 only |
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* in a few details. Most notably, it has an additional field to track |
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* tREFI in controller cycles (i.e. trefi_mem_ddr3). |
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*/ |
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struct rk3368_ddr_pctl { |
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u32 scfg; |
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u32 sctl; |
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u32 stat; |
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u32 intrstat; |
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u32 reserved0[12]; |
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u32 mcmd; |
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u32 powctl; |
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u32 powstat; |
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u32 cmdtstat; |
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u32 cmdtstaten; |
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u32 reserved1[3]; |
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u32 mrrcfg0; |
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u32 mrrstat0; |
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u32 mrrstat1; |
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u32 reserved2[4]; |
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u32 mcfg1; |
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u32 mcfg; |
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u32 ppcfg; |
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u32 mstat; |
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u32 lpddr2zqcfg; |
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u32 reserved3; |
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u32 dtupdes; |
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u32 dtuna; |
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u32 dtune; |
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u32 dtuprd0; |
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u32 dtuprd1; |
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u32 dtuprd2; |
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u32 dtuprd3; |
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u32 dtuawdt; |
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u32 reserved4[3]; |
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u32 togcnt1u; |
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u32 tinit; |
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u32 trsth; |
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u32 togcnt100n; |
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u32 trefi; |
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u32 tmrd; |
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u32 trfc; |
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u32 trp; |
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u32 trtw; |
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u32 tal; |
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u32 tcl; |
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u32 tcwl; |
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u32 tras; |
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u32 trc; |
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u32 trcd; |
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u32 trrd; |
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u32 trtp; |
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u32 twr; |
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u32 twtr; |
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u32 texsr; |
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u32 txp; |
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u32 txpdll; |
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u32 tzqcs; |
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u32 tzqcsi; |
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u32 tdqs; |
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u32 tcksre; |
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u32 tcksrx; |
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u32 tcke; |
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u32 tmod; |
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u32 trstl; |
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u32 tzqcl; |
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u32 tmrr; |
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u32 tckesr; |
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u32 tdpd; |
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u32 trefi_mem_ddr3; |
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u32 reserved5[45]; |
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u32 dtuwactl; |
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u32 dturactl; |
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u32 dtucfg; |
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u32 dtuectl; |
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u32 dtuwd0; |
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u32 dtuwd1; |
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u32 dtuwd2; |
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u32 dtuwd3; |
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u32 dtuwdm; |
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u32 dturd0; |
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u32 dturd1; |
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u32 dturd2; |
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u32 dturd3; |
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u32 dtulfsrwd; |
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u32 dtulfsrrd; |
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u32 dtueaf; |
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u32 dfitctrldelay; |
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u32 dfiodtcfg; |
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u32 dfiodtcfg1; |
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u32 dfiodtrankmap; |
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u32 dfitphywrdata; |
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u32 dfitphywrlat; |
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u32 reserved7[2]; |
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u32 dfitrddataen; |
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u32 dfitphyrdlat; |
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u32 reserved8[2]; |
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u32 dfitphyupdtype0; |
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u32 dfitphyupdtype1; |
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u32 dfitphyupdtype2; |
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u32 dfitphyupdtype3; |
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u32 dfitctrlupdmin; |
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u32 dfitctrlupdmax; |
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u32 dfitctrlupddly; |
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u32 reserved9; |
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u32 dfiupdcfg; |
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u32 dfitrefmski; |
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u32 dfitctrlupdi; |
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u32 reserved10[4]; |
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u32 dfitrcfg0; |
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u32 dfitrstat0; |
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u32 dfitrwrlvlen; |
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u32 dfitrrdlvlen; |
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u32 dfitrrdlvlgateen; |
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u32 dfiststat0; |
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u32 dfistcfg0; |
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u32 dfistcfg1; |
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u32 reserved11; |
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u32 dfitdramclken; |
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u32 dfitdramclkdis; |
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u32 dfistcfg2; |
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u32 dfistparclr; |
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u32 dfistparlog; |
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u32 reserved12[3]; |
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u32 dfilpcfg0; |
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u32 reserved13[3]; |
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u32 dfitrwrlvlresp0; |
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u32 dfitrwrlvlresp1; |
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u32 dfitrwrlvlresp2; |
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u32 dfitrrdlvlresp0; |
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u32 dfitrrdlvlresp1; |
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u32 dfitrrdlvlresp2; |
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u32 dfitrwrlvldelay0; |
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u32 dfitrwrlvldelay1; |
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u32 dfitrwrlvldelay2; |
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u32 dfitrrdlvldelay0; |
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u32 dfitrrdlvldelay1; |
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u32 dfitrrdlvldelay2; |
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u32 dfitrrdlvlgatedelay0; |
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u32 dfitrrdlvlgatedelay1; |
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u32 dfitrrdlvlgatedelay2; |
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u32 dfitrcmd; |
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u32 reserved14[46]; |
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u32 ipvr; |
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u32 iptr; |
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}; |
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check_member(rk3368_ddr_pctl, iptr, 0x03fc); |
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|
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struct rk3368_ddrphy { |
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u32 reg[0x100]; |
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}; |
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check_member(rk3368_ddrphy, reg[0xff], 0x03fc); |
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|
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struct rk3368_msch { |
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u32 coreid; |
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u32 revisionid; |
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u32 ddrconf; |
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u32 ddrtiming; |
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u32 ddrmode; |
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u32 readlatency; |
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u32 reserved1[8]; |
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u32 activate; |
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u32 devtodev; |
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}; |
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check_member(rk3368_msch, devtodev, 0x003c); |
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|
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/* GRF_SOC_CON0 */ |
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enum { |
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NOC_RSP_ERR_STALL = BIT(9), |
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MOBILE_DDR_SEL = BIT(4), |
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DDR0_16BIT_EN = BIT(3), |
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MSCH0_MAINDDR3_DDR3 = BIT(2), |
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MSCH0_MAINPARTIALPOP = BIT(1), |
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UPCTL_C_ACTIVE = BIT(0), |
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}; |
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|
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#endif |
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@ -0,0 +1,78 @@ |
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/*
|
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* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <debug_uart.h> |
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#include <dm.h> |
||||
#include <dm/pinctrl.h> |
||||
#include <ram.h> |
||||
#include <spl.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/cru_rk3368.h> |
||||
#include <asm/arch/grf_rk3368.h> |
||||
#include <asm/arch/hardware.h> |
||||
#include <asm/arch/periph.h> |
||||
#include <asm/arch/timer.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
void board_debug_uart_init(void) |
||||
{ |
||||
} |
||||
|
||||
void board_init_f(ulong dummy) |
||||
{ |
||||
struct udevice *pinctrl; |
||||
struct udevice *dev; |
||||
int ret; |
||||
|
||||
ret = spl_early_init(); |
||||
if (ret) { |
||||
debug("spl_early_init() failed: %d\n", ret); |
||||
hang(); |
||||
} |
||||
|
||||
/* Set up our preloader console */ |
||||
ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); |
||||
if (ret) { |
||||
error("%s: pinctrl init failed: %d\n", __func__, ret); |
||||
hang(); |
||||
} |
||||
|
||||
ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART0); |
||||
if (ret) { |
||||
error("%s: failed to set up console UART\n", __func__); |
||||
hang(); |
||||
} |
||||
|
||||
preloader_console_init(); |
||||
|
||||
ret = uclass_get_device(UCLASS_RAM, 0, &dev); |
||||
if (ret) { |
||||
debug("DRAM init failed: %d\n", ret); |
||||
return; |
||||
} |
||||
} |
||||
|
||||
u32 spl_boot_mode(const u32 boot_device) |
||||
{ |
||||
return MMCSD_MODE_RAW; |
||||
} |
||||
|
||||
u32 spl_boot_device(void) |
||||
{ |
||||
return BOOT_DEVICE_MMC1; |
||||
} |
||||
|
||||
#ifdef CONFIG_SPL_LOAD_FIT |
||||
int board_fit_config_name_match(const char *name) |
||||
{ |
||||
/* Just empty function now - can't decide what to choose */ |
||||
debug("%s: %s\n", __func__, name); |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
@ -0,0 +1,157 @@ |
||||
/*
|
||||
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <debug_uart.h> |
||||
#include <dm.h> |
||||
#include <ram.h> |
||||
#include <spl.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/bootrom.h> |
||||
#include <asm/arch/cru_rk3368.h> |
||||
#include <asm/arch/grf_rk3368.h> |
||||
#include <asm/arch/hardware.h> |
||||
#include <asm/arch/timer.h> |
||||
#include <syscon.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/*
|
||||
* The SPL (and also the full U-Boot stage on the RK3368) will run in |
||||
* secure mode (i.e. EL3) and an ATF will eventually be booted before |
||||
* starting up the operating system... so we can initialize the SGRF |
||||
* here and rely on the ATF installing the final (secure) policy |
||||
* later. |
||||
*/ |
||||
static inline uintptr_t sgrf_soc_con_addr(unsigned no) |
||||
{ |
||||
const uintptr_t SGRF_BASE = |
||||
(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); |
||||
|
||||
return SGRF_BASE + sizeof(u32) * no; |
||||
} |
||||
|
||||
static inline uintptr_t sgrf_busdmac_addr(unsigned no) |
||||
{ |
||||
const uintptr_t SGRF_BASE = |
||||
(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); |
||||
const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100; |
||||
const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET; |
||||
|
||||
return SGRF_BUSDMAC_BASE + sizeof(u32) * no; |
||||
} |
||||
|
||||
static void sgrf_init(void) |
||||
{ |
||||
struct rk3368_cru * const cru = |
||||
(struct rk3368_cru * const)rockchip_get_cru(); |
||||
const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0); |
||||
const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2); |
||||
const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12); |
||||
|
||||
/* Set all configurable IP to 'non secure'-mode */ |
||||
rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC); |
||||
rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC); |
||||
rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC); |
||||
|
||||
/*
|
||||
* From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c |
||||
* Original comment: "ddr space set no secure mode" |
||||
*/ |
||||
rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC); |
||||
rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC); |
||||
rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC); |
||||
|
||||
/* Set 'secure dma' to 'non secure'-mode */ |
||||
rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC); |
||||
rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC); |
||||
|
||||
dsb(); /* barrier */ |
||||
|
||||
rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ); |
||||
rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ); |
||||
|
||||
dsb(); /* barrier */ |
||||
udelay(10); |
||||
|
||||
rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ); |
||||
rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ); |
||||
} |
||||
|
||||
void board_debug_uart_init(void) |
||||
{ |
||||
/*
|
||||
* N.B.: This is called before the device-model has been |
||||
* initialised. For this reason, we can not access |
||||
* the GRF address range using the syscon API. |
||||
*/ |
||||
struct rk3368_grf * const grf = |
||||
(struct rk3368_grf * const)0xff770000; |
||||
|
||||
enum { |
||||
GPIO2D1_MASK = GENMASK(3, 2), |
||||
GPIO2D1_GPIO = 0, |
||||
GPIO2D1_UART0_SOUT = (1 << 2), |
||||
|
||||
GPIO2D0_MASK = GENMASK(1, 0), |
||||
GPIO2D0_GPIO = 0, |
||||
GPIO2D0_UART0_SIN = (1 << 0), |
||||
}; |
||||
|
||||
#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000) |
||||
/* Enable early UART0 on the RK3368 */ |
||||
rk_clrsetreg(&grf->gpio2d_iomux, |
||||
GPIO2D0_MASK, GPIO2D0_UART0_SIN); |
||||
rk_clrsetreg(&grf->gpio2d_iomux, |
||||
GPIO2D1_MASK, GPIO2D1_UART0_SOUT); |
||||
#endif |
||||
} |
||||
|
||||
void board_init_f(ulong dummy) |
||||
{ |
||||
struct udevice *dev; |
||||
int ret; |
||||
|
||||
#define EARLY_UART |
||||
#ifdef EARLY_UART |
||||
/*
|
||||
* Debug UART can be used from here if required: |
||||
* |
||||
* debug_uart_init(); |
||||
* printch('a'); |
||||
* printhex8(0x1234); |
||||
* printascii("string"); |
||||
*/ |
||||
debug_uart_init(); |
||||
printascii("U-Boot TPL board init\n"); |
||||
#endif |
||||
|
||||
ret = spl_early_init(); |
||||
if (ret) { |
||||
debug("spl_early_init() failed: %d\n", ret); |
||||
hang(); |
||||
} |
||||
|
||||
/* Reset security, so we can use DMA in the MMC drivers */ |
||||
sgrf_init(); |
||||
|
||||
ret = uclass_get_device(UCLASS_RAM, 0, &dev); |
||||
if (ret) { |
||||
debug("DRAM init failed: %d\n", ret); |
||||
return; |
||||
} |
||||
} |
||||
|
||||
void board_return_to_bootrom(void) |
||||
{ |
||||
back_to_bootrom(); |
||||
} |
||||
|
||||
u32 spl_boot_device(void) |
||||
{ |
||||
return BOOT_DEVICE_BOOTROM; |
||||
} |
||||
@ -1,60 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2016 Rockchip Electronics Co., Ltd. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <dm.h> |
||||
#include <ram.h> |
||||
#include <syscon.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/grf_rk3368.h> |
||||
#include <asm/arch/sdram_common.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
struct dram_info { |
||||
struct ram_info info; |
||||
struct rk3368_pmu_grf *pmugrf; |
||||
}; |
||||
|
||||
static int rk3368_dmc_probe(struct udevice *dev) |
||||
{ |
||||
struct dram_info *priv = dev_get_priv(dev); |
||||
|
||||
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); |
||||
debug("%s: grf=%p\n", __func__, priv->pmugrf); |
||||
priv->info.base = CONFIG_SYS_SDRAM_BASE; |
||||
priv->info.size = rockchip_sdram_size( |
||||
(phys_addr_t)&priv->pmugrf->os_reg[2]); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info) |
||||
{ |
||||
struct dram_info *priv = dev_get_priv(dev); |
||||
|
||||
*info = priv->info; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static struct ram_ops rk3368_dmc_ops = { |
||||
.get_info = rk3368_dmc_get_info, |
||||
}; |
||||
|
||||
|
||||
static const struct udevice_id rk3368_dmc_ids[] = { |
||||
{ .compatible = "rockchip,rk3368-dmc" }, |
||||
{ } |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(dmc_rk3368) = { |
||||
.name = "rockchip_rk3368_dmc", |
||||
.id = UCLASS_RAM, |
||||
.of_match = rk3368_dmc_ids, |
||||
.ops = &rk3368_dmc_ops, |
||||
.probe = rk3368_dmc_probe, |
||||
.priv_auto_alloc_size = sizeof(struct dram_info), |
||||
}; |
||||
@ -0,0 +1,13 @@ |
||||
/* |
||||
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#undef CONFIG_SPL_TEXT_BASE |
||||
#define CONFIG_SPL_TEXT_BASE CONFIG_TPL_TEXT_BASE |
||||
|
||||
#undef CONFIG_SPL_MAX_SIZE |
||||
#define CONFIG_SPL_MAX_SIZE CONFIG_TPL_MAX_SIZE |
||||
|
||||
#include "../../cpu/armv8/u-boot-spl.lds" |
||||
@ -0,0 +1,108 @@ |
||||
/*
|
||||
* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <dm.h> |
||||
#include <mmc.h> |
||||
#include <spl.h> |
||||
|
||||
#if CONFIG_IS_ENABLED(OF_CONTROL) |
||||
static int spl_node_to_boot_device(int node) |
||||
{ |
||||
struct udevice *parent; |
||||
|
||||
/*
|
||||
* This should eventually move into the SPL code, once SPL becomes |
||||
* aware of the block-device layer. Until then (and to avoid unneeded |
||||
* delays in getting this feature out, it lives at the board-level). |
||||
*/ |
||||
if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent)) { |
||||
struct udevice *dev; |
||||
struct blk_desc *desc = NULL; |
||||
|
||||
for (device_find_first_child(parent, &dev); |
||||
dev; |
||||
device_find_next_child(&dev)) { |
||||
if (device_get_uclass_id(dev) == UCLASS_BLK) { |
||||
desc = dev_get_uclass_platdata(dev); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
if (!desc) |
||||
return -ENOENT; |
||||
|
||||
switch (desc->devnum) { |
||||
case 0: |
||||
return BOOT_DEVICE_MMC1; |
||||
case 1: |
||||
return BOOT_DEVICE_MMC2; |
||||
default: |
||||
return -ENOSYS; |
||||
} |
||||
} |
||||
|
||||
/*
|
||||
* SPL doesn't differentiate SPI flashes, so we keep the detection |
||||
* brief and inaccurate... hopefully, the common SPL layer can be |
||||
* extended with awareness of the BLK layer (and matching OF_CONTROL) |
||||
* soon. |
||||
*/ |
||||
if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent)) |
||||
return BOOT_DEVICE_SPI; |
||||
|
||||
return -1; |
||||
} |
||||
|
||||
void board_boot_order(u32 *spl_boot_list) |
||||
{ |
||||
const void *blob = gd->fdt_blob; |
||||
int chosen_node = fdt_path_offset(blob, "/chosen"); |
||||
int idx = 0; |
||||
int elem; |
||||
int boot_device; |
||||
int node; |
||||
const char *conf; |
||||
|
||||
if (chosen_node < 0) { |
||||
debug("%s: /chosen not found, using spl_boot_device()\n", |
||||
__func__); |
||||
spl_boot_list[0] = spl_boot_device(); |
||||
return; |
||||
} |
||||
|
||||
for (elem = 0; |
||||
(conf = fdt_stringlist_get(blob, chosen_node, |
||||
"u-boot,spl-boot-order", elem, NULL)); |
||||
elem++) { |
||||
/* First check if the list element is an alias */ |
||||
const char *alias = fdt_get_alias(blob, conf); |
||||
if (alias) |
||||
conf = alias; |
||||
|
||||
/* Try to resolve the config item (or alias) as a path */ |
||||
node = fdt_path_offset(blob, conf); |
||||
if (node < 0) { |
||||
debug("%s: could not find %s in FDT", __func__, conf); |
||||
continue; |
||||
} |
||||
|
||||
/* Try to map this back onto SPL boot devices */ |
||||
boot_device = spl_node_to_boot_device(node); |
||||
if (boot_device < 0) { |
||||
debug("%s: could not map node @%x to a boot-device\n", |
||||
__func__, node); |
||||
continue; |
||||
} |
||||
|
||||
spl_boot_list[idx++] = boot_device; |
||||
} |
||||
|
||||
/* If we had no matches, fall back to spl_boot_device */ |
||||
if (idx == 0) |
||||
spl_boot_list[0] = spl_boot_device(); |
||||
} |
||||
#endif |
||||
@ -0,0 +1,15 @@ |
||||
if TARGET_LION_RK3368 |
||||
|
||||
config SYS_BOARD |
||||
default "lion_rk3368" |
||||
|
||||
config SYS_VENDOR |
||||
default "theobroma-systems" |
||||
|
||||
config SYS_CONFIG_NAME |
||||
default "lion_rk3368" |
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy |
||||
def_bool y |
||||
|
||||
endif |
||||
@ -0,0 +1,10 @@ |
||||
LION-RK3368 (RK3368-uQ7 system-on-module) |
||||
M: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
||||
M: Klaus Goger <klaus.goger@theobroma-systems.com> |
||||
S: Maintained |
||||
F: board/theobroma-systems/lion_rk3368 |
||||
F: include/configs/lion_rk3368.h |
||||
F: arch/arm/dts/rk3368-lion.dts |
||||
F: configs/lion-rk3368_defconfig |
||||
W: https://www.theobroma-systems.com/rk3368-uq7/tech-specs |
||||
T: git git://git.theobroma-systems.com/lion-u-boot.git |
||||
@ -0,0 +1,7 @@ |
||||
#
|
||||
# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += lion_rk3368.o
|
||||
@ -0,0 +1,60 @@ |
||||
Here is the step-by-step to boot to U-Boot on RK3368-uQ7 |
||||
|
||||
Get the Source and build ATF |
||||
============================ |
||||
|
||||
> git clone git://git.theobroma-systems.com/arm-trusted-firmware.git |
||||
> cd arm-trusted-firmware |
||||
> make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3368 bl31 |
||||
> cp build/rk3368/release/bl31.bin ../u-boot/bl31-rk3368.bin |
||||
|
||||
Configure U-Boot |
||||
================ |
||||
|
||||
> cd ../u-boot |
||||
> make lion-rk3368_defconfig |
||||
|
||||
Build the TPL/SPL stage |
||||
======================= |
||||
|
||||
> make CROSS_COMPILE=aarch64-unknown-elf- ARCH=arm |
||||
> tools/mkimage -n rk3368 -T rksd -d tpl/u-boot-tpl.bin spl-3368.img |
||||
> cat spl/u-boot-spl-dtb.bin >> spl-3368.img |
||||
|
||||
Build the full U-Boot and a FIT image including the ATF |
||||
======================================================= |
||||
|
||||
> make CROSS_COMPILE=aarch64-unknown-elf- ARCH=arm u-boot.itb |
||||
|
||||
Write to a SD-card |
||||
================== |
||||
|
||||
> dd if=spl-3368.img of=/dev/sdb seek=64 |
||||
> dd if=u-boot.itb of=/dev/sdb seek=512 |
||||
|
||||
|
||||
If everything went according to plan, you should see the following |
||||
output on UART0: |
||||
|
||||
<debug_uart> U-Boot TPL board init |
||||
Trying to boot from BOOTROM |
||||
Returning to boot ROM... |
||||
Trying to boot from MMC1 |
||||
NOTICE: BL31: v1.3(release):v1.2-1320-gbf43a443 |
||||
NOTICE: BL31: Built : 18:04:47, Jul 5 2017 |
||||
|
||||
|
||||
U-Boot 2017.07-00158-g2395e99858 (Jul 18 2017 - 21:03:31 +0200) |
||||
|
||||
Model: Theobroma Systems RK3368-uQ7 SoM |
||||
DRAM: 2 GiB |
||||
MMC: dwmmc@ff0c0000: 1, dwmmc@ff0f0000: 0 |
||||
Using default environment |
||||
|
||||
In: serial@ff180000 |
||||
Out: serial@ff180000 |
||||
Err: serial@ff180000 |
||||
Net: |
||||
Warning: ethernet@ff290000 (eth0) using random MAC address - d2:69:35:7e:d0:1e |
||||
eth0: ethernet@ff290000 |
||||
Hit any key to stop autoboot: 2 |
||||
@ -0,0 +1,51 @@ |
||||
/* |
||||
* Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH |
||||
* |
||||
* Minimal dts for a SPL FIT image payload. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ X11 |
||||
*/ |
||||
|
||||
/dts-v1/; |
||||
|
||||
/ { |
||||
description = "FIT image with U-Boot proper, ATF bl31, DTB"; |
||||
#address-cells = <1>; |
||||
|
||||
images { |
||||
uboot { |
||||
description = "U-Boot (64-bit)"; |
||||
data = /incbin/("../../../u-boot-nodtb.bin"); |
||||
type = "standalone"; |
||||
arch = "arm64"; |
||||
compression = "none"; |
||||
load = <0x00200000>; |
||||
}; |
||||
atf { |
||||
description = "ARM Trusted Firmware"; |
||||
data = /incbin/("../../../bl31-rk3368.bin"); |
||||
type = "firmware"; |
||||
arch = "arm64"; |
||||
compression = "none"; |
||||
load = <0x00010000>; |
||||
entry = <0x00010000>; |
||||
}; |
||||
|
||||
fdt { |
||||
description = "RK3368-uQ7 (Lion) flat device-tree"; |
||||
data = /incbin/("../../../u-boot.dtb"); |
||||
type = "flat_dt"; |
||||
compression = "none"; |
||||
}; |
||||
}; |
||||
|
||||
configurations { |
||||
default = "conf"; |
||||
conf { |
||||
description = "Theobroma Systems RK3368-uQ7 (Puma) SoM"; |
||||
firmware = "uboot"; |
||||
loadables = "atf"; |
||||
fdt = "fdt"; |
||||
}; |
||||
}; |
||||
}; |
||||
@ -0,0 +1,25 @@ |
||||
/*
|
||||
* Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#include <common.h> |
||||
#include <dm.h> |
||||
#include <ram.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/grf_rk3368.h> |
||||
#include <asm/arch/timer.h> |
||||
#include <syscon.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
int mach_cpu_init(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
@ -0,0 +1,27 @@ |
||||
/*
|
||||
* Copyright (C) 2017 Theobroma Systems Design und Consulting GmH |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <spl.h> |
||||
|
||||
__weak void board_return_to_bootrom(void) |
||||
{ |
||||
} |
||||
|
||||
static int spl_return_to_bootrom(struct spl_image_info *spl_image, |
||||
struct spl_boot_device *bootdev) |
||||
{ |
||||
/*
|
||||
* If the board implements a way to return to its ROM (with |
||||
* the expectation that the next stage of will be booted by |
||||
* the ROM), it will implement board_return_to_bootrom() and |
||||
* should not return from it. |
||||
*/ |
||||
board_return_to_bootrom(); |
||||
return false; |
||||
} |
||||
|
||||
SPL_LOAD_IMAGE_METHOD("BOOTROM", 0, BOOT_DEVICE_BOOTROM, spl_return_to_bootrom); |
||||
@ -0,0 +1,95 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_ROCKCHIP=y |
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y |
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y |
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000 |
||||
CONFIG_ROCKCHIP_RK3368=y |
||||
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0 |
||||
CONFIG_TPL_LIBCOMMON_SUPPORT=y |
||||
CONFIG_TPL_LIBGENERIC_SUPPORT=y |
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y |
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y |
||||
CONFIG_SPL_SPI_SUPPORT=y |
||||
CONFIG_SPL_STACK_R_ADDR=0x600000 |
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3368-lion" |
||||
CONFIG_SMBIOS_PRODUCT_NAME="sheep_rk3368" |
||||
CONFIG_DEBUG_UART=y |
||||
CONFIG_FIT=y |
||||
CONFIG_FIT_VERBOSE=y |
||||
CONFIG_SPL_LOAD_FIT=y |
||||
CONFIG_SPL_FIT_SOURCE="board/theobroma-systems/lion_rk3368/fit_spl_atf.its" |
||||
CONFIG_ENV_IS_IN_MMC=y |
||||
# CONFIG_DISPLAY_CPUINFO is not set |
||||
CONFIG_ARCH_EARLY_INIT_R=y |
||||
CONFIG_SPL=y |
||||
CONFIG_SPL_BOOTROM_SUPPORT=y |
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set |
||||
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set |
||||
CONFIG_TPL_SYS_MALLOC_SIMPLE=y |
||||
CONFIG_SPL_STACK_R=y |
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 |
||||
CONFIG_SPL_ATF_SUPPORT=y |
||||
CONFIG_SPL_ATF_TEXT_BASE=0x10000 |
||||
CONFIG_TPL=y |
||||
CONFIG_TPL_BOOTROM_SUPPORT=y |
||||
CONFIG_TPL_DRIVERS_MISC_SUPPORT=y |
||||
CONFIG_FASTBOOT=y |
||||
CONFIG_ANDROID_BOOT_IMAGE=y |
||||
# CONFIG_CMD_IMLS is not set |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_SF=y |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_REGULATOR=y |
||||
CONFIG_CMD_MTDPARTS=y |
||||
CONFIG_SPL_OF_CONTROL=y |
||||
CONFIG_TPL_OF_CONTROL=y |
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent" |
||||
CONFIG_TPL_OF_PLATDATA=y |
||||
CONFIG_NET_RANDOM_ETHADDR=y |
||||
CONFIG_TPL_DM=y |
||||
CONFIG_REGMAP=y |
||||
CONFIG_SPL_REGMAP=y |
||||
CONFIG_TPL_REGMAP=y |
||||
CONFIG_SYSCON=y |
||||
CONFIG_SPL_SYSCON=y |
||||
CONFIG_TPL_SYSCON=y |
||||
CONFIG_CLK=y |
||||
CONFIG_SPL_CLK=y |
||||
CONFIG_TPL_CLK=y |
||||
CONFIG_ROCKCHIP_GPIO=y |
||||
CONFIG_MMC_DW=y |
||||
CONFIG_MMC_DW_ROCKCHIP=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_SPI_FLASH_MACRONIX=y |
||||
CONFIG_SPI_FLASH_WINBOND=y |
||||
CONFIG_PHY_MICREL=y |
||||
CONFIG_PHY_MICREL_KSZ9031=y |
||||
CONFIG_DM_ETH=y |
||||
CONFIG_ETH_DESIGNWARE=y |
||||
CONFIG_RGMII=y |
||||
CONFIG_GMAC_ROCKCHIP=y |
||||
CONFIG_PINCTRL=y |
||||
CONFIG_SPL_PINCTRL=y |
||||
CONFIG_PINCTRL_ROCKCHIP_RK3368=y |
||||
CONFIG_DM_PMIC=y |
||||
CONFIG_PMIC_RK8XX=y |
||||
CONFIG_DM_REGULATOR_FIXED=y |
||||
CONFIG_RAM=y |
||||
CONFIG_SPL_RAM=y |
||||
CONFIG_TPL_RAM=y |
||||
CONFIG_DEBUG_UART_BASE=0xFF180000 |
||||
CONFIG_DEBUG_UART_CLOCK=24000000 |
||||
CONFIG_DEBUG_UART_SHIFT=2 |
||||
CONFIG_DEBUG_UART_ANNOUNCE=y |
||||
CONFIG_DEBUG_UART_SKIP_INIT=y |
||||
CONFIG_ROCKCHIP_SPI=y |
||||
CONFIG_SYSRESET=y |
||||
CONFIG_TIMER=y |
||||
CONFIG_SPL_TIMER=y |
||||
CONFIG_TPL_TIMER=y |
||||
CONFIG_ROCKCHIP_TIMER=y |
||||
CONFIG_USE_TINY_PRINTF=y |
||||
CONFIG_SPL_TINY_MEMSET=y |
||||
CONFIG_LZO=y |
||||
CONFIG_ERRNO_STR=y |
||||
CONFIG_SMBIOS_MANUFACTURER="rockchip" |
||||
Some files were not shown because too many files have changed in this diff Show More
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Reference in new issue