OMAP3: zoom1: Configure GPMC for Ethernet

zoom1 uses LAN9211 configured over GPMC Chip Select 1.

Signed-off-by: Nishanth Menon <nm@ti.com>

board/logicpd/zoom1/zoom1.c

@@ -18,6 +18,7 @@
 #include <netdev.h>
 #include <twl4030.h>
 #include <asm/io.h>
+#include <asm/arch/mem.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/sys_proto.h>
@@ -26,6 +27,20 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* gpmc_cfg is initialized by gpmc_init and we use it here */
+extern struct gpmc *gpmc_cfg;
+
+/* GPMC definitions for Ethenet Controller LAN9211 */
+static const u32 gpmc_lab_enet[] = {
+	ZOOM1_ENET_GPMC_CONF1,
+	ZOOM1_ENET_GPMC_CONF2,
+	ZOOM1_ENET_GPMC_CONF3,
+	ZOOM1_ENET_GPMC_CONF4,
+	ZOOM1_ENET_GPMC_CONF5,
+	ZOOM1_ENET_GPMC_CONF6,
+	/*CONF7- computed as params */
+};
+
 /*
  * Routine: board_init
  * Description: Early hardware init.
@@ -33,6 +48,9 @@ DECLARE_GLOBAL_DATA_PTR;
 int board_init(void)
 {
 	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* CS1 is Ethernet LAN9211 */
+	enable_gpmc_cs_config(gpmc_lab_enet, &gpmc_cfg->cs[1],
+			      DEBUG_BASE, GPMC_SIZE_16M);
 	/* board id for Linux */
 	gd->bd->bi_arch_number = MACH_TYPE_OMAP_LDP;
 	/* boot param addr */

board/logicpd/zoom1/zoom1.h

@@ -17,6 +17,13 @@ const omap3_sysinfo sysinfo = {
 	"NAND",
 };
 
+#define ZOOM1_ENET_GPMC_CONF1  0x00611000
+#define ZOOM1_ENET_GPMC_CONF2  0x001F1F01
+#define ZOOM1_ENET_GPMC_CONF3  0x00080803
+#define ZOOM1_ENET_GPMC_CONF4  0x1D091D09
+#define ZOOM1_ENET_GPMC_CONF5  0x041D1F1F
+#define ZOOM1_ENET_GPMC_CONF6  0x1D0904C4
+
 /*
  * IEN	- Input Enable
  * IDIS	- Input Disable
@@ -94,13 +101,13 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0)) /*GPMC_D14*/\
 	MUX_VAL(CP(GPMC_D15),		(IEN  | PTD | DIS | M0)) /*GPMC_D15*/\
 	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
-	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M7)) /*GPMC_nCS1*/\
-	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M7)) /*GPMC_nCS2*/\
-	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M7)) /*GPMC_nCS3*/\
-	MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTU | EN  | M7)) /*GPMC_nCS4*/\
-	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTD | DIS | M7)) /*GPMC_nCS5*/\
+	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
+	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | DIS | M7)) /*GPMC_nCS2*/\
+	MUX_VAL(CP(GPMC_NCS3),		(IEN  | PTU | DIS | M4)) /*GPMC_nCS3 -> GPIO54*/\
+	MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTU | DIS | M4)) /*GPMC_nCS4 -> GPIO 55*/\
+	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTD | DIS | M4)) /*GPMC_nCS5 -> GPIO 56*/\
 	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M7)) /*GPMC_nCS6*/\
-	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M7)) /*GPMC_nCS7*/\
+	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M1)) /*GPMC_nCS7 -> GPMC_IO_DIR*/\
 	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
 	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
 	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\