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@ -6,6 +6,8 @@ |
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* SPDX-License-Identifier: GPL-2.0+ X11 |
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*/ |
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/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */ |
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/ { |
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compatible = "socionext,ph1-ld20"; |
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#address-cells = <2>; |
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@ -41,7 +43,7 @@ |
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compatible = "arm,cortex-a72", "arm,armv8"; |
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reg = <0 0x000>; |
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enable-method = "spin-table"; |
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cpu-release-addr = <0 0x80000100>; |
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cpu-release-addr = <0 0x80000000>; |
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}; |
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cpu1: cpu@1 { |
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@ -49,7 +51,7 @@ |
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compatible = "arm,cortex-a72", "arm,armv8"; |
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reg = <0 0x001>; |
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enable-method = "spin-table"; |
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cpu-release-addr = <0 0x80000100>; |
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cpu-release-addr = <0 0x80000000>; |
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}; |
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cpu2: cpu@100 { |
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@ -57,7 +59,7 @@ |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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reg = <0 0x100>; |
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enable-method = "spin-table"; |
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cpu-release-addr = <0 0x80000100>; |
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cpu-release-addr = <0 0x80000000>; |
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}; |
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cpu3: cpu@101 { |
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@ -65,11 +67,17 @@ |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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reg = <0 0x101>; |
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enable-method = "spin-table"; |
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cpu-release-addr = <0 0x80000100>; |
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cpu-release-addr = <0 0x80000000>; |
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}; |
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}; |
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clocks { |
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refclk: ref { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <25000000>; |
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}; |
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uart_clk: uart_clk { |
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#clock-cells = <0>; |
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compatible = "fixed-clock"; |
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@ -96,6 +104,7 @@ |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0 0 0 0xffffffff>; |
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u-boot,dm-pre-reloc; |
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serial0: serial@54006800 { |
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compatible = "socionext,uniphier-uart"; |
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@ -219,6 +228,8 @@ |
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reg = <0x58c00000 0x400>; |
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#address-cells = <2>; |
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#size-cells = <1>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_system_bus>; |
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}; |
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smpctrl@59800000 { |
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@ -243,9 +254,15 @@ |
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bus-width = <4>; |
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}; |
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pinctrl: pinctrl@5f801000 { |
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compatible = "socionext,ph1-ld20-pinctrl", "syscon"; |
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reg = <0x5f801000 0xe00>; |
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soc-glue@5f800000 { |
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compatible = "simple-mfd", "syscon"; |
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reg = <0x5f800000 0x2000>; |
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u-boot,dm-pre-reloc; |
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pinctrl: pinctrl { |
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compatible = "socionext,uniphier-ld20-pinctrl"; |
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u-boot,dm-pre-reloc; |
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}; |
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}; |
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gic: interrupt-controller@5fe00000 { |
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