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ARM: dts: uniphier: sync Device Trees with upstream Linux

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I periodically sync Device Trees for better maintainability.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
master
Masahiro Yamada 9 years ago
parent aac641bcf4
commit c4adc50ea6
22 changed files with 99 additions and 138 deletions
  1. 22
      arch/arm/dts/uniphier-common32.dtsi
  2. 13
      arch/arm/dts/uniphier-ph1-ld11-ref.dts
  3. 45
      arch/arm/dts/uniphier-ph1-ld11.dtsi
  4. 10
      arch/arm/dts/uniphier-ph1-ld20-ref.dts
  5. 31
      arch/arm/dts/uniphier-ph1-ld20.dtsi
  6. 10
      arch/arm/dts/uniphier-ph1-ld4-ref.dts
  7. 2
      arch/arm/dts/uniphier-ph1-ld4.dtsi
  8. 10
      arch/arm/dts/uniphier-ph1-ld6b-ref.dts
  9. 4
      arch/arm/dts/uniphier-ph1-ld6b.dtsi
  10. 10
      arch/arm/dts/uniphier-ph1-pro4-ace.dts
  11. 10
      arch/arm/dts/uniphier-ph1-pro4-ref.dts
  12. 10
      arch/arm/dts/uniphier-ph1-pro4-sanji.dts
  13. 2
      arch/arm/dts/uniphier-ph1-pro4.dtsi
  14. 10
      arch/arm/dts/uniphier-ph1-pro5-4kbox.dts
  15. 2
      arch/arm/dts/uniphier-ph1-pro5.dtsi
  16. 10
      arch/arm/dts/uniphier-ph1-sld8-ref.dts
  17. 2
      arch/arm/dts/uniphier-ph1-sld8.dtsi
  18. 10
      arch/arm/dts/uniphier-pinctrl.dtsi
  19. 10
      arch/arm/dts/uniphier-proxstream2-gentil.dts
  20. 10
      arch/arm/dts/uniphier-proxstream2-vodka.dts
  21. 2
      arch/arm/dts/uniphier-proxstream2.dtsi
  22. 2
      arch/arm/dts/uniphier-ref-daughter.dtsi

22
arch/arm/dts/uniphier-common32.dtsi
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@ -22,6 +22,7 @@
#size-cells = <1>;
ranges;
interrupt-parent = <&intc>;
u-boot,dm-pre-reloc;
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
@ -65,9 +66,12 @@
system_bus: system-bus@58c00000 {
compatible = "socionext,uniphier-system-bus";
status = "disabled";
reg = <0x58c00000 0x400>;
#address-cells = <2>;
#size-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_system_bus>;
};
smpctrl@59800000 {
@ -109,9 +113,15 @@
interrupt-controller;
};
pinctrl: pinctrl@5f801000 {
/* specify compatible in each SoC DTSI */
reg = <0x5f801000 0xe00>;
soc-glue@5f800000 {
compatible = "simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
u-boot,dm-pre-reloc;
pinctrl: pinctrl {
/* specify compatible in each SoC DTSI */
u-boot,dm-pre-reloc;
};
};
sysctrl: sysctrl@61840000 {
@ -124,8 +134,12 @@
nand: nand@68000000 {
compatible = "denali,denali-nand-dt";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
status = "disabled";
reg-names = "nand_data", "denali_reg";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
interrupts = <0 65 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
};
};
};

13
arch/arm/dts/uniphier-ph1-ld11-ref.dts
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@ -1,7 +1,8 @@
/*
* Device Tree Source for UniPhier PH1-LD11 Reference Board
*
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
@ -62,20 +63,10 @@
};
/* for U-Boot only */
/ {
soc {
u-boot,dm-pre-reloc;
};
};
&serial0 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};

45
arch/arm/dts/uniphier-ph1-ld11.dtsi
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@ -1,11 +1,14 @@
/*
* Device Tree Source for UniPhier PH1-LD11 SoC
*
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+ X11
*/
/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
/ {
compatible = "socionext,ph1-ld11";
#address-cells = <2>;
@ -16,24 +19,41 @@
#address-cells = <2>;
#size-cells = <0>;
cpu@0 {
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x000>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000100>;
cpu-release-addr = <0 0x80000000>;
};
cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x001>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000100>;
cpu-release-addr = <0 0x80000000>;
};
};
clocks {
refclk: ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
uart_clk: uart_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
@ -60,6 +80,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
u-boot,dm-pre-reloc;
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
@ -183,6 +204,8 @@
reg = <0x58c00000 0x400>;
#address-cells = <2>;
#size-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_system_bus>;
};
smpctrl@59800000 {
@ -226,9 +249,15 @@
#clock-cells = <1>;
};
pinctrl: pinctrl@5f801000 {
compatible = "socionext,ph1-ld11-pinctrl", "syscon";
reg = <0x5f801000 0xe00>;
soc-glue@5f800000 {
compatible = "simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
u-boot,dm-pre-reloc;
pinctrl: pinctrl {
compatible = "socionext,uniphier-ld11-pinctrl";
u-boot,dm-pre-reloc;
};
};
gic: interrupt-controller@5fe00000 {

10
arch/arm/dts/uniphier-ph1-ld20-ref.dts
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@ -51,20 +51,10 @@
};
/* for U-Boot only */
/ {
soc {
u-boot,dm-pre-reloc;
};
};
&serial0 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};

31
arch/arm/dts/uniphier-ph1-ld20.dtsi
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@ -6,6 +6,8 @@
* SPDX-License-Identifier: GPL-2.0+ X11
*/
/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
/ {
compatible = "socionext,ph1-ld20";
#address-cells = <2>;
@ -41,7 +43,7 @@
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0 0x000>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000100>;
cpu-release-addr = <0 0x80000000>;
};
cpu1: cpu@1 {
@ -49,7 +51,7 @@
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0 0x001>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000100>;
cpu-release-addr = <0 0x80000000>;
};
cpu2: cpu@100 {
@ -57,7 +59,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x100>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000100>;
cpu-release-addr = <0 0x80000000>;
};
cpu3: cpu@101 {
@ -65,11 +67,17 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x101>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000100>;
cpu-release-addr = <0 0x80000000>;
};
};
clocks {
refclk: ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
uart_clk: uart_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
@ -96,6 +104,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
u-boot,dm-pre-reloc;
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
@ -219,6 +228,8 @@
reg = <0x58c00000 0x400>;
#address-cells = <2>;
#size-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_system_bus>;
};
smpctrl@59800000 {
@ -243,9 +254,15 @@
bus-width = <4>;
};
pinctrl: pinctrl@5f801000 {
compatible = "socionext,ph1-ld20-pinctrl", "syscon";
reg = <0x5f801000 0xe00>;
soc-glue@5f800000 {
compatible = "simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
u-boot,dm-pre-reloc;
pinctrl: pinctrl {
compatible = "socionext,uniphier-ld20-pinctrl";
u-boot,dm-pre-reloc;
};
};
gic: interrupt-controller@5fe00000 {

10
arch/arm/dts/uniphier-ph1-ld4-ref.dts
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@ -69,20 +69,10 @@
};
/* for U-Boot only */
/ {
soc {
u-boot,dm-pre-reloc;
};
};
&serial0 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};

2
arch/arm/dts/uniphier-ph1-ld4.dtsi
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@ -310,7 +310,7 @@
};
&pinctrl {
compatible = "socionext,ph1-ld4-pinctrl", "syscon";
compatible = "socionext,uniphier-ld4-pinctrl";
};
&sysctrl {

10
arch/arm/dts/uniphier-ph1-ld6b-ref.dts
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@ -71,20 +71,10 @@
};
/* for U-Boot only */
/ {
soc {
u-boot,dm-pre-reloc;
};
};
&serial0 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};

4
arch/arm/dts/uniphier-ph1-ld6b.dtsi
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@ -17,7 +17,7 @@
compatible = "socionext,ph1-ld6b";
};
/* UART3 unavilable: the pads are not wired to the package balls */
/* UART3 unavailable: the pads are not wired to the package balls */
&serial3 {
status = "disabled";
};
@ -27,5 +27,5 @@
* which makes the pinctrl driver unshareable.
*/
&pinctrl {
compatible = "socionext,ph1-ld6b-pinctrl", "syscon";
compatible = "socionext,uniphier-ld6b-pinctrl";
};

10
arch/arm/dts/uniphier-ph1-pro4-ace.dts
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@ -90,20 +90,10 @@
};
/* for U-Boot only */
/ {
soc {
u-boot,dm-pre-reloc;
};
};
&serial0 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};

10
arch/arm/dts/uniphier-ph1-pro4-ref.dts
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@ -80,20 +80,10 @@
};
/* for U-Boot only */
/ {
soc {
u-boot,dm-pre-reloc;
};
};
&serial0 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};

10
arch/arm/dts/uniphier-ph1-pro4-sanji.dts
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@ -85,12 +85,6 @@
};
/* for U-Boot only */
/ {
soc {
u-boot,dm-pre-reloc;
};
};
&serial0 {
u-boot,dm-pre-reloc;
};
@ -103,10 +97,6 @@
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};

2
arch/arm/dts/uniphier-ph1-pro4.dtsi
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@ -452,7 +452,7 @@
};
&pinctrl {
compatible = "socionext,ph1-pro4-pinctrl", "syscon";
compatible = "socionext,uniphier-pro4-pinctrl";
};
&sysctrl {

10
arch/arm/dts/uniphier-ph1-pro5-4kbox.dts
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@ -56,20 +56,10 @@
};
/* for U-Boot only */
/ {
soc {
u-boot,dm-pre-reloc;
};
};
&serial1 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_uart1 {
u-boot,dm-pre-reloc;
};

2
arch/arm/dts/uniphier-ph1-pro5.dtsi
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@ -431,7 +431,7 @@
};
&pinctrl {
compatible = "socionext,ph1-pro5-pinctrl", "syscon";
compatible = "socionext,uniphier-pro5-pinctrl";
};
&sysctrl {

10
arch/arm/dts/uniphier-ph1-sld8-ref.dts
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@ -73,20 +73,10 @@
};
/* for U-Boot only */
/ {
soc {
u-boot,dm-pre-reloc;
};
};
&serial0 {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0 {
u-boot,dm-pre-reloc;
};

2
arch/arm/dts/uniphier-ph1-sld8.dtsi
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@ -310,7 +310,7 @@
};
&pinctrl {
compatible = "socionext,ph1-sld8-pinctrl", "syscon";
compatible = "socionext,uniphier-sld8-pinctrl";
};
&sysctrl {

10
arch/arm/dts/uniphier-pinctrl.dtsi
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@ -47,6 +47,11 @@
function = "nand";
};
pinctrl_nand2cs: nand2cs_grp {
groups = "nand", "nand_cs1";
function = "nand";
};
pinctrl_sd: sd_grp {
groups = "sd";
function = "sd";
@ -67,6 +72,11 @@
function = "sd1";
};
pinctrl_system_bus: system_bus_grp {
groups = "system_bus", "system_bus_cs1";
function = "system_bus";
};
pinctrl_uart0: uart0_grp {
groups = "uart0";
function = "uart0";

10
arch/arm/dts/uniphier-proxstream2-gentil.dts
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@ -65,12 +65,6 @@
};
/* for U-Boot only */
/ {
soc {
u-boot,dm-pre-reloc;
};
};
&serial2 {
u-boot,dm-pre-reloc;
};
@ -83,10 +77,6 @@
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_uart2 {
u-boot,dm-pre-reloc;
};

10
arch/arm/dts/uniphier-proxstream2-vodka.dts
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@ -50,12 +50,6 @@
};
/* for U-Boot only */
/ {
soc {
u-boot,dm-pre-reloc;
};
};
&serial2 {
u-boot,dm-pre-reloc;
};
@ -68,10 +62,6 @@
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_uart2 {
u-boot,dm-pre-reloc;
};

2
arch/arm/dts/uniphier-proxstream2.dtsi
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@ -435,7 +435,7 @@
};
&pinctrl {
compatible = "socionext,proxstream2-pinctrl", "syscon";
compatible = "socionext,uniphier-pxs2-pinctrl";
};
&sysctrl {

2
arch/arm/dts/uniphier-ref-daughter.dtsi
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@ -7,7 +7,7 @@
*/
&i2c0 {
eeprom {
eeprom@50 {
compatible = "microchip,24lc128", "i2c-eeprom";
reg = <0x50>;
u-boot,i2c-offset-len = <2>;

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