Add support of 2 stage NAND boot loader using SPL framework. here, PBL initialise the internal SRAM and copy SPL(160KB). This further initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR. Finally SPL transer control to u-boot. Initialise/create followings required for SPL framework - Add spl.c which defines board_init_f, board_init_r - update tlb and ddr accordingly Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>master
Prabhakar Kushwaha
10 years ago
committed by
York Sun
parent
89ad7be8e7
commit
c5dfe6ec58
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/* Copyright 2013 Freescale Semiconductor, Inc.
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/spl.h> |
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#include <malloc.h> |
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#include <ns16550.h> |
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#include <nand.h> |
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#include <i2c.h> |
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#include "../common/qixis.h" |
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#include "b4860qds_qixis.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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phys_size_t get_effective_memsize(void) |
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{ |
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return CONFIG_SYS_L3_SIZE; |
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} |
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unsigned long get_board_sys_clk(void) |
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{ |
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u8 sysclk_conf = QIXIS_READ(brdcfg[1]); |
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switch ((sysclk_conf & 0x0C) >> 2) { |
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case QIXIS_CLK_100: |
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return 100000000; |
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case QIXIS_CLK_125: |
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return 125000000; |
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case QIXIS_CLK_133: |
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return 133333333; |
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} |
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return 66666666; |
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} |
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unsigned long get_board_ddr_clk(void) |
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{ |
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u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); |
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switch (ddrclk_conf & 0x03) { |
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case QIXIS_CLK_100: |
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return 100000000; |
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case QIXIS_CLK_125: |
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return 125000000; |
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case QIXIS_CLK_133: |
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return 133333333; |
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} |
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return 66666666; |
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} |
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void board_init_f(ulong bootflag) |
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{ |
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u32 plat_ratio, sys_clk, uart_clk; |
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; |
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/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ |
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memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); |
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/* Update GD pointer */ |
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gd = (gd_t *)(CONFIG_SPL_GD_ADDR); |
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/* compiler optimization barrier needed for GCC >= 3.4 */ |
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__asm__ __volatile__("" : : : "memory"); |
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console_init_f(); |
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/* initialize selected port with appropriate baud rate */ |
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sys_clk = get_board_sys_clk(); |
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plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; |
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uart_clk = sys_clk * plat_ratio / 2; |
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NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, |
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uart_clk / 16 / CONFIG_BAUDRATE); |
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relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); |
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} |
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void board_init_r(gd_t *gd, ulong dest_addr) |
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{ |
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bd_t *bd; |
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bd = (bd_t *)(gd + sizeof(gd_t)); |
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memset(bd, 0, sizeof(bd_t)); |
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gd->bd = bd; |
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bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; |
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bd->bi_memsize = CONFIG_SYS_L3_SIZE; |
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probecpu(); |
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get_clocks(); |
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mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, |
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CONFIG_SPL_RELOC_MALLOC_SIZE); |
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#ifndef CONFIG_SPL_NAND_BOOT |
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env_init(); |
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env_relocate(); |
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#else |
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/* relocate environment function pointers etc. */ |
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nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, |
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(uchar *)CONFIG_ENV_ADDR); |
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gd->env_addr = (ulong)(CONFIG_ENV_ADDR); |
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gd->env_valid = 1; |
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#endif |
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i2c_init_all(); |
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puts("\n\n"); |
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gd->ram_size = initdram(0); |
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#ifdef CONFIG_SPL_NAND_BOOT |
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nand_boot(); |
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#endif |
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} |
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