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/*
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* Copyright (c) 2011, Google Inc. All rights reserved. |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef _TEGRA2_GPIO_H_ |
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#define _TEGRA2_GPIO_H_ |
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/*
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* The Tegra 2x GPIO controller has 222 GPIOs arranged in 8 banks of 4 ports, |
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* each with 8 GPIOs. |
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*/ |
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#define TEGRA_GPIO_PORTS 4 /* The number of ports per bank */ |
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#define TEGRA_GPIO_BANKS 8 /* The number of banks */ |
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|
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/* GPIO Controller registers for a single bank */ |
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struct gpio_ctlr_bank { |
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uint gpio_config[TEGRA_GPIO_PORTS]; |
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uint gpio_dir_out[TEGRA_GPIO_PORTS]; |
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uint gpio_out[TEGRA_GPIO_PORTS]; |
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uint gpio_in[TEGRA_GPIO_PORTS]; |
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uint gpio_int_status[TEGRA_GPIO_PORTS]; |
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uint gpio_int_enable[TEGRA_GPIO_PORTS]; |
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uint gpio_int_level[TEGRA_GPIO_PORTS]; |
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uint gpio_int_clear[TEGRA_GPIO_PORTS]; |
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}; |
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struct gpio_ctlr { |
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struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS]; |
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}; |
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#define GPIO_BANK(x) ((x) >> 5) |
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#define GPIO_PORT(x) (((x) >> 3) & 0x3) |
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#define GPIO_BIT(x) ((x) & 0x7) |
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/*
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* GPIO_PI3 = Port I = 8, bit = 3. |
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* Seaboard: used for UART/SPI selection |
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* Harmony: not used |
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*/ |
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#define GPIO_PI3 ((8 << 3) | 3) |
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#endif /* TEGRA2_GPIO_H_ */ |
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