Albert ARIBAUD
13 years ago
commit
c68436fa42
@ -0,0 +1,33 @@ |
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/*
|
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* mux.c |
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* |
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation version 2. |
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* |
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any |
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* kind, whether express or implied; without even the implied warranty |
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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|
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#include <common.h> |
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#include <asm/arch/mux.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/io.h> |
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|
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/*
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* Configure the pin mux for the module |
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*/ |
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void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux) |
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{ |
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int i; |
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if (!mod_pin_mux) |
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return; |
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for (i = 0; mod_pin_mux[i].reg_offset != -1; i++) |
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MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset); |
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} |
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@ -0,0 +1,261 @@ |
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/*
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* mux.h |
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* |
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation version 2. |
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* |
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any |
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* kind, whether express or implied; without even the implied warranty |
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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|
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#ifndef _MUX_H_ |
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#define _MUX_H_ |
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#include <common.h> |
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#include <asm/io.h> |
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#define MUX_CFG(value, offset) \ |
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__raw_writel(value, (CTRL_BASE + offset)); |
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/* PAD Control Fields */ |
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#define SLEWCTRL (0x1 << 6) |
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#define RXACTIVE (0x1 << 5) |
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#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */ |
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#define PULLUDEN (0x0 << 3) /* Pull up enabled */ |
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#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ |
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#define MODE(val) val /* used for Readability */ |
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|
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/*
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* PAD CONTROL OFFSETS |
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* Field names corresponds to the pad signal name |
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*/ |
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struct pad_signals { |
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int gpmc_ad0; |
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int gpmc_ad1; |
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int gpmc_ad2; |
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int gpmc_ad3; |
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int gpmc_ad4; |
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int gpmc_ad5; |
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int gpmc_ad6; |
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int gpmc_ad7; |
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int gpmc_ad8; |
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int gpmc_ad9; |
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int gpmc_ad10; |
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int gpmc_ad11; |
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int gpmc_ad12; |
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int gpmc_ad13; |
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int gpmc_ad14; |
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int gpmc_ad15; |
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int gpmc_a0; |
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int gpmc_a1; |
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int gpmc_a2; |
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int gpmc_a3; |
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int gpmc_a4; |
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int gpmc_a5; |
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int gpmc_a6; |
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int gpmc_a7; |
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int gpmc_a8; |
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int gpmc_a9; |
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int gpmc_a10; |
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int gpmc_a11; |
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int gpmc_wait0; |
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int gpmc_wpn; |
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int gpmc_be1n; |
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int gpmc_csn0; |
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int gpmc_csn1; |
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int gpmc_csn2; |
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int gpmc_csn3; |
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int gpmc_clk; |
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int gpmc_advn_ale; |
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int gpmc_oen_ren; |
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int gpmc_wen; |
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int gpmc_be0n_cle; |
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int lcd_data0; |
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int lcd_data1; |
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int lcd_data2; |
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int lcd_data3; |
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int lcd_data4; |
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int lcd_data5; |
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int lcd_data6; |
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int lcd_data7; |
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int lcd_data8; |
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int lcd_data9; |
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int lcd_data10; |
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int lcd_data11; |
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int lcd_data12; |
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int lcd_data13; |
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int lcd_data14; |
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int lcd_data15; |
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int lcd_vsync; |
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int lcd_hsync; |
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int lcd_pclk; |
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int lcd_ac_bias_en; |
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int mmc0_dat3; |
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int mmc0_dat2; |
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int mmc0_dat1; |
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int mmc0_dat0; |
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int mmc0_clk; |
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int mmc0_cmd; |
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int mii1_col; |
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int mii1_crs; |
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int mii1_rxerr; |
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int mii1_txen; |
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int mii1_rxdv; |
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int mii1_txd3; |
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int mii1_txd2; |
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int mii1_txd1; |
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int mii1_txd0; |
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int mii1_txclk; |
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int mii1_rxclk; |
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int mii1_rxd3; |
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int mii1_rxd2; |
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int mii1_rxd1; |
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int mii1_rxd0; |
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int rmii1_refclk; |
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int mdio_data; |
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int mdio_clk; |
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int spi0_sclk; |
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int spi0_d0; |
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int spi0_d1; |
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int spi0_cs0; |
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int spi0_cs1; |
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int ecap0_in_pwm0_out; |
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int uart0_ctsn; |
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int uart0_rtsn; |
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int uart0_rxd; |
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int uart0_txd; |
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int uart1_ctsn; |
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int uart1_rtsn; |
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int uart1_rxd; |
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int uart1_txd; |
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int i2c0_sda; |
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int i2c0_scl; |
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int mcasp0_aclkx; |
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int mcasp0_fsx; |
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int mcasp0_axr0; |
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int mcasp0_ahclkr; |
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int mcasp0_aclkr; |
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int mcasp0_fsr; |
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int mcasp0_axr1; |
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int mcasp0_ahclkx; |
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int xdma_event_intr0; |
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int xdma_event_intr1; |
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int nresetin_out; |
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int porz; |
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int nnmi; |
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int osc0_in; |
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int osc0_out; |
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int rsvd1; |
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int tms; |
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int tdi; |
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int tdo; |
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int tck; |
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int ntrst; |
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int emu0; |
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int emu1; |
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int osc1_in; |
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int osc1_out; |
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int pmic_power_en; |
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int rtc_porz; |
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int rsvd2; |
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int ext_wakeup; |
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int enz_kaldo_1p8v; |
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int usb0_dm; |
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int usb0_dp; |
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int usb0_ce; |
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int usb0_id; |
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int usb0_vbus; |
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int usb0_drvvbus; |
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int usb1_dm; |
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int usb1_dp; |
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int usb1_ce; |
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int usb1_id; |
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int usb1_vbus; |
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int usb1_drvvbus; |
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int ddr_resetn; |
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int ddr_csn0; |
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int ddr_cke; |
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int ddr_ck; |
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int ddr_nck; |
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int ddr_casn; |
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int ddr_rasn; |
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int ddr_wen; |
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int ddr_ba0; |
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int ddr_ba1; |
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int ddr_ba2; |
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int ddr_a0; |
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int ddr_a1; |
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int ddr_a2; |
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int ddr_a3; |
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int ddr_a4; |
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int ddr_a5; |
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int ddr_a6; |
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int ddr_a7; |
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int ddr_a8; |
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int ddr_a9; |
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int ddr_a10; |
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int ddr_a11; |
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int ddr_a12; |
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int ddr_a13; |
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int ddr_a14; |
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int ddr_a15; |
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int ddr_odt; |
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int ddr_d0; |
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int ddr_d1; |
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int ddr_d2; |
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int ddr_d3; |
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int ddr_d4; |
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int ddr_d5; |
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int ddr_d6; |
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int ddr_d7; |
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int ddr_d8; |
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int ddr_d9; |
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int ddr_d10; |
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int ddr_d11; |
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int ddr_d12; |
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int ddr_d13; |
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int ddr_d14; |
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int ddr_d15; |
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int ddr_dqm0; |
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int ddr_dqm1; |
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int ddr_dqs0; |
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int ddr_dqsn0; |
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int ddr_dqs1; |
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int ddr_dqsn1; |
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int ddr_vref; |
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int ddr_vtp; |
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int ddr_strben0; |
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int ddr_strben1; |
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int ain7; |
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int ain6; |
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int ain5; |
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int ain4; |
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int ain3; |
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int ain2; |
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int ain1; |
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int ain0; |
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int vrefp; |
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int vrefn; |
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}; |
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struct module_pin_mux { |
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short reg_offset; |
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unsigned char val; |
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}; |
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/* Pad control register offset */ |
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#define PAD_CTRL_BASE 0x800 |
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#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \ |
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(PAD_CTRL_BASE))->x) |
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/*
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* Configure the pin mux for the module |
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*/ |
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void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux); |
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#endif |
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@ -0,0 +1,376 @@ |
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/*
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* board.c |
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* |
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* Board functions for TI AM335X based boards |
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* |
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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#include <common.h> |
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#include <errno.h> |
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#include <spl.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/omap.h> |
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#include <asm/arch/ddr_defs.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/gpio.h> |
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#include <asm/arch/mmc_host_def.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/io.h> |
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#include <asm/emif.h> |
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#include <asm/gpio.h> |
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#include <i2c.h> |
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#include <miiphy.h> |
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#include <cpsw.h> |
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#include "board.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; |
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#ifdef CONFIG_SPL_BUILD |
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static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; |
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#endif |
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/* MII mode defines */ |
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#define MII_MODE_ENABLE 0x0 |
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#define RGMII_MODE_ENABLE 0xA |
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/* GPIO that controls power to DDR on EVM-SK */ |
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#define GPIO_DDR_VTT_EN 7 |
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; |
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static struct am335x_baseboard_id __attribute__((section (".data"))) header; |
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static inline int board_is_bone(void) |
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{ |
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return !strncmp(header.name, "A335BONE", HDR_NAME_LEN); |
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} |
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static inline int board_is_bone_lt(void) |
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{ |
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return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN); |
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} |
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static inline int board_is_evm_sk(void) |
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{ |
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return !strncmp("A335X_SK", header.name, HDR_NAME_LEN); |
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} |
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/*
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* Read header information from EEPROM into global structure. |
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*/ |
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static int read_eeprom(void) |
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{ |
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/* Check if baseboard eeprom is available */ |
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if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { |
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puts("Could not probe the EEPROM; something fundamentally " |
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"wrong on the I2C bus.\n"); |
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return -ENODEV; |
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} |
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/* read the eeprom using i2c */ |
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header, |
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sizeof(header))) { |
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puts("Could not read the EEPROM; something fundamentally" |
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" wrong on the I2C bus.\n"); |
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return -EIO; |
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} |
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if (header.magic != 0xEE3355AA) { |
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/*
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* read the eeprom using i2c again, |
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* but use only a 1 byte address |
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*/ |
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, |
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(uchar *)&header, sizeof(header))) { |
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puts("Could not read the EEPROM; something " |
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"fundamentally wrong on the I2C bus.\n"); |
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return -EIO; |
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} |
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if (header.magic != 0xEE3355AA) { |
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printf("Incorrect magic number (0x%x) in EEPROM\n", |
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header.magic); |
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return -EINVAL; |
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} |
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} |
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return 0; |
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} |
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|
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/* UART Defines */ |
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#ifdef CONFIG_SPL_BUILD |
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#define UART_RESET (0x1 << 1) |
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#define UART_CLK_RUNNING_MASK 0x1 |
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#define UART_SMART_IDLE_EN (0x1 << 0x3) |
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static void rtc32k_enable(void) |
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{ |
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struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE; |
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/*
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* Unlock the RTC's registers. For more details please see the |
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* RTC_SS section of the TRM. In order to unlock we need to |
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* write these specific values (keys) in this order. |
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*/ |
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writel(0x83e70b13, &rtc->kick0r); |
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writel(0x95a4f1e0, &rtc->kick1r); |
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|
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/* Enable the RTC 32K OSC by setting bits 3 and 6. */ |
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writel((1 << 3) | (1 << 6), &rtc->osc); |
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} |
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|
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static const struct ddr_data ddr2_data = { |
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.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | |
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(MT47H128M16RT25E_RD_DQS<<20) | |
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(MT47H128M16RT25E_RD_DQS<<10) | |
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(MT47H128M16RT25E_RD_DQS<<0)), |
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.datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) | |
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(MT47H128M16RT25E_WR_DQS<<20) | |
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(MT47H128M16RT25E_WR_DQS<<10) | |
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(MT47H128M16RT25E_WR_DQS<<0)), |
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.datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) | |
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(MT47H128M16RT25E_PHY_WRLVL<<20) | |
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(MT47H128M16RT25E_PHY_WRLVL<<10) | |
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(MT47H128M16RT25E_PHY_WRLVL<<0)), |
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.datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) | |
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(MT47H128M16RT25E_PHY_GATELVL<<20) | |
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(MT47H128M16RT25E_PHY_GATELVL<<10) | |
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(MT47H128M16RT25E_PHY_GATELVL<<0)), |
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.datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) | |
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(MT47H128M16RT25E_PHY_FIFO_WE<<20) | |
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(MT47H128M16RT25E_PHY_FIFO_WE<<10) | |
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(MT47H128M16RT25E_PHY_FIFO_WE<<0)), |
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.datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) | |
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(MT47H128M16RT25E_PHY_WR_DATA<<20) | |
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(MT47H128M16RT25E_PHY_WR_DATA<<10) | |
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(MT47H128M16RT25E_PHY_WR_DATA<<0)), |
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.datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY, |
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.datadldiff0 = PHY_DLL_LOCK_DIFF, |
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}; |
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|
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static const struct cmd_control ddr2_cmd_ctrl_data = { |
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.cmd0csratio = MT47H128M16RT25E_RATIO, |
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.cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, |
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.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, |
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|
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.cmd1csratio = MT47H128M16RT25E_RATIO, |
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.cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, |
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.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, |
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|
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.cmd2csratio = MT47H128M16RT25E_RATIO, |
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.cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, |
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.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, |
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}; |
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|
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static const struct emif_regs ddr2_emif_reg_data = { |
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.sdram_config = MT47H128M16RT25E_EMIF_SDCFG, |
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.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, |
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.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, |
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.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, |
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.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, |
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.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, |
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}; |
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|
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static const struct ddr_data ddr3_data = { |
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.datardsratio0 = MT41J128MJT125_RD_DQS, |
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.datawdsratio0 = MT41J128MJT125_WR_DQS, |
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.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, |
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.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, |
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.datadldiff0 = PHY_DLL_LOCK_DIFF, |
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}; |
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|
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static const struct cmd_control ddr3_cmd_ctrl_data = { |
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.cmd0csratio = MT41J128MJT125_RATIO, |
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.cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF, |
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.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, |
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|
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.cmd1csratio = MT41J128MJT125_RATIO, |
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.cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF, |
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.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, |
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|
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.cmd2csratio = MT41J128MJT125_RATIO, |
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.cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF, |
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.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, |
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}; |
||||
|
||||
static struct emif_regs ddr3_emif_reg_data = { |
||||
.sdram_config = MT41J128MJT125_EMIF_SDCFG, |
||||
.ref_ctrl = MT41J128MJT125_EMIF_SDREF, |
||||
.sdram_tim1 = MT41J128MJT125_EMIF_TIM1, |
||||
.sdram_tim2 = MT41J128MJT125_EMIF_TIM2, |
||||
.sdram_tim3 = MT41J128MJT125_EMIF_TIM3, |
||||
.zq_config = MT41J128MJT125_ZQ_CFG, |
||||
.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY, |
||||
}; |
||||
#endif |
||||
|
||||
/*
|
||||
* early system init of muxing and clocks. |
||||
*/ |
||||
void s_init(void) |
||||
{ |
||||
/* WDT1 is already running when the bootloader gets control
|
||||
* Disable it to avoid "random" resets |
||||
*/ |
||||
writel(0xAAAA, &wdtimer->wdtwspr); |
||||
while (readl(&wdtimer->wdtwwps) != 0x0) |
||||
; |
||||
writel(0x5555, &wdtimer->wdtwspr); |
||||
while (readl(&wdtimer->wdtwwps) != 0x0) |
||||
; |
||||
|
||||
#ifdef CONFIG_SPL_BUILD |
||||
/* Setup the PLLs and the clocks for the peripherals */ |
||||
pll_init(); |
||||
|
||||
/* Enable RTC32K clock */ |
||||
rtc32k_enable(); |
||||
|
||||
/* UART softreset */ |
||||
u32 regVal; |
||||
|
||||
enable_uart0_pin_mux(); |
||||
|
||||
regVal = readl(&uart_base->uartsyscfg); |
||||
regVal |= UART_RESET; |
||||
writel(regVal, &uart_base->uartsyscfg); |
||||
while ((readl(&uart_base->uartsyssts) & |
||||
UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) |
||||
; |
||||
|
||||
/* Disable smart idle */ |
||||
regVal = readl(&uart_base->uartsyscfg); |
||||
regVal |= UART_SMART_IDLE_EN; |
||||
writel(regVal, &uart_base->uartsyscfg); |
||||
|
||||
gd = &gdata; |
||||
|
||||
preloader_console_init(); |
||||
|
||||
/* Initalize the board header */ |
||||
enable_i2c0_pin_mux(); |
||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
||||
if (read_eeprom() < 0) |
||||
puts("Could not get board ID.\n"); |
||||
|
||||
enable_board_pin_mux(&header); |
||||
if (board_is_evm_sk()) { |
||||
/*
|
||||
* EVM SK 1.2A and later use gpio0_7 to enable DDR3. |
||||
* This is safe enough to do on older revs. |
||||
*/ |
||||
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); |
||||
gpio_direction_output(GPIO_DDR_VTT_EN, 1); |
||||
} |
||||
|
||||
if (board_is_evm_sk() || board_is_bone_lt()) |
||||
config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, |
||||
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data); |
||||
else |
||||
config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data, |
||||
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data); |
||||
#endif |
||||
} |
||||
|
||||
/*
|
||||
* Basic board specific setup. Pinmux has been handled already. |
||||
*/ |
||||
int board_init(void) |
||||
{ |
||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
||||
if (read_eeprom() < 0) |
||||
puts("Could not get board ID.\n"); |
||||
|
||||
gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_DRIVER_TI_CPSW |
||||
static void cpsw_control(int enabled) |
||||
{ |
||||
/* VTP can be added here */ |
||||
|
||||
return; |
||||
} |
||||
|
||||
static struct cpsw_slave_data cpsw_slaves[] = { |
||||
{ |
||||
.slave_reg_ofs = 0x208, |
||||
.sliver_reg_ofs = 0xd80, |
||||
.phy_id = 0, |
||||
}, |
||||
{ |
||||
.slave_reg_ofs = 0x308, |
||||
.sliver_reg_ofs = 0xdc0, |
||||
.phy_id = 1, |
||||
}, |
||||
}; |
||||
|
||||
static struct cpsw_platform_data cpsw_data = { |
||||
.mdio_base = AM335X_CPSW_MDIO_BASE, |
||||
.cpsw_base = AM335X_CPSW_BASE, |
||||
.mdio_div = 0xff, |
||||
.channels = 8, |
||||
.cpdma_reg_ofs = 0x800, |
||||
.slaves = 1, |
||||
.slave_data = cpsw_slaves, |
||||
.ale_reg_ofs = 0xd00, |
||||
.ale_entries = 1024, |
||||
.host_port_reg_ofs = 0x108, |
||||
.hw_stats_reg_ofs = 0x900, |
||||
.mac_control = (1 << 5), |
||||
.control = cpsw_control, |
||||
.host_port_num = 0, |
||||
.version = CPSW_CTRL_VERSION_2, |
||||
}; |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
uint8_t mac_addr[6]; |
||||
uint32_t mac_hi, mac_lo; |
||||
|
||||
if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { |
||||
debug("<ethaddr> not set. Reading from E-fuse\n"); |
||||
/* try reading mac address from efuse */ |
||||
mac_lo = readl(&cdev->macid0l); |
||||
mac_hi = readl(&cdev->macid0h); |
||||
mac_addr[0] = mac_hi & 0xFF; |
||||
mac_addr[1] = (mac_hi & 0xFF00) >> 8; |
||||
mac_addr[2] = (mac_hi & 0xFF0000) >> 16; |
||||
mac_addr[3] = (mac_hi & 0xFF000000) >> 24; |
||||
mac_addr[4] = mac_lo & 0xFF; |
||||
mac_addr[5] = (mac_lo & 0xFF00) >> 8; |
||||
|
||||
if (is_valid_ether_addr(mac_addr)) |
||||
eth_setenv_enetaddr("ethaddr", mac_addr); |
||||
else |
||||
return -1; |
||||
} |
||||
|
||||
if (board_is_bone() || board_is_bone_lt()) { |
||||
writel(MII_MODE_ENABLE, &cdev->miisel); |
||||
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = |
||||
PHY_INTERFACE_MODE_MII; |
||||
} else { |
||||
writel(RGMII_MODE_ENABLE, &cdev->miisel); |
||||
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = |
||||
PHY_INTERFACE_MODE_RGMII; |
||||
} |
||||
|
||||
return cpsw_register(&cpsw_data); |
||||
} |
||||
#endif |
||||
@ -0,0 +1,49 @@ |
||||
/*
|
||||
* board.h |
||||
* |
||||
* TI AM335x boards information header |
||||
* |
||||
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
*/ |
||||
|
||||
#ifndef _BOARD_H_ |
||||
#define _BOARD_H_ |
||||
|
||||
/*
|
||||
* TI AM335x parts define a system EEPROM that defines certain sub-fields. |
||||
* We use these fields to in turn see what board we are on, and what |
||||
* that might require us to set or not set. |
||||
*/ |
||||
#define HDR_NO_OF_MAC_ADDR 3 |
||||
#define HDR_ETH_ALEN 6 |
||||
#define HDR_NAME_LEN 8 |
||||
|
||||
struct am335x_baseboard_id { |
||||
unsigned int magic; |
||||
char name[HDR_NAME_LEN]; |
||||
char version[4]; |
||||
char serial[12]; |
||||
char config[32]; |
||||
char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN]; |
||||
}; |
||||
|
||||
/*
|
||||
* We have three pin mux functions that must exist. We must be able to enable |
||||
* uart0, for initial output and i2c0 to read the main EEPROM. We then have a |
||||
* main pinmux function that can be overridden to enable all other pinmux that |
||||
* is required on the board. |
||||
*/ |
||||
void enable_uart0_pin_mux(void); |
||||
void enable_i2c0_pin_mux(void); |
||||
void enable_board_pin_mux(struct am335x_baseboard_id *header); |
||||
#endif |
||||
Loading…
Reference in new issue