This adds the bare minimum code to support Tegra186, with UART and eMMC working. The empty gpio.h is required because <asm/gpio.h> includes it. A future cleanup round may be able to solve this for all Tegra generations at once. mach-tegra/Makefile is adjusted not to compile anything for Tegra186, but instead to defer everything to mach-tegra/tegra186/Makefile. This allows the SoC code to pick-and-choose which of the C files in the "common" mach-tegra/ directory to compile in based on the SoC's needs. Most of the code is not valid for Tegra186, and this approach removes the need for mach-tegra/Makefile to contain many SoC-specific ifdefs. This approach may be applied to all other Tegra SoCs in a future cleanup round. board186.c is introduced to replace board.c and board2.c. These files currently contain a slew of SoC- and board-specific code that is not valid for Tegra186. This approach avoids adding yet more ifdefs to those files. A future cleanup round may refactor most of board*.c into board-/ SoC-specific functions files thus allowing the top-level functions like board_init_early_f to be shared again. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>master
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39f633320c
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#include "skeleton.dtsi" |
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#include <dt-bindings/gpio/tegra-gpio.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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/ { |
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compatible = "nvidia,tegra186"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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gpio@2200000 { |
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compatible = "nvidia,tegra186-gpio"; |
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reg-names = "security", "gpio"; |
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reg = |
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<0x0 0x2200000 0x0 0x10000>, |
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<0x0 0x2210000 0x0 0x10000>; |
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interrupts = |
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<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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uarta: serial@3100000 { |
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compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; |
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reg = <0x0 0x03100000 0x0 0x10000>; |
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reg-shift = <2>; |
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status = "disabled"; |
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}; |
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sdhci@3460000 { |
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compatible = "nvidia,tegra186-sdhci"; |
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reg = <0x0 0x03460000 0x0 0x200>; |
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interrupts = <GIC_SPI 31 0x04>; |
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status = "disabled"; |
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}; |
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gpio@c2f0000 { |
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compatible = "nvidia,tegra186-gpio-aon"; |
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reg-names = "security", "gpio"; |
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reg = |
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<0x0 0xc2f0000 0x0 0x1000>, |
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<0x0 0xc2f1000 0x0 0x1000>; |
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interrupts = |
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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}; |
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/*
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* Copyright (c) 2016, NVIDIA CORPORATION. |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#ifndef _TEGRA186_GPIO_H_ |
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#define _TEGRA186_GPIO_H_ |
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#endif |
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/*
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* (C) Copyright 2013-2016, NVIDIA CORPORATION. |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#ifndef _TEGRA186_TEGRA_H_ |
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#define _TEGRA186_TEGRA_H_ |
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#define GICD_BASE 0x03881000 /* Generic Int Cntrlr Distrib */ |
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#define GICC_BASE 0x03882000 /* Generic Int Cntrlr CPU I/F */ |
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#define NV_PA_SDRAM_BASE 0x80000000 |
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#include <asm/arch-tegra/tegra.h> |
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#endif |
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/*
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* Copyright (c) 2016, NVIDIA CORPORATION. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/arch/tegra.h> |
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#include <asm/arch-tegra/mmc.h> |
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#include <asm/arch-tegra/tegra_mmc.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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int dram_init(void) |
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{ |
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gd->ram_size = (1.5 * 1024 * 1024 * 1024); |
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return 0; |
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} |
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int board_early_init_f(void) |
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{ |
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return 0; |
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} |
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int board_init(void) |
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{ |
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return 0; |
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} |
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int board_late_init(void) |
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{ |
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return 0; |
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} |
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void dram_init_banksize(void) |
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{ |
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; |
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gd->bd->bi_dram[0].size = gd->ram_size; |
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} |
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void pad_init_mmc(struct mmc_host *host) |
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{ |
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} |
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int board_mmc_init(bd_t *bd) |
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{ |
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tegra_mmc_init(); |
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return 0; |
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} |
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int ft_system_setup(void *blob, bd_t *bd) |
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{ |
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return 0; |
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} |
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# Copyright (c) 2016, NVIDIA CORPORATION. |
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# |
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# SPDX-License-Identifier: GPL-2.0 |
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if TEGRA186 |
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choice |
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prompt "Tegra186 board select" |
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endchoice |
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config SYS_SOC |
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default "tegra186" |
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endif |
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# Copyright (c) 2016, NVIDIA CORPORATION.
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#
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# SPDX-License-Identifier: GPL-2.0
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obj-y += ../arm64-mmu.o
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obj-y += ../board186.o
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obj-y += ../lowlevel_init.o
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obj-$(CONFIG_DISPLAY_CPUINFO) += ../sys_info.o
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/*
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* Copyright 2013-2016, NVIDIA CORPORATION. |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#ifndef _TEGRA186_COMMON_H_ |
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#define _TEGRA186_COMMON_H_ |
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#include "tegra-common.h" |
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/* Cortex-A57 uses a cache line size of 64 bytes */ |
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#define CONFIG_SYS_CACHELINE_SIZE 64 |
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/*
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* NS16550 Configuration |
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*/ |
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#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ |
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/*
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* Miscellaneous configurable options |
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*/ |
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#define CONFIG_STACKBASE 0x82800000 /* 40MB */ |
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/*-----------------------------------------------------------------------
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* Physical Memory Map |
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*/ |
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#define CONFIG_SYS_TEXT_BASE 0x80080000 |
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/* Generic Interrupt Controller */ |
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#define CONFIG_GICV2 |
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/*
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* Memory layout for where various images get loaded by boot scripts: |
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* |
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* scriptaddr can be pretty much anywhere that doesn't conflict with something |
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* else. Put it above BOOTMAPSZ to eliminate conflicts. |
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* |
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* pxefile_addr_r can be pretty much anywhere that doesn't conflict with |
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* something else. Put it above BOOTMAPSZ to eliminate conflicts. |
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* |
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* kernel_addr_r must be within the first 128M of RAM in order for the |
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* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will |
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* decompress itself to 0x8000 after the start of RAM, kernel_addr_r |
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* should not overlap that area, or the kernel will have to copy itself |
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* somewhere else before decompression. Similarly, the address of any other |
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* data passed to the kernel shouldn't overlap the start of RAM. Pushing |
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* this up to 16M allows for a sizable kernel to be decompressed below the |
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* compressed load address. |
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* |
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* fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for |
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* the compressed kernel to be up to 16M too. |
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* |
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* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows |
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* for the FDT/DTB to be up to 1M, which is hopefully plenty. |
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*/ |
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#define CONFIG_LOADADDR 0x80080000 |
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#define MEM_LAYOUT_ENV_SETTINGS \ |
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"scriptaddr=0x90000000\0" \
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"pxefile_addr_r=0x90100000\0" \
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"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
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"fdt_addr_r=0x82000000\0" \
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"ramdisk_addr_r=0x82100000\0" |
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/* Defines for SPL */ |
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#define CONFIG_SPL_TEXT_BASE 0x80108000 |
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#define CONFIG_SYS_SPL_MALLOC_START 0x80090000 |
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#define CONFIG_SPL_STACK 0x800ffffc |
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#endif |
Loading…
Reference in new issue