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MPC5xxx: Change names of defines related to IPB and PCI clocks.

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Both CFG_PCISPEED_66 and CFG_IPBSPEED_133 are misnamed, as defining
them does not cause PCI or IPB clocks to run at the specified speed.
Instead, they configure divisors used to calculate said clocks. This
patch renames the defines according to their real function.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
master
Bartlomiej Sieka 18 years ago
parent a11c0b85dc
commit c99512d6bd
21 changed files with 61 additions and 61 deletions
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  1. 8
      cpu/mpc5xxx/cpu_init.c
  2. 12
      include/configs/BC3450.h
  3. 4
      include/configs/IceCube.h
  4. 2
      include/configs/PM520.h
  5. 12
      include/configs/TB5200.h
  6. 2
      include/configs/TOP5200.h
  7. 12
      include/configs/TQM5200.h
  8. 2
      include/configs/Total5200.h
  9. 12
      include/configs/aev.h
  10. 2
      include/configs/canmb.h
  11. 2
      include/configs/cpci5200.h
  12. 2
      include/configs/hmi1001.h
  13. 2
      include/configs/inka4x0.h
  14. 2
      include/configs/mcc200.h
  15. 4
      include/configs/motionpro.h
  16. 12
      include/configs/o2dnt.h
  17. 2
      include/configs/pf5200.h
  18. 12
      include/configs/smmaco4.h
  19. 12
      include/configs/spieval.h
  20. 2
      include/configs/uc101.h
  21. 2
      include/configs/v38b.h

8
cpu/mpc5xxx/cpu_init.c
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@ -156,21 +156,21 @@ void cpu_init_f (void)
*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15);
*(vu_long *)(MPC5XXX_XLBARB + 0x70) = CFG_SDRAM_BASE | 0x1d;
# if defined(CFG_IPBSPEED_133)
# if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/* Motorola reports IPB should better run at 133 MHz. */
*(vu_long *)MPC5XXX_ADDECR |= 1;
/* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
addecr = *(vu_long *)MPC5XXX_CDM_CFG;
addecr &= ~0x103;
# if defined(CFG_PCISPEED_66)
# if defined(CFG_PCICLK_EQUALS_IPBCLK_DIV2)
/* pci_clk_sel = 0x01 -> IPB_CLK/2 */
addecr |= 0x01;
# else
/* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */
addecr |= 0x02;
# endif /* CFG_PCISPEED_66 */
# endif /* CFG_PCICLK_EQUALS_IPBCLK_DIV2 */
*(vu_long *)MPC5XXX_CDM_CFG = addecr;
# endif /* CFG_IPBSPEED_133 */
# endif /* CFG_IPBCLK_EQUALS_XLBCLK */
/* Configure the XLB Arbiter */
*(vu_long *)MPC5XXX_XLBARB_MPRIEN = 0xff;
*(vu_long *)MPC5XXX_XLBARB_MPRIVAL = 0x11111111;

12
include/configs/BC3450.h
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@ -282,17 +282,17 @@
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
* CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet
* hasn't been tested with a IPB Bus Clock of 66 MHz.
* CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
#if defined(CFG_IPBSPEED_133)
# define CFG_PCISPEED_66 /* define for 66MHz speed */
#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
# define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
@ -488,7 +488,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
#ifdef CFG_PCISPEED_66
#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
# define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
# define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */

4
include/configs/IceCube.h
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@ -167,9 +167,9 @@
* IPB Bus clocking configuration.
*/
#if defined(CONFIG_LITE5200B)
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#else
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
#endif /* CONFIG_MPC5200 */

2
include/configs/PM520.h
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@ -160,7 +160,7 @@
/*
* IPB Bus clocking configuration.
*/
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
/*
* I2C configuration

12
include/configs/TB5200.h
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@ -200,17 +200,17 @@
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#if defined(CFG_IPBSPEED_133)
#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
* CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
* been tested with a IPB Bus Clock of 66 MHz.
* CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
#define CFG_PCISPEED_66 /* define for 66MHz speed */
#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
@ -432,7 +432,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
#ifdef CFG_PCISPEED_66
#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */

2
include/configs/TOP5200.h
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@ -186,7 +186,7 @@
/*
* IPB Bus clocking configuration.
*/
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* I2C configuration

12
include/configs/TQM5200.h
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@ -269,17 +269,17 @@
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#if defined(CFG_IPBSPEED_133) && !defined(CONFIG_CAM5200)
#if defined(CFG_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
* CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
* been tested with a IPB Bus Clock of 66 MHz.
* CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of
* 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
#define CFG_PCISPEED_66 /* define for 66MHz speed */
#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
@ -594,7 +594,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
#ifdef CFG_PCISPEED_66
#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */

2
include/configs/Total5200.h
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@ -183,7 +183,7 @@
/*
* IPB Bus clocking configuration.
*/
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
/*

12
include/configs/aev.h
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@ -166,17 +166,17 @@
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#if defined(CFG_IPBSPEED_133)
#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
* CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
* been tested with a IPB Bus Clock of 66 MHz.
* CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
#define CFG_PCISPEED_66 /* define for 66MHz speed */
#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
@ -362,7 +362,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
#ifdef CFG_PCISPEED_66
#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */

2
include/configs/canmb.h
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@ -111,7 +111,7 @@
/*
* IPB Bus clocking configuration.
*/
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* Flash configuration, expect one 16 Megabyte Bank at most

2
include/configs/cpci5200.h
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@ -179,7 +179,7 @@
/*
* IPB Bus clocking configuration.
*/
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
/*
* I2C configuration

2
include/configs/hmi1001.h
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@ -110,7 +110,7 @@
/*
* IPB Bus clocking configuration.
*/
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* I2C configuration

2
include/configs/inka4x0.h
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@ -147,7 +147,7 @@
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* Flash configuration

2
include/configs/mcc200.h
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@ -169,7 +169,7 @@
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* I2C configuration

4
include/configs/motionpro.h
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@ -160,9 +160,9 @@
/*
* Set IPB speed to 100MHz (yes, the #define is misnamed)
* Set IPB speed to 100MHz
*/
#define CFG_IPBSPEED_133
#define CFG_IPBCLK_EQUALS_XLBCLK
/*

12
include/configs/o2dnt.h
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@ -137,17 +137,17 @@
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#if defined(CFG_IPBSPEED_133)
#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
* CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
* been tested with a IPB Bus Clock of 66 MHz.
* CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
#define CFG_PCISPEED_66 /* define for 66MHz speed */
#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
#endif
@ -276,7 +276,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
#ifdef CFG_PCISPEED_66
#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
/*
* For 66 MHz PCI clock additional Wait State is needed for CS0 (flash).
*/

2
include/configs/pf5200.h
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@ -171,7 +171,7 @@
/*
* IPB Bus clocking configuration.
*/
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
/*
* I2C configuration

12
include/configs/smmaco4.h
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@ -138,17 +138,17 @@
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#if defined(CFG_IPBSPEED_133)
#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
* CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
* been tested with a IPB Bus Clock of 66 MHz.
* CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
#define CFG_PCISPEED_66 /* define for 66MHz speed */
#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
@ -357,7 +357,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
#ifdef CFG_PCISPEED_66
#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */

12
include/configs/spieval.h
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@ -219,17 +219,17 @@
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#if defined(CFG_IPBSPEED_133)
#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
* CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
* been tested with a IPB Bus Clock of 66 MHz.
* CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
#define CFG_PCISPEED_66 /* define for 66MHz speed */
#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
@ -444,7 +444,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
#ifdef CFG_PCISPEED_66
#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */

2
include/configs/uc101.h
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@ -114,7 +114,7 @@
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* I2C configuration

2
include/configs/v38b.h
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@ -167,7 +167,7 @@
/*
* IPB Bus clocking configuration.
*/
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
/*

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