Add device tree support to allow for CONFIG_OF_CONTROL in OMAP3630 boards. DM3730 can use this same device tree. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>master
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cac4d6a680
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/* |
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* Device Tree Source for OMAP34XX/OMAP36XX clock data |
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* |
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* Copyright (C) 2013 Texas Instruments, Inc. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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*/ |
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&cm_clocks { |
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security_l4_ick2: security_l4_ick2 { |
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#clock-cells = <0>; |
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compatible = "fixed-factor-clock"; |
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clocks = <&l4_ick>; |
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clock-mult = <1>; |
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clock-div = <1>; |
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}; |
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|
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aes1_ick: aes1_ick@a14 { |
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#clock-cells = <0>; |
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compatible = "ti,omap3-interface-clock"; |
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clocks = <&security_l4_ick2>; |
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ti,bit-shift = <3>; |
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reg = <0x0a14>; |
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}; |
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|
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rng_ick: rng_ick@a14 { |
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#clock-cells = <0>; |
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compatible = "ti,omap3-interface-clock"; |
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clocks = <&security_l4_ick2>; |
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reg = <0x0a14>; |
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ti,bit-shift = <2>; |
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}; |
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|
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sha11_ick: sha11_ick@a14 { |
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#clock-cells = <0>; |
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compatible = "ti,omap3-interface-clock"; |
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clocks = <&security_l4_ick2>; |
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reg = <0x0a14>; |
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ti,bit-shift = <1>; |
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}; |
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|
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des1_ick: des1_ick@a14 { |
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#clock-cells = <0>; |
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compatible = "ti,omap3-interface-clock"; |
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clocks = <&security_l4_ick2>; |
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reg = <0x0a14>; |
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ti,bit-shift = <0>; |
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}; |
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|
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cam_mclk: cam_mclk@f00 { |
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#clock-cells = <0>; |
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compatible = "ti,gate-clock"; |
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clocks = <&dpll4_m5x2_ck>; |
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ti,bit-shift = <0>; |
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reg = <0x0f00>; |
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ti,set-rate-parent; |
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}; |
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|
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cam_ick: cam_ick@f10 { |
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#clock-cells = <0>; |
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compatible = "ti,omap3-no-wait-interface-clock"; |
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clocks = <&l4_ick>; |
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reg = <0x0f10>; |
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ti,bit-shift = <0>; |
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}; |
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|
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csi2_96m_fck: csi2_96m_fck@f00 { |
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#clock-cells = <0>; |
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compatible = "ti,gate-clock"; |
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clocks = <&core_96m_fck>; |
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reg = <0x0f00>; |
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ti,bit-shift = <1>; |
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}; |
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|
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security_l3_ick: security_l3_ick { |
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#clock-cells = <0>; |
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compatible = "fixed-factor-clock"; |
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clocks = <&l3_ick>; |
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clock-mult = <1>; |
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clock-div = <1>; |
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}; |
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|
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pka_ick: pka_ick@a14 { |
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#clock-cells = <0>; |
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compatible = "ti,omap3-interface-clock"; |
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clocks = <&security_l3_ick>; |
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reg = <0x0a14>; |
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ti,bit-shift = <4>; |
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}; |
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|
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icr_ick: icr_ick@a10 { |
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#clock-cells = <0>; |
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compatible = "ti,omap3-interface-clock"; |
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clocks = <&core_l4_ick>; |
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reg = <0x0a10>; |
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ti,bit-shift = <29>; |
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}; |
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|
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des2_ick: des2_ick@a10 { |
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#clock-cells = <0>; |
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compatible = "ti,omap3-interface-clock"; |
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clocks = <&core_l4_ick>; |
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reg = <0x0a10>; |
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ti,bit-shift = <26>; |
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}; |
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|
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mspro_ick: mspro_ick@a10 { |
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#clock-cells = <0>; |
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compatible = "ti,omap3-interface-clock"; |
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clocks = <&core_l4_ick>; |
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reg = <0x0a10>; |
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ti,bit-shift = <23>; |
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}; |
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|
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mailboxes_ick: mailboxes_ick@a10 { |
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#clock-cells = <0>; |
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compatible = "ti,omap3-interface-clock"; |
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clocks = <&core_l4_ick>; |
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reg = <0x0a10>; |
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ti,bit-shift = <7>; |
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}; |
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|
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ssi_l4_ick: ssi_l4_ick { |
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#clock-cells = <0>; |
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compatible = "fixed-factor-clock"; |
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clocks = <&l4_ick>; |
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clock-mult = <1>; |
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clock-div = <1>; |
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}; |
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|
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sr1_fck: sr1_fck@c00 { |
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#clock-cells = <0>; |
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compatible = "ti,wait-gate-clock"; |
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clocks = <&sys_ck>; |
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reg = <0x0c00>; |
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ti,bit-shift = <6>; |
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}; |
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sr2_fck: sr2_fck@c00 { |
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#clock-cells = <0>; |
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compatible = "ti,wait-gate-clock"; |
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clocks = <&sys_ck>; |
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reg = <0x0c00>; |
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ti,bit-shift = <7>; |
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}; |
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sr_l4_ick: sr_l4_ick { |
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#clock-cells = <0>; |
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compatible = "fixed-factor-clock"; |
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clocks = <&l4_ick>; |
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clock-mult = <1>; |
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clock-div = <1>; |
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}; |
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|
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dpll2_fck: dpll2_fck@40 { |
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#clock-cells = <0>; |
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compatible = "ti,divider-clock"; |
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clocks = <&core_ck>; |
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ti,bit-shift = <19>; |
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ti,max-div = <7>; |
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reg = <0x0040>; |
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ti,index-starts-at-one; |
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}; |
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|
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dpll2_ck: dpll2_ck@4 { |
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#clock-cells = <0>; |
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compatible = "ti,omap3-dpll-clock"; |
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clocks = <&sys_ck>, <&dpll2_fck>; |
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reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>; |
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ti,low-power-stop; |
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ti,lock; |
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ti,low-power-bypass; |
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}; |
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dpll2_m2_ck: dpll2_m2_ck@44 { |
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#clock-cells = <0>; |
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compatible = "ti,divider-clock"; |
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clocks = <&dpll2_ck>; |
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ti,max-div = <31>; |
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reg = <0x0044>; |
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ti,index-starts-at-one; |
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}; |
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iva2_ck: iva2_ck@0 { |
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#clock-cells = <0>; |
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compatible = "ti,wait-gate-clock"; |
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clocks = <&dpll2_m2_ck>; |
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reg = <0x0000>; |
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ti,bit-shift = <0>; |
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}; |
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modem_fck: modem_fck@a00 { |
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#clock-cells = <0>; |
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compatible = "ti,omap3-interface-clock"; |
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clocks = <&sys_ck>; |
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reg = <0x0a00>; |
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ti,bit-shift = <31>; |
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}; |
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sad2d_ick: sad2d_ick@a10 { |
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#clock-cells = <0>; |
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compatible = "ti,omap3-interface-clock"; |
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clocks = <&l3_ick>; |
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reg = <0x0a10>; |
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ti,bit-shift = <3>; |
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}; |
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mad2d_ick: mad2d_ick@a18 { |
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#clock-cells = <0>; |
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compatible = "ti,omap3-interface-clock"; |
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clocks = <&l3_ick>; |
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reg = <0x0a18>; |
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ti,bit-shift = <3>; |
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}; |
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mspro_fck: mspro_fck@a00 { |
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#clock-cells = <0>; |
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compatible = "ti,wait-gate-clock"; |
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clocks = <&core_96m_fck>; |
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reg = <0x0a00>; |
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ti,bit-shift = <23>; |
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}; |
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}; |
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|
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&cm_clockdomains { |
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cam_clkdm: cam_clkdm { |
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compatible = "ti,clockdomain"; |
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clocks = <&cam_ick>, <&csi2_96m_fck>; |
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}; |
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iva2_clkdm: iva2_clkdm { |
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compatible = "ti,clockdomain"; |
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clocks = <&iva2_ck>; |
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}; |
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dpll2_clkdm: dpll2_clkdm { |
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compatible = "ti,clockdomain"; |
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clocks = <&dpll2_ck>; |
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}; |
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wkup_clkdm: wkup_clkdm { |
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compatible = "ti,clockdomain"; |
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clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, |
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<&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, |
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<&gpt1_ick>, <&sr1_fck>, <&sr2_fck>; |
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}; |
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d2d_clkdm: d2d_clkdm { |
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compatible = "ti,clockdomain"; |
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clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>; |
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}; |
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core_l4_clkdm: core_l4_clkdm { |
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compatible = "ti,clockdomain"; |
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clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, |
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<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, |
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<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, |
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<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, |
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<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, |
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<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, |
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<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, |
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<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, |
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<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>, |
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<&des2_ick>, <&mspro_ick>, <&mailboxes_ick>, |
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<&mspro_fck>; |
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}; |
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}; |
@ -0,0 +1,242 @@ |
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/* |
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* Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data |
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* |
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* Copyright (C) 2013 Texas Instruments, Inc. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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*/ |
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&prm_clocks { |
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corex2_d3_fck: corex2_d3_fck { |
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#clock-cells = <0>; |
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compatible = "fixed-factor-clock"; |
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clocks = <&corex2_fck>; |
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clock-mult = <1>; |
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clock-div = <3>; |
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}; |
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corex2_d5_fck: corex2_d5_fck { |
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#clock-cells = <0>; |
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compatible = "fixed-factor-clock"; |
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clocks = <&corex2_fck>; |
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clock-mult = <1>; |
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clock-div = <5>; |
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}; |
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}; |
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&cm_clocks { |
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dpll5_ck: dpll5_ck@d04 { |
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#clock-cells = <0>; |
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compatible = "ti,omap3-dpll-clock"; |
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clocks = <&sys_ck>, <&sys_ck>; |
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reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>; |
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ti,low-power-stop; |
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ti,lock; |
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}; |
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dpll5_m2_ck: dpll5_m2_ck@d50 { |
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#clock-cells = <0>; |
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compatible = "ti,divider-clock"; |
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clocks = <&dpll5_ck>; |
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ti,max-div = <31>; |
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reg = <0x0d50>; |
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ti,index-starts-at-one; |
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}; |
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sgx_gate_fck: sgx_gate_fck@b00 { |
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#clock-cells = <0>; |
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compatible = "ti,composite-gate-clock"; |
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clocks = <&core_ck>; |
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ti,bit-shift = <1>; |
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reg = <0x0b00>; |
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}; |
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core_d3_ck: core_d3_ck { |
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#clock-cells = <0>; |
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compatible = "fixed-factor-clock"; |
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clocks = <&core_ck>; |
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clock-mult = <1>; |
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clock-div = <3>; |
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}; |
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core_d4_ck: core_d4_ck { |
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#clock-cells = <0>; |
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compatible = "fixed-factor-clock"; |
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clocks = <&core_ck>; |
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clock-mult = <1>; |
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clock-div = <4>; |
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}; |
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core_d6_ck: core_d6_ck { |
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#clock-cells = <0>; |
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compatible = "fixed-factor-clock"; |
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clocks = <&core_ck>; |
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clock-mult = <1>; |
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clock-div = <6>; |
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}; |
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omap_192m_alwon_fck: omap_192m_alwon_fck { |
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#clock-cells = <0>; |
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compatible = "fixed-factor-clock"; |
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clocks = <&dpll4_m2x2_ck>; |
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clock-mult = <1>; |
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clock-div = <1>; |
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}; |
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core_d2_ck: core_d2_ck { |
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#clock-cells = <0>; |
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compatible = "fixed-factor-clock"; |
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clocks = <&core_ck>; |
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clock-mult = <1>; |
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clock-div = <2>; |
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}; |
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sgx_mux_fck: sgx_mux_fck@b40 { |
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#clock-cells = <0>; |
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compatible = "ti,composite-mux-clock"; |
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clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>; |
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reg = <0x0b40>; |
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}; |
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sgx_fck: sgx_fck { |
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#clock-cells = <0>; |
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compatible = "ti,composite-clock"; |
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clocks = <&sgx_gate_fck>, <&sgx_mux_fck>; |
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}; |
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sgx_ick: sgx_ick@b10 { |
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#clock-cells = <0>; |
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compatible = "ti,wait-gate-clock"; |
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clocks = <&l3_ick>; |
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reg = <0x0b10>; |
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ti,bit-shift = <0>; |
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}; |
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cpefuse_fck: cpefuse_fck@a08 { |
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#clock-cells = <0>; |
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compatible = "ti,gate-clock"; |
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clocks = <&sys_ck>; |
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reg = <0x0a08>; |
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ti,bit-shift = <0>; |
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}; |
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ts_fck: ts_fck@a08 { |
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#clock-cells = <0>; |
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compatible = "ti,gate-clock"; |
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clocks = <&omap_32k_fck>; |
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reg = <0x0a08>; |
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ti,bit-shift = <1>; |
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}; |
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usbtll_fck: usbtll_fck@a08 { |
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#clock-cells = <0>; |
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compatible = "ti,wait-gate-clock"; |
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clocks = <&dpll5_m2_ck>; |
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reg = <0x0a08>; |
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ti,bit-shift = <2>; |
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}; |
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usbtll_ick: usbtll_ick@a18 { |
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#clock-cells = <0>; |
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compatible = "ti,omap3-interface-clock"; |
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clocks = <&core_l4_ick>; |
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reg = <0x0a18>; |
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ti,bit-shift = <2>; |
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}; |
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mmchs3_ick: mmchs3_ick@a10 { |
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#clock-cells = <0>; |
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compatible = "ti,omap3-interface-clock"; |
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clocks = <&core_l4_ick>; |
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reg = <0x0a10>; |
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ti,bit-shift = <30>; |
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}; |
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mmchs3_fck: mmchs3_fck@a00 { |
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#clock-cells = <0>; |
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compatible = "ti,wait-gate-clock"; |
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clocks = <&core_96m_fck>; |
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reg = <0x0a00>; |
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ti,bit-shift = <30>; |
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}; |
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dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 { |
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#clock-cells = <0>; |
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compatible = "ti,dss-gate-clock"; |
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clocks = <&dpll4_m4x2_ck>; |
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ti,bit-shift = <0>; |
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reg = <0x0e00>; |
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ti,set-rate-parent; |
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}; |
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dss_ick: dss_ick_3430es2@e10 { |
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#clock-cells = <0>; |
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compatible = "ti,omap3-dss-interface-clock"; |
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clocks = <&l4_ick>; |
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reg = <0x0e10>; |
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ti,bit-shift = <0>; |
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}; |
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usbhost_120m_fck: usbhost_120m_fck@1400 { |
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#clock-cells = <0>; |
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compatible = "ti,gate-clock"; |
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clocks = <&dpll5_m2_ck>; |
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reg = <0x1400>; |
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ti,bit-shift = <1>; |
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}; |
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usbhost_48m_fck: usbhost_48m_fck@1400 { |
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#clock-cells = <0>; |
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compatible = "ti,dss-gate-clock"; |
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clocks = <&omap_48m_fck>; |
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reg = <0x1400>; |
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ti,bit-shift = <0>; |
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}; |
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usbhost_ick: usbhost_ick@1410 { |
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#clock-cells = <0>; |
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compatible = "ti,omap3-dss-interface-clock"; |
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clocks = <&l4_ick>; |
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reg = <0x1410>; |
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ti,bit-shift = <0>; |
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}; |
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}; |
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&cm_clockdomains { |
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dpll5_clkdm: dpll5_clkdm { |
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compatible = "ti,clockdomain"; |
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clocks = <&dpll5_ck>; |
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}; |
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sgx_clkdm: sgx_clkdm { |
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compatible = "ti,clockdomain"; |
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clocks = <&sgx_ick>; |
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}; |
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dss_clkdm: dss_clkdm { |
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compatible = "ti,clockdomain"; |
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clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>, |
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<&dss1_alwon_fck>, <&dss_ick>; |
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}; |
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core_l4_clkdm: core_l4_clkdm { |
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compatible = "ti,clockdomain"; |
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clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, |
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<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, |
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<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, |
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<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, |
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<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, |
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<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, |
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<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, |
||||
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, |
||||
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, |
||||
<&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, |
||||
<&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>; |
||||
}; |
||||
|
||||
usbhost_clkdm: usbhost_clkdm { |
||||
compatible = "ti,clockdomain"; |
||||
clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>, |
||||
<&usbhost_ick>; |
||||
}; |
||||
}; |
@ -0,0 +1,110 @@ |
||||
/* |
||||
* Device Tree Source for OMAP36xx clock data |
||||
* |
||||
* Copyright (C) 2013 Texas Instruments, Inc. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
&cm_clocks { |
||||
dpll4_ck: dpll4_ck@d00 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,omap3-dpll-per-j-type-clock"; |
||||
clocks = <&sys_ck>, <&sys_ck>; |
||||
reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>; |
||||
}; |
||||
|
||||
dpll4_m5x2_ck: dpll4_m5x2_ck@d00 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,hsdiv-gate-clock"; |
||||
clocks = <&dpll4_m5x2_mul_ck>; |
||||
ti,bit-shift = <0x1e>; |
||||
reg = <0x0d00>; |
||||
ti,set-rate-parent; |
||||
ti,set-bit-to-disable; |
||||
}; |
||||
|
||||
dpll4_m2x2_ck: dpll4_m2x2_ck@d00 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,hsdiv-gate-clock"; |
||||
clocks = <&dpll4_m2x2_mul_ck>; |
||||
ti,bit-shift = <0x1b>; |
||||
reg = <0x0d00>; |
||||
ti,set-bit-to-disable; |
||||
}; |
||||
|
||||
dpll3_m3x2_ck: dpll3_m3x2_ck@d00 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,hsdiv-gate-clock"; |
||||
clocks = <&dpll3_m3x2_mul_ck>; |
||||
ti,bit-shift = <0xc>; |
||||
reg = <0x0d00>; |
||||
ti,set-bit-to-disable; |
||||
}; |
||||
|
||||
dpll4_m3x2_ck: dpll4_m3x2_ck@d00 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,hsdiv-gate-clock"; |
||||
clocks = <&dpll4_m3x2_mul_ck>; |
||||
ti,bit-shift = <0x1c>; |
||||
reg = <0x0d00>; |
||||
ti,set-bit-to-disable; |
||||
}; |
||||
|
||||
dpll4_m6x2_ck: dpll4_m6x2_ck@d00 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,hsdiv-gate-clock"; |
||||
clocks = <&dpll4_m6x2_mul_ck>; |
||||
ti,bit-shift = <0x1f>; |
||||
reg = <0x0d00>; |
||||
ti,set-bit-to-disable; |
||||
}; |
||||
|
||||
uart4_fck: uart4_fck@1000 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,wait-gate-clock"; |
||||
clocks = <&per_48m_fck>; |
||||
reg = <0x1000>; |
||||
ti,bit-shift = <18>; |
||||
}; |
||||
}; |
||||
|
||||
&dpll4_m2x2_mul_ck { |
||||
clock-mult = <1>; |
||||
}; |
||||
|
||||
&dpll4_m3x2_mul_ck { |
||||
clock-mult = <1>; |
||||
}; |
||||
|
||||
&dpll4_m4x2_mul_ck { |
||||
ti,clock-mult = <1>; |
||||
}; |
||||
|
||||
&dpll4_m5x2_mul_ck { |
||||
ti,clock-mult = <1>; |
||||
}; |
||||
|
||||
&dpll4_m6x2_mul_ck { |
||||
clock-mult = <1>; |
||||
}; |
||||
|
||||
&cm_clockdomains { |
||||
dpll4_clkdm: dpll4_clkdm { |
||||
compatible = "ti,clockdomain"; |
||||
clocks = <&dpll4_ck>; |
||||
}; |
||||
|
||||
per_clkdm: per_clkdm { |
||||
compatible = "ti,clockdomain"; |
||||
clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>, |
||||
<&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>, |
||||
<&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>, |
||||
<&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>, |
||||
<&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>, |
||||
<&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>, |
||||
<&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, |
||||
<&mcbsp4_ick>, <&uart4_fck>; |
||||
}; |
||||
}; |
@ -0,0 +1,198 @@ |
||||
/* |
||||
* Device Tree Source for OMAP34xx/OMAP36xx clock data |
||||
* |
||||
* Copyright (C) 2013 Texas Instruments, Inc. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
&cm_clocks { |
||||
ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,composite-no-wait-gate-clock"; |
||||
clocks = <&corex2_fck>; |
||||
ti,bit-shift = <0>; |
||||
reg = <0x0a00>; |
||||
}; |
||||
|
||||
ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,composite-divider-clock"; |
||||
clocks = <&corex2_fck>; |
||||
ti,bit-shift = <8>; |
||||
reg = <0x0a40>; |
||||
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; |
||||
}; |
||||
|
||||
ssi_ssr_fck: ssi_ssr_fck_3430es2 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,composite-clock"; |
||||
clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>; |
||||
}; |
||||
|
||||
ssi_sst_fck: ssi_sst_fck_3430es2 { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&ssi_ssr_fck>; |
||||
clock-mult = <1>; |
||||
clock-div = <2>; |
||||
}; |
||||
|
||||
hsotgusb_ick_3430es2: hsotgusb_ick_3430es2@a10 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,omap3-hsotgusb-interface-clock"; |
||||
clocks = <&core_l3_ick>; |
||||
reg = <0x0a10>; |
||||
ti,bit-shift = <4>; |
||||
}; |
||||
|
||||
ssi_l4_ick: ssi_l4_ick { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&l4_ick>; |
||||
clock-mult = <1>; |
||||
clock-div = <1>; |
||||
}; |
||||
|
||||
ssi_ick: ssi_ick_3430es2@a10 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,omap3-ssi-interface-clock"; |
||||
clocks = <&ssi_l4_ick>; |
||||
reg = <0x0a10>; |
||||
ti,bit-shift = <0>; |
||||
}; |
||||
|
||||
usim_gate_fck: usim_gate_fck@c00 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,composite-gate-clock"; |
||||
clocks = <&omap_96m_fck>; |
||||
ti,bit-shift = <9>; |
||||
reg = <0x0c00>; |
||||
}; |
||||
|
||||
sys_d2_ck: sys_d2_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&sys_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <2>; |
||||
}; |
||||
|
||||
omap_96m_d2_fck: omap_96m_d2_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&omap_96m_fck>; |
||||
clock-mult = <1>; |
||||
clock-div = <2>; |
||||
}; |
||||
|
||||
omap_96m_d4_fck: omap_96m_d4_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&omap_96m_fck>; |
||||
clock-mult = <1>; |
||||
clock-div = <4>; |
||||
}; |
||||
|
||||
omap_96m_d8_fck: omap_96m_d8_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&omap_96m_fck>; |
||||
clock-mult = <1>; |
||||
clock-div = <8>; |
||||
}; |
||||
|
||||
omap_96m_d10_fck: omap_96m_d10_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&omap_96m_fck>; |
||||
clock-mult = <1>; |
||||
clock-div = <10>; |
||||
}; |
||||
|
||||
dpll5_m2_d4_ck: dpll5_m2_d4_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&dpll5_m2_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <4>; |
||||
}; |
||||
|
||||
dpll5_m2_d8_ck: dpll5_m2_d8_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&dpll5_m2_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <8>; |
||||
}; |
||||
|
||||
dpll5_m2_d16_ck: dpll5_m2_d16_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&dpll5_m2_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <16>; |
||||
}; |
||||
|
||||
dpll5_m2_d20_ck: dpll5_m2_d20_ck { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-factor-clock"; |
||||
clocks = <&dpll5_m2_ck>; |
||||
clock-mult = <1>; |
||||
clock-div = <20>; |
||||
}; |
||||
|
||||
usim_mux_fck: usim_mux_fck@c40 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,composite-mux-clock"; |
||||
clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>; |
||||
ti,bit-shift = <3>; |
||||
reg = <0x0c40>; |
||||
ti,index-starts-at-one; |
||||
}; |
||||
|
||||
usim_fck: usim_fck { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,composite-clock"; |
||||
clocks = <&usim_gate_fck>, <&usim_mux_fck>; |
||||
}; |
||||
|
||||
usim_ick: usim_ick@c10 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,omap3-interface-clock"; |
||||
clocks = <&wkup_l4_ick>; |
||||
reg = <0x0c10>; |
||||
ti,bit-shift = <9>; |
||||
}; |
||||
}; |
||||
|
||||
&cm_clockdomains { |
||||
core_l3_clkdm: core_l3_clkdm { |
||||
compatible = "ti,clockdomain"; |
||||
clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>; |
||||
}; |
||||
|
||||
wkup_clkdm: wkup_clkdm { |
||||
compatible = "ti,clockdomain"; |
||||
clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, |
||||
<&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, |
||||
<&gpt1_ick>, <&usim_ick>; |
||||
}; |
||||
|
||||
core_l4_clkdm: core_l4_clkdm { |
||||
compatible = "ti,clockdomain"; |
||||
clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, |
||||
<&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>, |
||||
<&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, |
||||
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, |
||||
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, |
||||
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, |
||||
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, |
||||
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, |
||||
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, |
||||
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, |
||||
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, |
||||
<&ssi_ick>; |
||||
}; |
||||
}; |
@ -0,0 +1,118 @@ |
||||
/* |
||||
* Device Tree Source for OMAP3 SoC |
||||
* |
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ |
||||
* |
||||
* This file is licensed under the terms of the GNU General Public License |
||||
* version 2. This program is licensed "as is" without any warranty of any |
||||
* kind, whether express or implied. |
||||
*/ |
||||
|
||||
#include <dt-bindings/media/omap3-isp.h> |
||||
|
||||
#include "omap3.dtsi" |
||||
|
||||
/ { |
||||
aliases { |
||||
serial3 = &uart4; |
||||
}; |
||||
|
||||
cpus { |
||||
/* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */ |
||||
cpu@0 { |
||||
operating-points = < |
||||
/* kHz uV */ |
||||
300000 1012500 |
||||
600000 1200000 |
||||
800000 1325000 |
||||
>; |
||||
clock-latency = <300000>; /* From legacy driver */ |
||||
}; |
||||
}; |
||||
|
||||
ocp@68000000 { |
||||
uart4: serial@49042000 { |
||||
compatible = "ti,omap3-uart"; |
||||
reg = <0x49042000 0x400>; |
||||
interrupts = <80>; |
||||
dmas = <&sdma 81 &sdma 82>; |
||||
dma-names = "tx", "rx"; |
||||
ti,hwmods = "uart4"; |
||||
clock-frequency = <48000000>; |
||||
}; |
||||
|
||||
abb_mpu_iva: regulator-abb-mpu { |
||||
compatible = "ti,abb-v1"; |
||||
regulator-name = "abb_mpu_iva"; |
||||
#address-cells = <0>; |
||||
#size-cells = <0>; |
||||
reg = <0x483072f0 0x8>, <0x48306818 0x4>; |
||||
reg-names = "base-address", "int-address"; |
||||
ti,tranxdone-status-mask = <0x4000000>; |
||||
clocks = <&sys_ck>; |
||||
ti,settling-time = <30>; |
||||
ti,clock-cycles = <8>; |
||||
ti,abb_info = < |
||||
/*uV ABB efuse rbb_m fbb_m vset_m*/ |
||||
1012500 0 0 0 0 0 |
||||
1200000 0 0 0 0 0 |
||||
1325000 0 0 0 0 0 |
||||
1375000 1 0 0 0 0 |
||||
>; |
||||
}; |
||||
|
||||
omap3_pmx_core2: pinmux@480025a0 { |
||||
compatible = "ti,omap3-padconf", "pinctrl-single"; |
||||
reg = <0x480025a0 0x5c>; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
#interrupt-cells = <1>; |
||||
interrupt-controller; |
||||
pinctrl-single,register-width = <16>; |
||||
pinctrl-single,function-mask = <0xff1f>; |
||||
}; |
||||
|
||||
isp: isp@480bc000 { |
||||
compatible = "ti,omap3-isp"; |
||||
reg = <0x480bc000 0x12fc |
||||
0x480bd800 0x0600>; |
||||
interrupts = <24>; |
||||
iommus = <&mmu_isp>; |
||||
syscon = <&scm_conf 0x2f0>; |
||||
ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>; |
||||
#clock-cells = <1>; |
||||
ports { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
}; |
||||
}; |
||||
|
||||
bandgap@48002524 { |
||||
reg = <0x48002524 0x4>; |
||||
compatible = "ti,omap36xx-bandgap"; |
||||
#thermal-sensor-cells = <0>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
/* OMAP3630 needs dss_96m_fck for VENC */ |
||||
&venc { |
||||
clocks = <&dss_tv_fck>, <&dss_96m_fck>; |
||||
clock-names = "fck", "tv_dac_clk"; |
||||
}; |
||||
|
||||
&ssi { |
||||
status = "ok"; |
||||
|
||||
clocks = <&ssi_ssr_fck>, |
||||
<&ssi_sst_fck>, |
||||
<&ssi_ick>; |
||||
clock-names = "ssi_ssr_fck", |
||||
"ssi_sst_fck", |
||||
"ssi_ick"; |
||||
}; |
||||
|
||||
/include/ "omap34xx-omap36xx-clocks.dtsi" |
||||
/include/ "omap36xx-omap3430es2plus-clocks.dtsi" |
||||
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" |
||||
/include/ "omap36xx-clocks.dtsi" |
@ -0,0 +1,22 @@ |
||||
/*
|
||||
* include/dt-bindings/media/omap3-isp.h |
||||
* |
||||
* Copyright (C) 2015 Sakari Ailus |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License |
||||
* version 2 as published by the Free Software Foundation. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, but |
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
||||
* General Public License for more details. |
||||
*/ |
||||
|
||||
#ifndef __DT_BINDINGS_OMAP3_ISP_H__ |
||||
#define __DT_BINDINGS_OMAP3_ISP_H__ |
||||
|
||||
#define OMAP3ISP_PHY_TYPE_COMPLEX_IO 0 |
||||
#define OMAP3ISP_PHY_TYPE_CSIPHY 1 |
||||
|
||||
#endif /* __DT_BINDINGS_OMAP3_ISP_H__ */ |
Loading…
Reference in new issue