commit
cad0499071
@ -0,0 +1,131 @@ |
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/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc. |
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* Michal Simek <michal.simek@xilinx.com> |
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* (This file derived from arch/arm/cpu/armv8/zynqmp/cpu.c) |
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* |
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* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/system.h> |
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#include <asm/armv8/mmu.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define SECTION_SHIFT_L1 30UL |
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#define SECTION_SHIFT_L2 21UL |
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#define BLOCK_SIZE_L0 0x8000000000UL |
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#define BLOCK_SIZE_L1 (1 << SECTION_SHIFT_L1) |
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#define BLOCK_SIZE_L2 (1 << SECTION_SHIFT_L2) |
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#define TCR_TG1_4K (1 << 31) |
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#define TCR_EPD1_DISABLE (1 << 23) |
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#define TEGRA_VA_BITS 40 |
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#define TEGRA_TCR TCR_TG1_4K | \ |
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TCR_EPD1_DISABLE | \
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TCR_SHARED_OUTER | \
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TCR_SHARED_INNER | \
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TCR_IRGN_WBWA | \
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TCR_ORGN_WBWA | \
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TCR_T0SZ(TEGRA_VA_BITS) |
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#define MEMORY_ATTR PMD_SECT_AF | PMD_SECT_INNER_SHARE | \ |
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PMD_ATTRINDX(MT_NORMAL) | \
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PMD_TYPE_SECT |
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#define DEVICE_ATTR PMD_SECT_AF | PMD_SECT_PXN | \ |
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PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_NGNRNE) | \
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PMD_TYPE_SECT |
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/* 4K size is required to place 512 entries in each level */ |
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#define TLB_TABLE_SIZE 0x1000 |
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/*
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* This mmu table looks as below |
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* Level 0 table contains two entries to 512GB sizes. One is Level1 Table 0 |
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* and other Level1 Table1. |
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* Level1 Table0 contains entries for each 1GB from 0 to 511GB. |
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* Level1 Table1 contains entries for each 1GB from 512GB to 1TB. |
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* Level2 Table0, Level2 Table1, Level2 Table2 and Level2 Table3 contains |
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* entries for each 2MB starting from 0GB, 1GB, 2GB and 3GB respectively. |
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*/ |
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void mmu_setup(void) |
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{ |
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int el; |
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u64 i, section_l1t0, section_l1t1; |
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u64 section_l2t0, section_l2t1, section_l2t2, section_l2t3; |
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u64 *level0_table = (u64 *)gd->arch.tlb_addr; |
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u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + TLB_TABLE_SIZE); |
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u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + (2 * TLB_TABLE_SIZE)); |
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u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE)); |
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u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + (4 * TLB_TABLE_SIZE)); |
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u64 *level2_table_2 = (u64 *)(gd->arch.tlb_addr + (5 * TLB_TABLE_SIZE)); |
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u64 *level2_table_3 = (u64 *)(gd->arch.tlb_addr + (6 * TLB_TABLE_SIZE)); |
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/* Invalidate all table entries */ |
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memset(level0_table, 0, PGTABLE_SIZE); |
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level0_table[0] = |
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(u64)level1_table_0 | PMD_TYPE_TABLE; |
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level0_table[1] = |
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(u64)level1_table_1 | PMD_TYPE_TABLE; |
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/*
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* set level 1 table 0, covering 0 to 512GB |
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* set level 1 table 1, covering 512GB to 1TB |
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*/ |
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section_l1t0 = 0; |
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section_l1t1 = BLOCK_SIZE_L0; |
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for (i = 0; i < 512; i++) { |
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level1_table_0[i] = section_l1t0; |
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if (i >= 4) |
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level1_table_0[i] |= MEMORY_ATTR; |
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level1_table_1[i] = section_l1t1; |
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level1_table_1[i] |= MEMORY_ATTR; |
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section_l1t0 += BLOCK_SIZE_L1; |
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section_l1t1 += BLOCK_SIZE_L1; |
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} |
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level1_table_0[0] = |
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(u64)level2_table_0 | PMD_TYPE_TABLE; |
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level1_table_0[1] = |
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(u64)level2_table_1 | PMD_TYPE_TABLE; |
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level1_table_0[2] = |
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(u64)level2_table_2 | PMD_TYPE_TABLE; |
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level1_table_0[3] = |
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(u64)level2_table_3 | PMD_TYPE_TABLE; |
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section_l2t0 = 0; |
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section_l2t1 = section_l2t0 + BLOCK_SIZE_L1; /* 1GB */ |
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section_l2t2 = section_l2t1 + BLOCK_SIZE_L1; /* 2GB */ |
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section_l2t3 = section_l2t2 + BLOCK_SIZE_L1; /* 3GB */ |
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for (i = 0; i < 512; i++) { |
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level2_table_0[i] = section_l2t0 | DEVICE_ATTR; |
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level2_table_1[i] = section_l2t1 | DEVICE_ATTR; |
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level2_table_2[i] = section_l2t2 | MEMORY_ATTR; |
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level2_table_3[i] = section_l2t3 | MEMORY_ATTR; |
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section_l2t0 += BLOCK_SIZE_L2; |
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section_l2t1 += BLOCK_SIZE_L2; |
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section_l2t2 += BLOCK_SIZE_L2; |
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section_l2t3 += BLOCK_SIZE_L2; |
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} |
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/* flush new MMU table */ |
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flush_dcache_range(gd->arch.tlb_addr, |
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gd->arch.tlb_addr + gd->arch.tlb_size); |
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/* point TTBR to the new table */ |
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el = current_el(); |
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set_ttbr_tcr_mair(el, gd->arch.tlb_addr, |
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TEGRA_TCR, MEMORY_ATTRIBUTES); |
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set_sctlr(get_sctlr() | CR_M); |
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} |
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u64 *arch_get_page_table(void) |
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{ |
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return (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE)); |
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} |
@ -0,0 +1,69 @@ |
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/*
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* Thumb-1 drop-in for the linux/include/asm-arm/proc-armv/system.h |
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* |
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* (C) Copyright 2015 |
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* Albert ARIBAUD <albert.u.boot@aribaud.net> |
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* |
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* The original file does not build in Thumb mode. However, in U-Boot |
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* we don't use interrupt context, so we can redefine these as empty |
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* memory barriers, which makes Thumb-1 compiler happy. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/*
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* Use the same macro name as linux/include/asm-arm/proc-armv/system.h |
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* here, so that if the original ever gets included after us, it won't |
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* try to re-redefine anything. |
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*/ |
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#ifndef __ASM_PROC_SYSTEM_H |
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#define __ASM_PROC_SYSTEM_H |
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/*
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* Redefine all original macros with static inline functions containing |
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* a simple memory barrier, so that they produce the same instruction |
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* ordering constraints as their original counterparts. |
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* We use static inline functions rather than macros so that we can tell |
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* the compiler to not complain about unused arguments. |
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*/ |
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static inline void local_irq_save( |
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unsigned long flags __attribute__((unused))) |
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{ |
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__asm__ __volatile__ ("" : : : "memory"); |
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} |
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static inline void local_irq_enable(void) |
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{ |
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__asm__ __volatile__ ("" : : : "memory"); |
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} |
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static inline void local_irq_disable(void) |
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{ |
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__asm__ __volatile__ ("" : : : "memory"); |
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} |
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static inline void __stf(void) |
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{ |
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__asm__ __volatile__ ("" : : : "memory"); |
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} |
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static inline void __clf(void) |
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{ |
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__asm__ __volatile__ ("" : : : "memory"); |
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} |
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static inline void local_save_flags( |
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unsigned long flags __attribute__((unused))) |
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{ |
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__asm__ __volatile__ ("" : : : "memory"); |
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} |
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static inline void local_irq_restore( |
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unsigned long flags __attribute__((unused))) |
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{ |
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__asm__ __volatile__ ("" : : : "memory"); |
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} |
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#endif /* __ASM_PROC_SYSTEM_H */ |
@ -0,0 +1,12 @@ |
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if TARGET_OPENRD |
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config SYS_BOARD |
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default "openrd" |
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config SYS_VENDOR |
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default "Marvell" |
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config SYS_CONFIG_NAME |
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default "openrd" |
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endif |
@ -0,0 +1,12 @@ |
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OPENRD BOARD |
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M: Albert ARIBAUD <albert-u-boot@aribaud.net> |
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S: Maintained |
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F: board/Marvell/openrd/ |
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F: include/configs/openrd.h |
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F: configs/openrd_base_defconfig |
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OPENRD_CLIENT BOARD |
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M: Albert ARIBAUD <albert-u-boot@aribaud.net> |
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S: Maintained |
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F: configs/openrd_client_defconfig |
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F: configs/openrd_ultimate_defconfig |
@ -0,0 +1,14 @@ |
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#
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# (C) Copyright 2009
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# Net Insight <www.netinsight.net>
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# Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
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#
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# Based on sheevaplug:
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# (C) Copyright 2009
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := openrd.o
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@ -0,0 +1,152 @@ |
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# |
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# (C) Copyright 2009 |
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# Marvell Semiconductor <www.marvell.com> |
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
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# |
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# SPDX-License-Identifier: GPL-2.0+ |
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# |
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# Refer doc/README.kwbimage for more details about how-to configure |
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# and create kirkwood boot image |
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# |
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# Boot Media configurations |
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BOOT_FROM nand |
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NAND_ECC_MODE default |
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NAND_PAGE_SIZE 0x0800 |
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# SOC registers configuration using bootrom header extension |
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# Maximum KWBIMAGE_MAX_CONFIG configurations allowed |
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# Configure RGMII-0 interface pad voltage to 1.8V |
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DATA 0xFFD100e0 0x1b1b1b9b |
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#Dram initalization for SINGLE x16 CL=5 @ 400MHz |
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DATA 0xFFD01400 0x43000c30 # DDR Configuration register |
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# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) |
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# bit23-14: zero |
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# bit24: 1= enable exit self refresh mode on DDR access |
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# bit25: 1 required |
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# bit29-26: zero |
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# bit31-30: 01 |
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DATA 0xFFD01404 0x37543000 # DDR Controller Control Low |
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# bit 4: 0=addr/cmd in smame cycle |
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# bit 5: 0=clk is driven during self refresh, we don't care for APX |
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# bit 6: 0=use recommended falling edge of clk for addr/cmd |
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# bit14: 0=input buffer always powered up |
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# bit18: 1=cpu lock transaction enabled |
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# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 |
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# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM |
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# bit30-28: 3 required |
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# bit31: 0=no additional STARTBURST delay |
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DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) |
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# bit3-0: TRAS lsbs |
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# bit7-4: TRCD |
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# bit11- 8: TRP |
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# bit15-12: TWR |
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# bit19-16: TWTR |
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# bit20: TRAS msb |
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# bit23-21: 0x0 |
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# bit27-24: TRRD |
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# bit31-28: TRTP |
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DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) |
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# bit6-0: TRFC |
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# bit8-7: TR2R |
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# bit10-9: TR2W |
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# bit12-11: TW2W |
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# bit31-13: zero required |
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DATA 0xFFD01410 0x000000cc # DDR Address Control |
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# bit1-0: 00, Cs0width=x8 |
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# bit3-2: 11, Cs0size=1Gb |
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# bit5-4: 00, Cs1width=x8 |
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# bit7-6: 11, Cs1size=1Gb |
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# bit9-8: 00, Cs2width=nonexistent |
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# bit11-10: 00, Cs2size =nonexistent |
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# bit13-12: 00, Cs3width=nonexistent |
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# bit15-14: 00, Cs3size =nonexistent |
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# bit16: 0, Cs0AddrSel |
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# bit17: 0, Cs1AddrSel |
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# bit18: 0, Cs2AddrSel |
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# bit19: 0, Cs3AddrSel |
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# bit31-20: 0 required |
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DATA 0xFFD01414 0x00000000 # DDR Open Pages Control |
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# bit0: 0, OpenPage enabled |
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# bit31-1: 0 required |
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DATA 0xFFD01418 0x00000000 # DDR Operation |
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# bit3-0: 0x0, DDR cmd |
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# bit31-4: 0 required |
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DATA 0xFFD0141C 0x00000C52 # DDR Mode |
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# bit2-0: 2, BurstLen=2 required |
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# bit3: 0, BurstType=0 required |
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# bit6-4: 4, CL=5 |
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# bit7: 0, TestMode=0 normal |
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# bit8: 0, DLL reset=0 normal |
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# bit11-9: 6, auto-precharge write recovery ???????????? |
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# bit12: 0, PD must be zero |
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# bit31-13: 0 required |
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DATA 0xFFD01420 0x00000042 # DDR Extended Mode |
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# bit0: 0, DDR DLL enabled |
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# bit1: 1, DDR drive strength reduced |
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# bit2: 0, DDR ODT control lsd (disabled) |
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# bit5-3: 000, required |
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# bit6: 1, DDR ODT control msb, (disabled) |
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# bit9-7: 000, required |
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# bit10: 0, differential DQS enabled |
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# bit11: 0, required |
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# bit12: 0, DDR output buffer enabled |
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# bit31-13: 0 required |
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DATA 0xFFD01424 0x0000F17F # DDR Controller Control High |
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# bit2-0: 111, required |
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# bit3 : 1 , MBUS Burst Chop disabled |
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# bit6-4: 111, required |
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# bit7 : 0 |
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# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz |
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# bit9 : 0 , no half clock cycle addition to dataout |
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# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals |
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# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh |
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# bit15-12: 1111 required |
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# bit31-16: 0 required |
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DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) |
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DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) |
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DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 |
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DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size |
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# bit0: 1, Window enabled |
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# bit1: 0, Write Protect disabled |
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# bit3-2: 00, CS0 hit selected |
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# bit23-4: ones, required |
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# bit31-24: 0x0F, Size (i.e. 256MB) |
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DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb |
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DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 |
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DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled |
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DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled |
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|
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DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) |
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# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1 |
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# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0 |
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# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1. |
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# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0. |
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DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) |
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|
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DATA 0xFFD0149C 0x0000E40f # CPU ODT Control |
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# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3 |
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# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm |
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# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm |
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# bit14: 1, M_STARTBURST_IN ODT: Enabled |
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# bit15: 1, DDR IO ODT Unit: Use ODT block |
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DATA 0xFFD01480 0x00000001 # DDR Initialization Control |
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#bit0=1, enable DDR init upon this register write |
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|
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# End of Header extension |
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DATA 0x0 0x0 |
@ -0,0 +1,160 @@ |
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/*
|
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* (C) Copyright 2009 |
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* Net Insight <www.netinsight.net> |
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* Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net> |
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* |
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* Based on sheevaplug.c: |
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* (C) Copyright 2009 |
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* Marvell Semiconductor <www.marvell.com> |
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <miiphy.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/arch/soc.h> |
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#include <asm/arch/mpp.h> |
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#include "openrd.h" |
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|
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DECLARE_GLOBAL_DATA_PTR; |
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|
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int board_early_init_f(void) |
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{ |
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/*
|
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* default gpio configuration |
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* There are maximum 64 gpios controlled through 2 sets of registers |
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* the below configuration configures mainly initial LED status |
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*/ |
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mvebu_config_gpio(OPENRD_OE_VAL_LOW, |
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OPENRD_OE_VAL_HIGH, |
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OPENRD_OE_LOW, OPENRD_OE_HIGH); |
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|
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/* Multi-Purpose Pins Functionality configuration */ |
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static const u32 kwmpp_config[] = { |
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MPP0_NF_IO2, |
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MPP1_NF_IO3, |
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MPP2_NF_IO4, |
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MPP3_NF_IO5, |
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MPP4_NF_IO6, |
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MPP5_NF_IO7, |
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MPP6_SYSRST_OUTn, |
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MPP7_GPO, |
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MPP8_TW_SDA, |
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MPP9_TW_SCK, |
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MPP10_UART0_TXD, |
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MPP11_UART0_RXD, |
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MPP12_SD_CLK, |
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MPP13_SD_CMD, /* Alt UART1_TXD */ |
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MPP14_SD_D0, /* Alt UART1_RXD */ |
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MPP15_SD_D1, |
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MPP16_SD_D2, |
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MPP17_SD_D3, |
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MPP18_NF_IO0, |
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MPP19_NF_IO1, |
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MPP20_GE1_0, |
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MPP21_GE1_1, |
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MPP22_GE1_2, |
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MPP23_GE1_3, |
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MPP24_GE1_4, |
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MPP25_GE1_5, |
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MPP26_GE1_6, |
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MPP27_GE1_7, |
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MPP28_GPIO, |
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MPP29_TSMP9, |
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MPP30_GE1_10, |
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MPP31_GE1_11, |
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MPP32_GE1_12, |
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MPP33_GE1_13, |
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MPP34_GPIO, /* UART1 / SD sel */ |
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MPP35_TDM_CH0_TX_QL, |
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MPP36_TDM_SPI_CS1, |
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MPP37_TDM_CH2_TX_QL, |
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MPP38_TDM_CH2_RX_QL, |
||||
MPP39_AUDIO_I2SBCLK, |
||||
MPP40_AUDIO_I2SDO, |
||||
MPP41_AUDIO_I2SLRC, |
||||
MPP42_AUDIO_I2SMCLK, |
||||
MPP43_AUDIO_I2SDI, |
||||
MPP44_AUDIO_EXTCLK, |
||||
MPP45_TDM_PCLK, |
||||
MPP46_TDM_FS, |
||||
MPP47_TDM_DRX, |
||||
MPP48_TDM_DTX, |
||||
MPP49_TDM_CH0_RX_QL, |
||||
0 |
||||
}; |
||||
|
||||
kirkwood_mpp_conf(kwmpp_config, NULL); |
||||
return 0; |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
/*
|
||||
* arch number of board |
||||
*/ |
||||
#if defined(CONFIG_BOARD_IS_OPENRD_BASE) |
||||
gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE; |
||||
#elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT) |
||||
gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT; |
||||
#elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE) |
||||
gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE; |
||||
#endif |
||||
|
||||
/* adress of boot parameters */ |
||||
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; |
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_RESET_PHY_R |
||||
/* Configure and enable MV88E1116/88E1121 PHY */ |
||||
void mv_phy_init(char *name) |
||||
{ |
||||
u16 reg; |
||||
u16 devadr; |
||||
|
||||
if (miiphy_set_current_dev(name)) |
||||
return; |
||||
|
||||
/* command to read PHY dev address */ |
||||
if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) { |
||||
printf("Err..%s could not read PHY dev address\n", __func__); |
||||
return; |
||||
} |
||||
|
||||
/*
|
||||
* Enable RGMII delay on Tx and Rx for CPU port |
||||
* Ref: sec 4.7.2 of chip datasheet |
||||
*/ |
||||
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); |
||||
miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); |
||||
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); |
||||
miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); |
||||
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); |
||||
|
||||
/* reset the phy */ |
||||
miiphy_reset(name, devadr); |
||||
|
||||
printf(PHY_NO" Initialized on %s\n", name); |
||||
} |
||||
|
||||
void reset_phy(void) |
||||
{ |
||||
mv_phy_init("egiga0"); |
||||
|
||||
#ifdef CONFIG_BOARD_IS_OPENRD_CLIENT |
||||
/* Kirkwood ethernet driver is written with the assumption that in case
|
||||
* of multiple PHYs, their addresses are consecutive. But unfortunately |
||||
* in case of OpenRD-Client, PHY addresses are not consecutive.*/ |
||||
miiphy_write("egiga1", 0xEE, 0xEE, 24); |
||||
#endif |
||||
|
||||
#if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \ |
||||
defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE) |
||||
/* configure and initialize both PHY's */ |
||||
mv_phy_init("egiga1"); |
||||
#endif |
||||
} |
||||
#endif /* CONFIG_RESET_PHY_R */ |
@ -0,0 +1,30 @@ |
||||
/*
|
||||
* (C) Copyright 2009 |
||||
* Net Insight <www.netinsight.net> |
||||
* Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net> |
||||
* |
||||
* Based on sheevaplug.h: |
||||
* (C) Copyright 2009 |
||||
* Marvell Semiconductor <www.marvell.com> |
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __OPENRD_BASE_H |
||||
#define __OPENRD_BASE_H |
||||
|
||||
#define OPENRD_OE_LOW (~(1<<28)) /* RS232 / RS485 */ |
||||
#define OPENRD_OE_HIGH (~(1<<2)) /* SD / UART1 */ |
||||
#define OPENRD_OE_VAL_LOW (0) /* Sel RS232 */ |
||||
#define OPENRD_OE_VAL_HIGH (1 << 2) /* Sel SD */ |
||||
|
||||
/* PHY related */ |
||||
#define MV88E1116_LED_FCTRL_REG 10 |
||||
#define MV88E1116_CPRSP_CR3_REG 21 |
||||
#define MV88E1116_MAC_CTRL_REG 21 |
||||
#define MV88E1116_PGADR_REG 22 |
||||
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) |
||||
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) |
||||
|
||||
#endif /* __OPENRD_BASE_H */ |
@ -0,0 +1,7 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_KIRKWOOD=y |
||||
CONFIG_TARGET_OPENRD=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE" |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_FLASH is not set |
||||
# CONFIG_CMD_SETEXPR is not set |
@ -0,0 +1,7 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_KIRKWOOD=y |
||||
CONFIG_TARGET_OPENRD=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT" |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_FLASH is not set |
||||
# CONFIG_CMD_SETEXPR is not set |
@ -0,0 +1,7 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_KIRKWOOD=y |
||||
CONFIG_TARGET_OPENRD=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE" |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_FLASH is not set |
||||
# CONFIG_CMD_SETEXPR is not set |
@ -0,0 +1,138 @@ |
||||
/*
|
||||
* (C) Copyright 2009 |
||||
* Net Insight <www.netinsight.net> |
||||
* Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net> |
||||
* |
||||
* Based on sheevaplug.h: |
||||
* (C) Copyright 2009 |
||||
* Marvell Semiconductor <www.marvell.com> |
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _CONFIG_OPENRD_H |
||||
#define _CONFIG_OPENRD_H |
||||
|
||||
/*
|
||||
* Version number information |
||||
*/ |
||||
#ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE |
||||
# define CONFIG_IDENT_STRING "\nOpenRD-Ultimate" |
||||
#else |
||||
# ifdef CONFIG_BOARD_IS_OPENRD_CLIENT |
||||
# define CONFIG_IDENT_STRING "\nOpenRD-Client" |
||||
# else |
||||
# ifdef CONFIG_BOARD_IS_OPENRD_BASE |
||||
# define CONFIG_IDENT_STRING "\nOpenRD-Base" |
||||
# else |
||||
# error Unknown OpenRD board specified |
||||
# endif |
||||
# endif |
||||
#endif |
||||
|
||||
/*
|
||||
* High Level Configuration Options (easy to change) |
||||
*/ |
||||
#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ |
||||
#define CONFIG_KW88F6281 1 /* SOC Name */ |
||||
#define CONFIG_MACH_OPENRD_BASE /* Machine type */ |
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ |
||||
#define CONFIG_SYS_THUMB_BUILD |
||||
|
||||
/*
|
||||
* Commands configuration |
||||
*/ |
||||
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ |
||||
#define CONFIG_SYS_MVFS |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_ENV |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_CMD_NAND |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_USB |
||||
#define CONFIG_CMD_IDE |
||||
|
||||
/*
|
||||
* mv-common.h should be defined after CMD configs since it used them |
||||
* to enable certain macros |
||||
*/ |
||||
#include "mv-common.h" |
||||
|
||||
/*
|
||||
* Environment variables configurations |
||||
*/ |
||||
#ifdef CONFIG_CMD_NAND |
||||
#define CONFIG_ENV_IS_IN_NAND 1 |
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ |
||||
#else |
||||
#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ |
||||
#endif |
||||
/*
|
||||
* max 4k env size is enough, but in case of nand |
||||
* it has to be rounded to sector size |
||||
*/ |
||||
#define CONFIG_ENV_SIZE 0x20000 /* 128k */ |
||||
#define CONFIG_ENV_ADDR 0x60000 |
||||
#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ |
||||
/*
|
||||
* Environment is right behind U-Boot in flash. Make sure U-Boot |
||||
* doesn't grow into the environment area. |
||||
*/ |
||||
#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET |
||||
|
||||
/*
|
||||
* Default environment variables |
||||
*/ |
||||
#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ |
||||
"setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
|
||||
"${x_bootcmd_usb}; bootm 0x6400000;" |
||||
|
||||
#define MTDIDS_DEFAULT "nand0=nand_mtd" |
||||
#define MTDPARTS_DEFAULT "mtdparts=nand_mtd:0x100000@0x000000(uboot),"\ |
||||
"0x400000@0x100000(uImage),"\
|
||||
"0x1fb00000@0x500000(rootfs)" |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ |
||||
"=ttyS0,115200 "MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \
|
||||
"x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
|
||||
"x_bootcmd_usb=usb start\0" \
|
||||
"x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" \
|
||||
"mtdids="MTDIDS_DEFAULT"\0" \
|
||||
"mtdparts="MTDPARTS_DEFAULT"\0" |
||||
|
||||
/*
|
||||
* Ethernet Driver configuration |
||||
*/ |
||||
#ifdef CONFIG_CMD_NET |
||||
# ifdef CONFIG_BOARD_IS_OPENRD_BASE |
||||
# define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ |
||||
# else |
||||
# define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ |
||||
# endif |
||||
# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE |
||||
# define CONFIG_PHY_BASE_ADR 0x0 |
||||
# define PHY_NO "88E1121" |
||||
# else |
||||
# define CONFIG_PHY_BASE_ADR 0x8 |
||||
# define PHY_NO "88E1116" |
||||
# endif |
||||
#endif /* CONFIG_CMD_NET */ |
||||
|
||||
/*
|
||||
* SATA Driver configuration |
||||
*/ |
||||
#ifdef CONFIG_MVSATA_IDE |
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET |
||||
#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET |
||||
#endif /*CONFIG_MVSATA_IDE*/ |
||||
|
||||
#ifdef CONFIG_CMD_MMC |
||||
#define CONFIG_MMC |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_MVEBU_MMC |
||||
#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE |
||||
#endif /* CONFIG_CMD_MMC */ |
||||
|
||||
#endif /* _CONFIG_OPENRD_BASE_H */ |
Loading…
Reference in new issue