@ -564,53 +564,6 @@ static iomux_v3_cfg_t const rgb_pads[] = {
MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL ( OUTPUT_RGB ) ,
} ;
static iomux_v3_cfg_t const vga_pads [ ] = {
# ifdef FOR_DL_SOLO
/* DualLite/Solo doesn't have IPU2 */
MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK ,
MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 ,
MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 ,
MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 ,
MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 ,
MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 ,
MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 ,
MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 ,
MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 ,
MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 ,
MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 ,
MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 ,
MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 ,
MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 ,
MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 ,
MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 ,
MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 ,
MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 ,
MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 ,
MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 ,
# else
MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK ,
MX6_PAD_DI0_PIN15__IPU2_DI0_PIN15 ,
MX6_PAD_DI0_PIN2__IPU2_DI0_PIN02 ,
MX6_PAD_DI0_PIN3__IPU2_DI0_PIN03 ,
MX6_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 ,
MX6_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 ,
MX6_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 ,
MX6_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 ,
MX6_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 ,
MX6_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 ,
MX6_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 ,
MX6_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 ,
MX6_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 ,
MX6_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 ,
MX6_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 ,
MX6_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 ,
MX6_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 ,
MX6_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 ,
MX6_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 ,
MX6_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 ,
# endif
} ;
static void do_enable_hdmi ( struct display_info_t const * dev )
{
imx_enable_hdmi_phy ( ) ;