trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>master
commit
cbe7706ab8
@ -0,0 +1,6 @@ |
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config ARCH_LS1021A |
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bool "Freescale Layerscape LS1021A SoC" |
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select SYS_FSL_ERRATUM_A010315 |
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|
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config LS1_DEEP_SLEEP |
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bool "Freescale Layerscape 1 deep sleep" |
@ -0,0 +1,236 @@ |
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/*
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* Copyright 2016 Freescale Semiconductor, Inc. |
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* Author: Hongbo Zhang <hongbo.zhang@nxp.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* This file implements LS102X platform PSCI SYSTEM-SUSPEND function |
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*/ |
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#include <config.h> |
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#include <asm/io.h> |
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#include <asm/psci.h> |
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#include <asm/arch/immap_ls102xa.h> |
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#include <fsl_immap.h> |
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#include "fsl_epu.h" |
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#define __secure __attribute__((section("._secure.text"))) |
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#define CCSR_GICD_CTLR 0x1000 |
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#define CCSR_GICC_CTLR 0x2000 |
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#define DCSR_RCPM_CG1CR0 0x31c |
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#define DCSR_RCPM_CSTTACR0 0xb00 |
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#define DCFG_CRSTSR_WDRFR 0x8 |
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#define DDR_RESV_LEN 128 |
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#ifdef CONFIG_LS1_DEEP_SLEEP |
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/*
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* DDR controller initialization training breaks the first 128 bytes of DDR, |
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* save them so that the bootloader can restore them while resuming. |
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*/ |
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static void __secure ls1_save_ddr_head(void) |
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{ |
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const char *src = (const char *)CONFIG_SYS_SDRAM_BASE; |
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char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN); |
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struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; |
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int i; |
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out_le32(&scfg->sparecr[2], dest); |
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for (i = 0; i < DDR_RESV_LEN; i++) |
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*dest++ = *src++; |
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} |
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static void __secure ls1_fsm_setup(void) |
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{ |
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void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); |
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void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR; |
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out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001); |
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out_be32(dcsr_rcpm_base + DCSR_RCPM_CG1CR0, 0x00000001); |
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fsl_epu_setup((void *)dcsr_epu_base); |
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/* Pull MCKE signal low before enabling deep sleep signal in FPGA */ |
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out_be32(dcsr_epu_base + EPECR0, 0x5); |
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out_be32(dcsr_epu_base + EPSMCR15, 0x76300000); |
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} |
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static void __secure ls1_deepsleep_irq_cfg(void) |
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{ |
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struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; |
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struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR; |
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u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0; |
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/* Mask interrupts from GIC */ |
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out_be32(&rcpm->nfiqoutr, 0x0ffffffff); |
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out_be32(&rcpm->nirqoutr, 0x0ffffffff); |
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/* Mask deep sleep wake-up interrupts while entering deep sleep */ |
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out_be32(&rcpm->dsimskr, 0x0ffffffff); |
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ippdexpcr0 = in_be32(&rcpm->ippdexpcr0); |
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/*
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* Workaround: There is bug of register ippdexpcr1, when read it always |
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* returns zero, so its value is saved to a scrachpad register to be |
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* read, that is why we don't read it from register ippdexpcr1 itself. |
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*/ |
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ippdexpcr1 = in_le32(&scfg->sparecr[7]); |
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if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC) |
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pmcintecr |= SCFG_PMCINTECR_ETSECRXG0 | |
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SCFG_PMCINTECR_ETSECRXG1 | |
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SCFG_PMCINTECR_ETSECERRG0 | |
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SCFG_PMCINTECR_ETSECERRG1; |
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if (ippdexpcr0 & RCPM_IPPDEXPCR0_GPIO) |
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pmcintecr |= SCFG_PMCINTECR_GPIO; |
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if (ippdexpcr1 & RCPM_IPPDEXPCR1_LPUART) |
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pmcintecr |= SCFG_PMCINTECR_LPUART; |
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if (ippdexpcr1 & RCPM_IPPDEXPCR1_FLEXTIMER) |
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pmcintecr |= SCFG_PMCINTECR_FTM; |
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/* Always set external IRQ pins as wakeup source */ |
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pmcintecr |= SCFG_PMCINTECR_IRQ0 | SCFG_PMCINTECR_IRQ1; |
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out_be32(&scfg->pmcintlecr, 0); |
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/* Clear PMC interrupt status */ |
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out_be32(&scfg->pmcintsr, 0xffffffff); |
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/* Enable wakeup interrupt during deep sleep */ |
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out_be32(&scfg->pmcintecr, pmcintecr); |
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} |
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static void __secure ls1_delay(unsigned int loop) |
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{ |
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while (loop--) { |
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int i = 1000; |
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while (i--) |
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; |
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} |
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} |
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static void __secure ls1_start_fsm(void) |
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{ |
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void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); |
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void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR; |
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struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; |
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struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; |
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/* Set HRSTCR */ |
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setbits_be32(&scfg->hrstcr, 0x80000000); |
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/* Place DDR controller in self refresh mode */ |
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setbits_be32(&ddr->sdram_cfg_2, 0x80000000); |
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ls1_delay(2000); |
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/* Set EVT4_B to lock the signal MCKE down */ |
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out_be32(dcsr_epu_base + EPECR0, 0x0); |
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ls1_delay(2000); |
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out_be32(ccsr_gic_base + CCSR_GICD_CTLR, 0x0); |
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out_be32(ccsr_gic_base + CCSR_GICC_CTLR, 0x0); |
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/* Enable all EPU Counters */ |
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setbits_be32(dcsr_epu_base + EPGCR, 0x80000000); |
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/* Enable SCU15 */ |
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setbits_be32(dcsr_epu_base + EPECR15, 0x90000004); |
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/* Enter WFI mode, and EPU FSM will start */ |
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__asm__ __volatile__ ("wfi" : : : "memory"); |
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/* NEVER ENTER HERE */ |
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while (1) |
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; |
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} |
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static void __secure ls1_deep_sleep(u32 entry_point) |
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{ |
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struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; |
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; |
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struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR; |
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#ifdef QIXIS_BASE |
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u32 tmp; |
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void *qixis_base = (void *)QIXIS_BASE; |
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#endif |
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/* Enable cluster to enter the PCL10 state */ |
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out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN); |
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/* Save the first 128 bytes of DDR data */ |
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ls1_save_ddr_head(); |
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/* Save the kernel resume entry */ |
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out_le32(&scfg->sparecr[3], entry_point); |
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/* Request to put cluster 0 in PCL10 state */ |
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setbits_be32(&rcpm->clpcl10setr, RCPM_CLPCL10SETR_C0); |
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/* Setup the registers of the EPU FSM for deep sleep */ |
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ls1_fsm_setup(); |
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#ifdef QIXIS_BASE |
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/* Connect the EVENT button to IRQ in FPGA */ |
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tmp = in_8(qixis_base + QIXIS_CTL_SYS); |
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tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK; |
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tmp |= QIXIS_CTL_SYS_EVTSW_IRQ; |
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out_8(qixis_base + QIXIS_CTL_SYS, tmp); |
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/* Enable deep sleep signals in FPGA */ |
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tmp = in_8(qixis_base + QIXIS_PWR_CTL2); |
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tmp |= QIXIS_PWR_CTL2_PCTL; |
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out_8(qixis_base + QIXIS_PWR_CTL2, tmp); |
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/* Pull down PCIe RST# */ |
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tmp = in_8(qixis_base + QIXIS_RST_FORCE_3); |
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tmp |= QIXIS_RST_FORCE_3_PCIESLOT1; |
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out_8(qixis_base + QIXIS_RST_FORCE_3, tmp); |
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#endif |
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/* Enable Warm Device Reset */ |
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setbits_be32(&scfg->dpslpcr, SCFG_DPSLPCR_WDRR_EN); |
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setbits_be32(&gur->crstsr, DCFG_CRSTSR_WDRFR); |
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ls1_deepsleep_irq_cfg(); |
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psci_v7_flush_dcache_all(); |
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ls1_start_fsm(); |
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} |
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#else |
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static void __secure ls1_sleep(void) |
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{ |
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struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; |
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struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR; |
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#ifdef QIXIS_BASE |
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u32 tmp; |
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void *qixis_base = (void *)QIXIS_BASE; |
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/* Connect the EVENT button to IRQ in FPGA */ |
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tmp = in_8(qixis_base + QIXIS_CTL_SYS); |
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tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK; |
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tmp |= QIXIS_CTL_SYS_EVTSW_IRQ; |
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out_8(qixis_base + QIXIS_CTL_SYS, tmp); |
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#endif |
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/* Enable cluster to enter the PCL10 state */ |
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out_be32(&scfg->clusterpmcr, SCFG_CLUSTERPMCR_WFIL2EN); |
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setbits_be32(&rcpm->powmgtcsr, RCPM_POWMGTCSR_LPM20_REQ); |
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__asm__ __volatile__ ("wfi" : : : "memory"); |
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} |
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#endif |
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void __secure ls1_system_suspend(u32 fn, u32 entry_point, u32 context_id) |
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{ |
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#ifdef CONFIG_LS1_DEEP_SLEEP |
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ls1_deep_sleep(entry_point); |
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#else |
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ls1_sleep(); |
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#endif |
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} |
@ -0,0 +1,17 @@ |
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config ARCH_LS1012A |
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bool "Freescale Layerscape LS1012A SoC" |
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select SYS_FSL_MMDC |
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select SYS_FSL_ERRATUM_A010315 |
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config ARCH_LS1043A |
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bool "Freescale Layerscape LS1043A SoC" |
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select SYS_FSL_ERRATUM_A010315 |
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config ARCH_LS1046A |
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bool "Freescale Layerscape LS1046A SoC" |
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config SYS_FSL_MMDC |
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bool "Freescale Multi Mode DDR Controller" |
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config SYS_FSL_ERRATUM_A010315 |
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bool "Workaround for PCIe erratum A010315" |
@ -0,0 +1,16 @@ |
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/* |
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* Device Tree file for Freescale Layerscape-1046A family SoC. |
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* |
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* Copyright (C) 2016, Freescale Semiconductor |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/dts-v1/; |
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#include "fsl-ls1046a-qds.dtsi" |
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/ { |
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chosen { |
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stdout-path = &duart0; |
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}; |
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}; |
@ -0,0 +1,77 @@ |
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/* |
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* Device Tree Include file for Freescale Layerscape-1046A family SoC. |
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* |
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* Copyright (C) 2016, Freescale Semiconductor |
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* |
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* Mingkai Hu <Mingkai.hu@nxp.com> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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/include/ "fsl-ls1046a.dtsi" |
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/ { |
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model = "LS1046A QDS Board"; |
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aliases { |
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spi0 = &qspi; |
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spi1 = &dspi0; |
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}; |
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}; |
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&dspi0 { |
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bus-num = <0>; |
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status = "okay"; |
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dflash0: n25q128a { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "spi-flash"; |
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spi-max-frequency = <1000000>; /* input clock */ |
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spi-cpol; |
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spi-cpha; |
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reg = <0>; |
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}; |
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dflash1: sst25wf040b { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "spi-flash"; |
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spi-max-frequency = <3500000>; |
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spi-cpol; |
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spi-cpha; |
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reg = <1>; |
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}; |
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dflash2: en25s64 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "spi-flash"; |
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spi-max-frequency = <3500000>; |
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spi-cpol; |
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spi-cpha; |
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reg = <2>; |
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}; |
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}; |
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&qspi { |
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bus-num = <0>; |
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status = "okay"; |
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qflash0: s25fl128s@0 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "spi-flash"; |
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spi-max-frequency = <20000000>; |
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reg = <0>; |
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}; |
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}; |
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&duart0 { |
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status = "okay"; |
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}; |
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&duart1 { |
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status = "okay"; |
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}; |
@ -0,0 +1,44 @@ |
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/* |
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* Device Tree Include file for Freescale Layerscape-1046A family SoC. |
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* |
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* Copyright 2016, Freescale Semiconductor |
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* |
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* Mingkai Hu <Mingkai.hu@freescale.com> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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/dts-v1/; |
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/include/ "fsl-ls1046a.dtsi" |
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/ { |
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model = "LS1046A RDB Board"; |
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aliases { |
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spi0 = &qspi; |
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}; |
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}; |
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&qspi { |
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bus-num = <0>; |
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status = "okay"; |
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qflash0: s25fs512s@0 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "spi-flash"; |
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spi-max-frequency = <50000000>; |
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reg = <0>; |
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}; |
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qflash1: s25fs512s@1 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "spi-flash"; |
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spi-max-frequency = <50000000>; |
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reg = <1>; |
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}; |
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}; |
@ -0,0 +1,166 @@ |
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/* |
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* Device Tree Include file for Freescale Layerscape-1046A family SoC. |
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* |
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* Copyright (C) 2016, Freescale Semiconductor |
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* |
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* Mingkai Hu <mingkai.hu@nxp.com> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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/include/ "skeleton64.dtsi" |
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/ { |
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compatible = "fsl,ls1046a"; |
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interrupt-parent = <&gic>; |
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sysclk: sysclk { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <100000000>; |
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clock-output-names = "sysclk"; |
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}; |
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gic: interrupt-controller@1400000 { |
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compatible = "arm,gic-400"; |
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#interrupt-cells = <3>; |
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interrupt-controller; |
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reg = <0x0 0x1410000 0 0x10000>, /* GICD */ |
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<0x0 0x1420000 0 0x10000>, /* GICC */ |
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<0x0 0x1440000 0 0x20000>, /* GICH */ |
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<0x0 0x1460000 0 0x20000>; /* GICV */ |
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interrupts = <1 9 0xf08>; |
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}; |
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soc { |
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compatible = "simple-bus"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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clockgen: clocking@1ee1000 { |
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compatible = "fsl,ls1046a-clockgen"; |
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reg = <0x0 0x1ee1000 0x0 0x1000>; |
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#clock-cells = <2>; |
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clocks = <&sysclk>; |
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}; |
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dspi0: dspi@2100000 { |
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compatible = "fsl,vf610-dspi"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x0 0x2100000 0x0 0x10000>; |
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interrupts = <0 64 0x4>; |
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clock-names = "dspi"; |
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clocks = <&clockgen 4 0>; |
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num-cs = <6>; |
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big-endian; |
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status = "disabled"; |
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}; |
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dspi1: dspi@2110000 { |
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compatible = "fsl,vf610-dspi"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x0 0x2110000 0x0 0x10000>; |
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interrupts = <0 65 0x4>; |
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clock-names = "dspi"; |
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clocks = <&clockgen 4 0>; |
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num-cs = <6>; |
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big-endian; |
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status = "disabled"; |
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}; |
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ifc: ifc@1530000 { |
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compatible = "fsl,ifc", "simple-bus"; |
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reg = <0x0 0x1530000 0x0 0x10000>; |
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interrupts = <0 43 0x4>; |
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}; |
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i2c0: i2c@2180000 { |
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compatible = "fsl,vf610-i2c"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x0 0x2180000 0x0 0x10000>; |
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interrupts = <0 56 0x4>; |
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clock-names = "i2c"; |
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clocks = <&clockgen 4 0>; |
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status = "disabled"; |
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}; |
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i2c1: i2c@2190000 { |
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compatible = "fsl,vf610-i2c"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x0 0x2190000 0x0 0x10000>; |
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interrupts = <0 57 0x4>; |
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clock-names = "i2c"; |
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clocks = <&clockgen 4 0>; |
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status = "disabled"; |
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}; |
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|
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i2c2: i2c@21a0000 { |
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compatible = "fsl,vf610-i2c"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x0 0x21a0000 0x0 0x10000>; |
||||
interrupts = <0 58 0x4>; |
||||
clock-names = "i2c"; |
||||
clocks = <&clockgen 4 0>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
i2c3: i2c@21b0000 { |
||||
compatible = "fsl,vf610-i2c"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
reg = <0x0 0x21b0000 0x0 0x10000>; |
||||
interrupts = <0 59 0x4>; |
||||
clock-names = "i2c"; |
||||
clocks = <&clockgen 4 0>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
duart0: serial@21c0500 { |
||||
compatible = "fsl,ns16550", "ns16550a"; |
||||
reg = <0x00 0x21c0500 0x0 0x100>; |
||||
interrupts = <0 54 0x4>; |
||||
clocks = <&clockgen 4 0>; |
||||
}; |
||||
|
||||
duart1: serial@21c0600 { |
||||
compatible = "fsl,ns16550", "ns16550a"; |
||||
reg = <0x00 0x21c0600 0x0 0x100>; |
||||
interrupts = <0 54 0x4>; |
||||
clocks = <&clockgen 4 0>; |
||||
}; |
||||
|
||||
duart2: serial@21d0500 { |
||||
compatible = "fsl,ns16550", "ns16550a"; |
||||
reg = <0x0 0x21d0500 0x0 0x100>; |
||||
interrupts = <0 55 0x4>; |
||||
clocks = <&clockgen 4 0>; |
||||
}; |
||||
|
||||
duart3: serial@21d0600 { |
||||
compatible = "fsl,ns16550", "ns16550a"; |
||||
reg = <0x0 0x21d0600 0x0 0x100>; |
||||
interrupts = <0 55 0x4>; |
||||
clocks = <&clockgen 4 0>; |
||||
}; |
||||
|
||||
qspi: quadspi@1550000 { |
||||
compatible = "fsl,vf610-qspi"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
reg = <0x0 0x1550000 0x0 0x10000>, |
||||
<0x0 0x40000000 0x0 0x10000000>; |
||||
reg-names = "QuadSPI", "QuadSPI-memory"; |
||||
num-cs = <4>; |
||||
big-endian; |
||||
status = "disabled"; |
||||
}; |
||||
}; |
||||
}; |
@ -0,0 +1,15 @@ |
||||
if TARGET_LS1046AQDS |
||||
|
||||
config SYS_BOARD |
||||
default "ls1046aqds" |
||||
|
||||
config SYS_VENDOR |
||||
default "freescale" |
||||
|
||||
config SYS_SOC |
||||
default "fsl-layerscape" |
||||
|
||||
config SYS_CONFIG_NAME |
||||
default "ls1046aqds" |
||||
|
||||
endif |
@ -0,0 +1,10 @@ |
||||
LS1046AQDS BOARD |
||||
M: Mingkai Hu <Mingkai.Hu@nxp.com> |
||||
S: Maintained |
||||
F: board/freescale/ls1046aqds/ |
||||
F: include/configs/ls1046aqds.h |
||||
F: configs/ls1046aqds_defconfig |
||||
F: configs/ls1046aqds_nand_defconfig |
||||
F: configs/ls1046aqds_sdcard_ifc_defconfig |
||||
F: configs/ls1046aqds_sdcard_qspi_defconfig |
||||
F: configs/ls1046aqds_qspi_defconfig |
@ -0,0 +1,9 @@ |
||||
#
|
||||
# Copyright 2016 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += ddr.o
|
||||
obj-y += eth.o
|
||||
obj-y += ls1046aqds.o
|
@ -0,0 +1,70 @@ |
||||
Overview |
||||
-------- |
||||
The LS1046A Development System (QDS) is a high-performance computing, |
||||
evaluation, and development platform that supports the QorIQ LS1046A |
||||
LayerScape Architecture processor. The LS1046AQDS provides SW development |
||||
platform for the Freescale LS1046A processor series, with a complete |
||||
debugging environment. |
||||
|
||||
LS1046A SoC Overview |
||||
-------------------- |
||||
Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A |
||||
SoC overview. |
||||
|
||||
LS1046AQDS board Overview |
||||
----------------------- |
||||
- SERDES Connections, 8 lanes supporting: |
||||
- PCI Express - 3.0 |
||||
- SGMII, SGMII 2.5 |
||||
- QSGMII |
||||
- SATA 3.0 |
||||
- XFI |
||||
- DDR Controller |
||||
- 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s |
||||
-IFC/Local Bus |
||||
- One in-socket 128 MB NOR flash 16-bit data bus |
||||
- One 512 MB NAND flash with ECC support |
||||
- PromJet Port |
||||
- FPGA connection |
||||
- USB 3.0 |
||||
- Three high speed USB 3.0 ports |
||||
- First USB 3.0 port configured as Host with Type-A connector |
||||
- The other two USB 3.0 ports configured as OTG with micro-AB connector |
||||
- SDHC port connects directly to an adapter card slot, featuring: |
||||
- Optional clock feedback paths, and optional high-speed voltage translation assistance |
||||
- SD slots for SD, SDHC (1x, 4x, 8x), and/or MMC |
||||
- eMMC memory devices |
||||
- DSPI: Onboard support for three SPI flash memory devices |
||||
- 4 I2C controllers |
||||
- One SATA onboard connectors |
||||
- UART |
||||
- Two 4-pin serial ports at up to 115.2 Kbit/s |
||||
- Two DB9 D-Type connectors supporting one Serial port each |
||||
- ARM JTAG support |
||||
|
||||
Memory map from core's view |
||||
---------------------------- |
||||
Start Address End Address Description Size |
||||
0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB |
||||
0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB |
||||
0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB |
||||
0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB |
||||
0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB |
||||
0x00_6000_0000 - 0x00_67FF_FFFF IFC - NOR Flash 128MB |
||||
0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB |
||||
0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - FPGA 4KB |
||||
0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB |
||||
0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M |
||||
0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M |
||||
0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB |
||||
0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G |
||||
0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G |
||||
0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G |
||||
|
||||
Booting Options |
||||
--------------- |
||||
a) Promjet Boot |
||||
b) NOR boot |
||||
c) NAND boot |
||||
d) SD boot |
||||
e) QSPI boot |
@ -0,0 +1,140 @@ |
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <fsl_ddr_sdram.h> |
||||
#include <fsl_ddr_dimm_params.h> |
||||
#ifdef CONFIG_FSL_DEEP_SLEEP |
||||
#include <fsl_sleep.h> |
||||
#endif |
||||
#include "ddr.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
void fsl_ddr_board_options(memctl_options_t *popts, |
||||
dimm_params_t *pdimm, |
||||
unsigned int ctrl_num) |
||||
{ |
||||
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; |
||||
ulong ddr_freq; |
||||
|
||||
if (ctrl_num > 3) { |
||||
printf("Not supported controller number %d\n", ctrl_num); |
||||
return; |
||||
} |
||||
if (!pdimm->n_ranks) |
||||
return; |
||||
|
||||
pbsp = udimms[0]; |
||||
|
||||
/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
|
||||
* freqency and n_banks specified in board_specific_parameters table. |
||||
*/ |
||||
ddr_freq = get_ddr_freq(0) / 1000000; |
||||
while (pbsp->datarate_mhz_high) { |
||||
if (pbsp->n_ranks == pdimm->n_ranks) { |
||||
if (ddr_freq <= pbsp->datarate_mhz_high) { |
||||
popts->clk_adjust = pbsp->clk_adjust; |
||||
popts->wrlvl_start = pbsp->wrlvl_start; |
||||
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
||||
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
||||
goto found; |
||||
} |
||||
pbsp_highest = pbsp; |
||||
} |
||||
pbsp++; |
||||
} |
||||
|
||||
if (pbsp_highest) { |
||||
printf("Error: board specific timing not found for %lu MT/s\n", |
||||
ddr_freq); |
||||
printf("Trying to use the highest speed (%u) parameters\n", |
||||
pbsp_highest->datarate_mhz_high); |
||||
popts->clk_adjust = pbsp_highest->clk_adjust; |
||||
popts->wrlvl_start = pbsp_highest->wrlvl_start; |
||||
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
||||
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
||||
} else { |
||||
panic("DIMM is not supported by this board"); |
||||
} |
||||
found: |
||||
debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", |
||||
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); |
||||
|
||||
popts->data_bus_width = 0; /* 64b data bus */ |
||||
popts->otf_burst_chop_en = 0; |
||||
popts->burst_length = DDR_BL8; |
||||
popts->bstopre = 0; /* enable auto precharge */ |
||||
|
||||
popts->half_strength_driver_enable = 0; |
||||
/*
|
||||
* Write leveling override |
||||
*/ |
||||
popts->wrlvl_override = 1; |
||||
popts->wrlvl_sample = 0xf; |
||||
|
||||
/*
|
||||
* Rtt and Rtt_WR override |
||||
*/ |
||||
popts->rtt_override = 0; |
||||
|
||||
/* Enable ZQ calibration */ |
||||
popts->zq_en = 1; |
||||
|
||||
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); |
||||
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | |
||||
DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; |
||||
} |
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
phys_size_t dram_size; |
||||
|
||||
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) |
||||
return fsl_ddr_sdram_size(); |
||||
#else |
||||
puts("Initializing DDR....using SPD\n"); |
||||
|
||||
dram_size = fsl_ddr_sdram(); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_FSL_DEEP_SLEEP |
||||
fsl_dp_ddr_restore(); |
||||
#endif |
||||
|
||||
erratum_a008850_post(); |
||||
|
||||
return dram_size; |
||||
} |
||||
|
||||
void dram_init_banksize(void) |
||||
{ |
||||
/*
|
||||
* gd->arch.secure_ram tracks the location of secure memory. |
||||
* It was set as if the memory starts from 0. |
||||
* The address needs to add the offset of its bank. |
||||
*/ |
||||
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; |
||||
if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { |
||||
gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; |
||||
gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; |
||||
gd->bd->bi_dram[1].size = gd->ram_size - |
||||
CONFIG_SYS_DDR_BLOCK1_SIZE; |
||||
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE |
||||
gd->arch.secure_ram = gd->bd->bi_dram[1].start + |
||||
gd->arch.secure_ram - |
||||
CONFIG_SYS_DDR_BLOCK1_SIZE; |
||||
gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; |
||||
#endif |
||||
} else { |
||||
gd->bd->bi_dram[0].size = gd->ram_size; |
||||
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE |
||||
gd->arch.secure_ram = gd->bd->bi_dram[0].start + |
||||
gd->arch.secure_ram; |
||||
gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; |
||||
#endif |
||||
} |
||||
} |
@ -0,0 +1,44 @@ |
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __DDR_H__ |
||||
#define __DDR_H__ |
||||
|
||||
void erratum_a008850_post(void); |
||||
|
||||
struct board_specific_parameters { |
||||
u32 n_ranks; |
||||
u32 datarate_mhz_high; |
||||
u32 rank_gb; |
||||
u32 clk_adjust; |
||||
u32 wrlvl_start; |
||||
u32 wrlvl_ctl_2; |
||||
u32 wrlvl_ctl_3; |
||||
}; |
||||
|
||||
/*
|
||||
* These tables contain all valid speeds we want to override with board |
||||
* specific parameters. datarate_mhz_high values need to be in ascending order |
||||
* for each n_ranks group. |
||||
*/ |
||||
static const struct board_specific_parameters udimm0[] = { |
||||
/*
|
||||
* memory controller 0 |
||||
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | |
||||
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |
||||
*/ |
||||
{2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, |
||||
{2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, |
||||
{2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, |
||||
{2, 2300, 0, 8, 9, 0x0A0C0D11, 0x1214150E,}, |
||||
{} |
||||
}; |
||||
|
||||
static const struct board_specific_parameters *udimms[] = { |
||||
udimm0, |
||||
}; |
||||
|
||||
#endif |
@ -0,0 +1,415 @@ |
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <netdev.h> |
||||
#include <fdt_support.h> |
||||
#include <fm_eth.h> |
||||
#include <fsl_mdio.h> |
||||
#include <fsl_dtsec.h> |
||||
#include <malloc.h> |
||||
#include <asm/arch/fsl_serdes.h> |
||||
|
||||
#include "../common/qixis.h" |
||||
#include "../common/fman.h" |
||||
#include "ls1046aqds_qixis.h" |
||||
|
||||
#define EMI_NONE 0xFF |
||||
#define EMI1_RGMII1 0 |
||||
#define EMI1_RGMII2 1 |
||||
#define EMI1_SLOT1 2 |
||||
#define EMI1_SLOT2 3 |
||||
#define EMI1_SLOT4 4 |
||||
|
||||
static int mdio_mux[NUM_FM_PORTS]; |
||||
|
||||
static const char * const mdio_names[] = { |
||||
"LS1046AQDS_MDIO_RGMII1", |
||||
"LS1046AQDS_MDIO_RGMII2", |
||||
"LS1046AQDS_MDIO_SLOT1", |
||||
"LS1046AQDS_MDIO_SLOT2", |
||||
"LS1046AQDS_MDIO_SLOT4", |
||||
"NULL", |
||||
}; |
||||
|
||||
/* Map SerDes 1 & 2 lanes to default slot. */ |
||||
static u8 lane_to_slot[] = {1, 1, 1, 1, 0, 4, 0 , 0}; |
||||
|
||||
static const char *ls1046aqds_mdio_name_for_muxval(u8 muxval) |
||||
{ |
||||
return mdio_names[muxval]; |
||||
} |
||||
|
||||
struct mii_dev *mii_dev_for_muxval(u8 muxval) |
||||
{ |
||||
struct mii_dev *bus; |
||||
const char *name; |
||||
|
||||
if (muxval > EMI1_SLOT4) |
||||
return NULL; |
||||
|
||||
name = ls1046aqds_mdio_name_for_muxval(muxval); |
||||
|
||||
if (!name) { |
||||
printf("No bus for muxval %x\n", muxval); |
||||
return NULL; |
||||
} |
||||
|
||||
bus = miiphy_get_dev_by_name(name); |
||||
|
||||
if (!bus) { |
||||
printf("No bus by name %s\n", name); |
||||
return NULL; |
||||
} |
||||
|
||||
return bus; |
||||
} |
||||
|
||||
struct ls1046aqds_mdio { |
||||
u8 muxval; |
||||
struct mii_dev *realbus; |
||||
}; |
||||
|
||||
static void ls1046aqds_mux_mdio(u8 muxval) |
||||
{ |
||||
u8 brdcfg4; |
||||
|
||||
if (muxval < 7) { |
||||
brdcfg4 = QIXIS_READ(brdcfg[4]); |
||||
brdcfg4 &= ~BRDCFG4_EMISEL_MASK; |
||||
brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); |
||||
QIXIS_WRITE(brdcfg[4], brdcfg4); |
||||
} |
||||
} |
||||
|
||||
static int ls1046aqds_mdio_read(struct mii_dev *bus, int addr, int devad, |
||||
int regnum) |
||||
{ |
||||
struct ls1046aqds_mdio *priv = bus->priv; |
||||
|
||||
ls1046aqds_mux_mdio(priv->muxval); |
||||
|
||||
return priv->realbus->read(priv->realbus, addr, devad, regnum); |
||||
} |
||||
|
||||
static int ls1046aqds_mdio_write(struct mii_dev *bus, int addr, int devad, |
||||
int regnum, u16 value) |
||||
{ |
||||
struct ls1046aqds_mdio *priv = bus->priv; |
||||
|
||||
ls1046aqds_mux_mdio(priv->muxval); |
||||
|
||||
return priv->realbus->write(priv->realbus, addr, devad, |
||||
regnum, value); |
||||
} |
||||
|
||||
static int ls1046aqds_mdio_reset(struct mii_dev *bus) |
||||
{ |
||||
struct ls1046aqds_mdio *priv = bus->priv; |
||||
|
||||
return priv->realbus->reset(priv->realbus); |
||||
} |
||||
|
||||
static int ls1046aqds_mdio_init(char *realbusname, u8 muxval) |
||||
{ |
||||
struct ls1046aqds_mdio *pmdio; |
||||
struct mii_dev *bus = mdio_alloc(); |
||||
|
||||
if (!bus) { |
||||
printf("Failed to allocate ls1046aqds MDIO bus\n"); |
||||
return -1; |
||||
} |
||||
|
||||
pmdio = malloc(sizeof(*pmdio)); |
||||
if (!pmdio) { |
||||
printf("Failed to allocate ls1046aqds private data\n"); |
||||
free(bus); |
||||
return -1; |
||||
} |
||||
|
||||
bus->read = ls1046aqds_mdio_read; |
||||
bus->write = ls1046aqds_mdio_write; |
||||
bus->reset = ls1046aqds_mdio_reset; |
||||
sprintf(bus->name, ls1046aqds_mdio_name_for_muxval(muxval)); |
||||
|
||||
pmdio->realbus = miiphy_get_dev_by_name(realbusname); |
||||
|
||||
if (!pmdio->realbus) { |
||||
printf("No bus with name %s\n", realbusname); |
||||
free(bus); |
||||
free(pmdio); |
||||
return -1; |
||||
} |
||||
|
||||
pmdio->muxval = muxval; |
||||
bus->priv = pmdio; |
||||
return mdio_register(bus); |
||||
} |
||||
|
||||
void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, |
||||
enum fm_port port, int offset) |
||||
{ |
||||
struct fixed_link f_link; |
||||
|
||||
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { |
||||
switch (port) { |
||||
case FM1_DTSEC9: |
||||
fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p1"); |
||||
break; |
||||
case FM1_DTSEC10: |
||||
fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p2"); |
||||
break; |
||||
case FM1_DTSEC5: |
||||
fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p3"); |
||||
break; |
||||
case FM1_DTSEC6: |
||||
fdt_set_phy_handle(fdt, compat, addr, "sgmii_s1_p4"); |
||||
break; |
||||
case FM1_DTSEC2: |
||||
fdt_set_phy_handle(fdt, compat, addr, "sgmii_s4_p1"); |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) { |
||||
/* 2.5G SGMII interface */ |
||||
f_link.phy_id = cpu_to_fdt32(port); |
||||
f_link.duplex = cpu_to_fdt32(1); |
||||
f_link.link_speed = cpu_to_fdt32(1000); |
||||
f_link.pause = 0; |
||||
f_link.asym_pause = 0; |
||||
/* no PHY for 2.5G SGMII on QDS */ |
||||
fdt_delprop(fdt, offset, "phy-handle"); |
||||
fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); |
||||
fdt_setprop_string(fdt, offset, "phy-connection-type", |
||||
"sgmii-2500"); |
||||
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { |
||||
switch (port) { |
||||
case FM1_DTSEC1: |
||||
fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p4"); |
||||
break; |
||||
case FM1_DTSEC5: |
||||
fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p2"); |
||||
break; |
||||
case FM1_DTSEC6: |
||||
fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p1"); |
||||
break; |
||||
case FM1_DTSEC10: |
||||
fdt_set_phy_handle(fdt, compat, addr, "qsgmii_s2_p3"); |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
fdt_delprop(fdt, offset, "phy-connection-type"); |
||||
fdt_setprop_string(fdt, offset, "phy-connection-type", |
||||
"qsgmii"); |
||||
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && |
||||
(port == FM1_10GEC1 || port == FM1_10GEC2)) { |
||||
/* XFI interface */ |
||||
f_link.phy_id = cpu_to_fdt32(port); |
||||
f_link.duplex = cpu_to_fdt32(1); |
||||
f_link.link_speed = cpu_to_fdt32(10000); |
||||
f_link.pause = 0; |
||||
f_link.asym_pause = 0; |
||||
/* no PHY for XFI */ |
||||
fdt_delprop(fdt, offset, "phy-handle"); |
||||
fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); |
||||
fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii"); |
||||
} |
||||
} |
||||
|
||||
void fdt_fixup_board_enet(void *fdt) |
||||
{ |
||||
int i; |
||||
|
||||
for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) { |
||||
switch (fm_info_get_enet_if(i)) { |
||||
case PHY_INTERFACE_MODE_SGMII: |
||||
case PHY_INTERFACE_MODE_QSGMII: |
||||
switch (mdio_mux[i]) { |
||||
case EMI1_SLOT1: |
||||
fdt_status_okay_by_alias(fdt, "emi1_slot1"); |
||||
break; |
||||
case EMI1_SLOT2: |
||||
fdt_status_okay_by_alias(fdt, "emi1_slot2"); |
||||
break; |
||||
case EMI1_SLOT4: |
||||
fdt_status_okay_by_alias(fdt, "emi1_slot4"); |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
} |
||||
} |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
#ifdef CONFIG_FMAN_ENET |
||||
int i, idx, lane, slot, interface; |
||||
struct memac_mdio_info dtsec_mdio_info; |
||||
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
||||
u32 srds_s1, srds_s2; |
||||
u8 brdcfg12; |
||||
|
||||
srds_s1 = in_be32(&gur->rcwsr[4]) & |
||||
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; |
||||
srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; |
||||
|
||||
srds_s2 = in_be32(&gur->rcwsr[4]) & |
||||
FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; |
||||
srds_s2 >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT; |
||||
|
||||
/* Initialize the mdio_mux array so we can recognize empty elements */ |
||||
for (i = 0; i < NUM_FM_PORTS; i++) |
||||
mdio_mux[i] = EMI_NONE; |
||||
|
||||
dtsec_mdio_info.regs = |
||||
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; |
||||
|
||||
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; |
||||
|
||||
/* Register the 1G MDIO bus */ |
||||
fm_memac_mdio_init(bis, &dtsec_mdio_info); |
||||
|
||||
/* Register the muxing front-ends to the MDIO buses */ |
||||
ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); |
||||
ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); |
||||
ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); |
||||
ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); |
||||
ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); |
||||
|
||||
/* Set the two on-board RGMII PHY address */ |
||||
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); |
||||
|
||||
switch (srds_s1) { |
||||
case 0x3333: |
||||
/* SGMII on slot 1, MAC 9 */ |
||||
fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); |
||||
case 0x1333: |
||||
case 0x2333: |
||||
/* SGMII on slot 1, MAC 10 */ |
||||
fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); |
||||
case 0x1133: |
||||
case 0x2233: |
||||
/* SGMII on slot 1, MAC 5/6 */ |
||||
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); |
||||
break; |
||||
case 0x1040: |
||||
case 0x2040: |
||||
/* QSGMII on lane B, MAC 6/5/10/1 */ |
||||
fm_info_set_phy_address(FM1_DTSEC6, |
||||
QSGMII_CARD_PORT1_PHY_ADDR_S2); |
||||
fm_info_set_phy_address(FM1_DTSEC5, |
||||
QSGMII_CARD_PORT2_PHY_ADDR_S2); |
||||
fm_info_set_phy_address(FM1_DTSEC10, |
||||
QSGMII_CARD_PORT3_PHY_ADDR_S2); |
||||
fm_info_set_phy_address(FM1_DTSEC1, |
||||
QSGMII_CARD_PORT4_PHY_ADDR_S2); |
||||
break; |
||||
case 0x3363: |
||||
/* SGMII on slot 1, MAC 9/10 */ |
||||
fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); |
||||
case 0x1163: |
||||
case 0x2263: |
||||
case 0x2223: |
||||
/* SGMII on slot 1, MAC 6 */ |
||||
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); |
||||
break; |
||||
default: |
||||
printf("Invalid SerDes protocol 0x%x for LS1046AQDS\n", |
||||
srds_s1); |
||||
break; |
||||
} |
||||
|
||||
if (srds_s2 == 0x5a59 || srds_s2 == 0x5a06) |
||||
/* SGMII on slot 4, MAC 2 */ |
||||
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); |
||||
|
||||
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { |
||||
idx = i - FM1_DTSEC1; |
||||
interface = fm_info_get_enet_if(i); |
||||
switch (interface) { |
||||
case PHY_INTERFACE_MODE_SGMII: |
||||
case PHY_INTERFACE_MODE_QSGMII: |
||||
if (interface == PHY_INTERFACE_MODE_SGMII) { |
||||
if (i == FM1_DTSEC5) { |
||||
/* route lane 2 to slot1 so to have
|
||||
* one sgmii riser card supports |
||||
* MAC5 and MAC6. |
||||
*/ |
||||
brdcfg12 = QIXIS_READ(brdcfg[12]); |
||||
QIXIS_WRITE(brdcfg[12], |
||||
brdcfg12 | 0x80); |
||||
} |
||||
lane = serdes_get_first_lane(FSL_SRDS_1, |
||||
SGMII_FM1_DTSEC1 + idx); |
||||
} else { |
||||
/* clear the bit 7 to route lane B on slot2. */ |
||||
brdcfg12 = QIXIS_READ(brdcfg[12]); |
||||
QIXIS_WRITE(brdcfg[12], brdcfg12 & 0x7f); |
||||
|
||||
lane = serdes_get_first_lane(FSL_SRDS_1, |
||||
QSGMII_FM1_A); |
||||
lane_to_slot[lane] = 2; |
||||
} |
||||
|
||||
if (i == FM1_DTSEC2) |
||||
lane = 5; |
||||
|
||||
if (lane < 0) |
||||
break; |
||||
|
||||
slot = lane_to_slot[lane]; |
||||
debug("FM1@DTSEC%u expects SGMII in slot %u\n", |
||||
idx + 1, slot); |
||||
if (QIXIS_READ(present2) & (1 << (slot - 1))) |
||||
fm_disable_port(i); |
||||
|
||||
switch (slot) { |
||||
case 1: |
||||
mdio_mux[i] = EMI1_SLOT1; |
||||
fm_info_set_mdio(i, mii_dev_for_muxval( |
||||
mdio_mux[i])); |
||||
break; |
||||
case 2: |
||||
mdio_mux[i] = EMI1_SLOT2; |
||||
fm_info_set_mdio(i, mii_dev_for_muxval( |
||||
mdio_mux[i])); |
||||
break; |
||||
case 4: |
||||
mdio_mux[i] = EMI1_SLOT4; |
||||
fm_info_set_mdio(i, mii_dev_for_muxval( |
||||
mdio_mux[i])); |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
break; |
||||
case PHY_INTERFACE_MODE_RGMII: |
||||
if (i == FM1_DTSEC3) |
||||
mdio_mux[i] = EMI1_RGMII1; |
||||
else if (i == FM1_DTSEC4) |
||||
mdio_mux[i] = EMI1_RGMII2; |
||||
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
} |
||||
|
||||
cpu_eth_init(bis); |
||||
#endif /* CONFIG_FMAN_ENET */ |
||||
|
||||
return pci_eth_init(bis); |
||||
} |
@ -0,0 +1,298 @@ |
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <i2c.h> |
||||
#include <fdt_support.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/fsl_serdes.h> |
||||
#include <asm/arch/fdt.h> |
||||
#include <asm/arch/soc.h> |
||||
#include <ahci.h> |
||||
#include <hwconfig.h> |
||||
#include <mmc.h> |
||||
#include <scsi.h> |
||||
#include <fm_eth.h> |
||||
#include <fsl_csu.h> |
||||
#include <fsl_esdhc.h> |
||||
#include <fsl_ifc.h> |
||||
#include <spl.h> |
||||
|
||||
#include "../common/vid.h" |
||||
#include "../common/qixis.h" |
||||
#include "ls1046aqds_qixis.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
enum { |
||||
MUX_TYPE_GPIO, |
||||
}; |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
char buf[64]; |
||||
#ifndef CONFIG_SD_BOOT |
||||
u8 sw; |
||||
#endif |
||||
|
||||
puts("Board: LS1046AQDS, boot from "); |
||||
|
||||
#ifdef CONFIG_SD_BOOT |
||||
puts("SD\n"); |
||||
#else |
||||
sw = QIXIS_READ(brdcfg[0]); |
||||
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; |
||||
|
||||
if (sw < 0x8) |
||||
printf("vBank: %d\n", sw); |
||||
else if (sw == 0x8) |
||||
puts("PromJet\n"); |
||||
else if (sw == 0x9) |
||||
puts("NAND\n"); |
||||
else if (sw == 0xF) |
||||
printf("QSPI\n"); |
||||
else |
||||
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); |
||||
#endif |
||||
|
||||
printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n", |
||||
QIXIS_READ(id), QIXIS_READ(arch)); |
||||
|
||||
printf("FPGA: v%d (%s), build %d\n", |
||||
(int)QIXIS_READ(scver), qixis_read_tag(buf), |
||||
(int)qixis_read_minor()); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
bool if_board_diff_clk(void) |
||||
{ |
||||
u8 diff_conf = QIXIS_READ(brdcfg[11]); |
||||
|
||||
return diff_conf & 0x40; |
||||
} |
||||
|
||||
unsigned long get_board_sys_clk(void) |
||||
{ |
||||
u8 sysclk_conf = QIXIS_READ(brdcfg[1]); |
||||
|
||||
switch (sysclk_conf & 0x0f) { |
||||
case QIXIS_SYSCLK_64: |
||||
return 64000000; |
||||
case QIXIS_SYSCLK_83: |
||||
return 83333333; |
||||
case QIXIS_SYSCLK_100: |
||||
return 100000000; |
||||
case QIXIS_SYSCLK_125: |
||||
return 125000000; |
||||
case QIXIS_SYSCLK_133: |
||||
return 133333333; |
||||
case QIXIS_SYSCLK_150: |
||||
return 150000000; |
||||
case QIXIS_SYSCLK_160: |
||||
return 160000000; |
||||
case QIXIS_SYSCLK_166: |
||||
return 166666666; |
||||
} |
||||
|
||||
return 66666666; |
||||
} |
||||
|
||||
unsigned long get_board_ddr_clk(void) |
||||
{ |
||||
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); |
||||
|
||||
if (if_board_diff_clk()) |
||||
return get_board_sys_clk(); |
||||
switch ((ddrclk_conf & 0x30) >> 4) { |
||||
case QIXIS_DDRCLK_100: |
||||
return 100000000; |
||||
case QIXIS_DDRCLK_125: |
||||
return 125000000; |
||||
case QIXIS_DDRCLK_133: |
||||
return 133333333; |
||||
} |
||||
|
||||
return 66666666; |
||||
} |
||||
|
||||
int select_i2c_ch_pca9547(u8 ch) |
||||
{ |
||||
int ret; |
||||
|
||||
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); |
||||
if (ret) { |
||||
puts("PCA: failed to select proper channel\n"); |
||||
return ret; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
/*
|
||||
* When resuming from deep sleep, the I2C channel may not be |
||||
* in the default channel. So, switch to the default channel |
||||
* before accessing DDR SPD. |
||||
*/ |
||||
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); |
||||
gd->ram_size = initdram(0); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int i2c_multiplexer_select_vid_channel(u8 channel) |
||||
{ |
||||
return select_i2c_ch_pca9547(channel); |
||||
} |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
#ifdef CONFIG_HAS_FSL_XHCI_USB |
||||
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; |
||||
u32 usb_pwrfault; |
||||
#endif |
||||
|
||||
#ifdef CONFIG_SYS_I2C_EARLY_INIT |
||||
i2c_early_init_f(); |
||||
#endif |
||||
fsl_lsch2_early_init_f(); |
||||
|
||||
#ifdef CONFIG_HAS_FSL_XHCI_USB |
||||
out_be32(&scfg->rcwpmuxcr0, 0x3333); |
||||
out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); |
||||
usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << |
||||
SCFG_USBPWRFAULT_USB3_SHIFT) | |
||||
(SCFG_USBPWRFAULT_DEDICATED << |
||||
SCFG_USBPWRFAULT_USB2_SHIFT) | |
||||
(SCFG_USBPWRFAULT_SHARED << |
||||
SCFG_USBPWRFAULT_USB1_SHIFT); |
||||
out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_FSL_DEEP_SLEEP |
||||
/* determine if it is a warm boot */ |
||||
bool is_warm_boot(void) |
||||
{ |
||||
#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) |
||||
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; |
||||
|
||||
if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) |
||||
return 1; |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
int config_board_mux(int ctrl_type) |
||||
{ |
||||
u8 reg14; |
||||
|
||||
reg14 = QIXIS_READ(brdcfg[14]); |
||||
|
||||
switch (ctrl_type) { |
||||
case MUX_TYPE_GPIO: |
||||
reg14 = (reg14 & (~0x6)) | 0x2; |
||||
break; |
||||
default: |
||||
puts("Unsupported mux interface type\n"); |
||||
return -1; |
||||
} |
||||
|
||||
QIXIS_WRITE(brdcfg[14], reg14); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int config_serdes_mux(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_MISC_INIT_R |
||||
int misc_init_r(void) |
||||
{ |
||||
if (hwconfig("gpio")) |
||||
config_board_mux(MUX_TYPE_GPIO); |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
int board_init(void) |
||||
{ |
||||
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); |
||||
|
||||
#ifdef CONFIG_SYS_FSL_SERDES |
||||
config_serdes_mux(); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS |
||||
enable_layerscape_ns_access(); |
||||
#endif |
||||
|
||||
if (adjust_vdd(0)) |
||||
printf("Warning: Adjusting core voltage failed.\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_OF_BOARD_SETUP |
||||
int ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
u64 base[CONFIG_NR_DRAM_BANKS]; |
||||
u64 size[CONFIG_NR_DRAM_BANKS]; |
||||
u8 reg; |
||||
|
||||
/* fixup DT for the two DDR banks */ |
||||
base[0] = gd->bd->bi_dram[0].start; |
||||
size[0] = gd->bd->bi_dram[0].size; |
||||
base[1] = gd->bd->bi_dram[1].start; |
||||
size[1] = gd->bd->bi_dram[1].size; |
||||
|
||||
fdt_fixup_memory_banks(blob, base, size, 2); |
||||
ft_cpu_setup(blob, bd); |
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN |
||||
fdt_fixup_fman_ethernet(blob); |
||||
fdt_fixup_board_enet(blob); |
||||
#endif |
||||
|
||||
reg = QIXIS_READ(brdcfg[0]); |
||||
reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; |
||||
|
||||
/* Disable IFC if QSPI is enabled */ |
||||
if (reg == 0xF) |
||||
do_fixup_by_compat(blob, "fsl,ifc", |
||||
"status", "disabled", 8 + 1, 1); |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
u8 flash_read8(void *addr) |
||||
{ |
||||
return __raw_readb(addr + 1); |
||||
} |
||||
|
||||
void flash_write16(u16 val, void *addr) |
||||
{ |
||||
u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); |
||||
|
||||
__raw_writew(shftval, addr); |
||||
} |
||||
|
||||
u16 flash_read16(void *addr) |
||||
{ |
||||
u16 val = __raw_readw(addr); |
||||
|
||||
return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); |
||||
} |
@ -0,0 +1,17 @@ |
||||
#Configure Scratch register |
||||
09570600 00000000 |
||||
09570604 10000000 |
||||
#Alt base register |
||||
09570158 00001000 |
||||
#Disable CCI barrier tranaction |
||||
09570178 0000e010 |
||||
09180000 00000008 |
||||
#USB PHY frequency sel |
||||
09570418 0000009e |
||||
0957041c 0000009e |
||||
09570420 0000009e |
||||
#Serdes SATA |
||||
09eb1300 80104e20 |
||||
09eb08dc 00502880 |
||||
#flush PBI data |
||||
096100c0 000fffff |
@ -0,0 +1,39 @@ |
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __LS1046AQDS_QIXIS_H__ |
||||
#define __LS1046AQDS_QIXIS_H__ |
||||
|
||||
/* Definitions of QIXIS Registers for LS1046AQDS */ |
||||
|
||||
/* BRDCFG4[4:7] select EC1 and EC2 as a pair */ |
||||
#define BRDCFG4_EMISEL_MASK 0xe0 |
||||
#define BRDCFG4_EMISEL_SHIFT 5 |
||||
|
||||
/* SYSCLK */ |
||||
#define QIXIS_SYSCLK_66 0x0 |
||||
#define QIXIS_SYSCLK_83 0x1 |
||||
#define QIXIS_SYSCLK_100 0x2 |
||||
#define QIXIS_SYSCLK_125 0x3 |
||||
#define QIXIS_SYSCLK_133 0x4 |
||||
#define QIXIS_SYSCLK_150 0x5 |
||||
#define QIXIS_SYSCLK_160 0x6 |
||||
#define QIXIS_SYSCLK_166 0x7 |
||||
#define QIXIS_SYSCLK_64 0x8 |
||||
|
||||
/* DDRCLK */ |
||||
#define QIXIS_DDRCLK_66 0x0 |
||||
#define QIXIS_DDRCLK_100 0x1 |
||||
#define QIXIS_DDRCLK_125 0x2 |
||||
#define QIXIS_DDRCLK_133 0x3 |
||||
|
||||
/* BRDCFG2 - SD clock*/ |
||||
#define QIXIS_SDCLK1_100 0x0 |
||||
#define QIXIS_SDCLK1_125 0x1 |
||||
#define QIXIS_SDCLK1_165 0x2 |
||||
#define QIXIS_SDCLK1_100_SP 0x3 |
||||
|
||||
#endif |
@ -0,0 +1,7 @@ |
||||
#PBL preamble and RCW header |
||||
aa55aa55 01ee0100 |
||||
# serdes protocol |
||||
0c150010 0e000000 00000000 00000000 |
||||
11335559 40005012 e0116000 c1000000 |
||||
00000000 00000000 00000000 00038800 |
||||
00000000 01001101 00000096 00000001 |
@ -0,0 +1,8 @@ |
||||
#PBL preamble and RCW header |
||||
aa55aa55 01ee0100 |
||||
# RCW |
||||
# Enable IFC; disable QSPI |
||||
0c150010 0e000000 00000000 00000000 |
||||
11335559 40005012 60040000 c1000000 |
||||
00000000 00000000 00000000 00038800 |
||||
00000000 01001101 00000096 00000001 |
@ -0,0 +1,8 @@ |
||||
#PBL preamble and RCW header |
||||
aa55aa55 01ee0100 |
||||
# RCW |
||||
# Enable QSPI; disable IFC |
||||
0c150010 0e000000 00000000 00000000 |
||||
11335559 40005012 60040000 c1000000 |
||||
00000000 00000000 00000000 00038800 |
||||
20124000 01001101 00000096 00000001 |
@ -0,0 +1,16 @@ |
||||
|
||||
if TARGET_LS1046ARDB |
||||
|
||||
config SYS_BOARD |
||||
default "ls1046ardb" |
||||
|
||||
config SYS_VENDOR |
||||
default "freescale" |
||||
|
||||
config SYS_SOC |
||||
default "fsl-layerscape" |
||||
|
||||
config SYS_CONFIG_NAME |
||||
default "ls1046ardb" |
||||
|
||||
endif |
@ -0,0 +1,9 @@ |
||||
LS1046A BOARD |
||||
M: Mingkai Hu <mingkai.hu@nxp.com> |
||||
S: Maintained |
||||
F: board/freescale/ls1046ardb/ |
||||
F: board/freescale/ls1046ardb/ls1046ardb.c |
||||
F: include/configs/ls1046ardb.h |
||||
F: configs/ls1046ardb_qspi_defconfig |
||||
F: configs/ls1046ardb_sdcard_defconfig |
||||
F: configs/ls1046ardb_emmc_defconfig |
@ -0,0 +1,10 @@ |
||||
#
|
||||
# Copyright 2016 Freescale Semiconductor
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += cpld.o
|
||||
obj-y += ddr.o
|
||||
obj-y += ls1046ardb.o
|
||||
obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o
|
@ -0,0 +1,76 @@ |
||||
Overview |
||||
-------- |
||||
The LS1046A Reference Design Board (RDB) is a high-performance computing, |
||||
evaluation, and development platform that supports the QorIQ LS1046A |
||||
LayerScape Architecture processor. The LS1046ARDB provides SW development |
||||
platform for the Freescale LS1046A processor series, with a complete |
||||
debugging environment. The LS1046A RDB is lead-free and RoHS-compliant. |
||||
|
||||
LS1046A SoC Overview |
||||
-------------------- |
||||
Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A |
||||
SoC overview. |
||||
|
||||
LS1046ARDB board Overview |
||||
----------------------- |
||||
- SERDES1 Connections, 4 lanes supporting: |
||||
- Lane0: XFI with x1 RJ45 connector |
||||
- Lane1: XFI Cage |
||||
- Lane2: SGMII.5 |
||||
- Lane3: SGMII.6 |
||||
- SERDES2 Connections, 4 lanes supporting: |
||||
- Lane0: PCIe1 with miniPCIe slot |
||||
- Lane1: PCIe2 with PCIe x2 slot |
||||
- Lane2: PCIe3 with PCIe x4 slot |
||||
- Lane3: SATA |
||||
- DDR Controller |
||||
- 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s |
||||
-IFC/Local Bus |
||||
- One 512 MB NAND flash with ECC support |
||||
- CPLD connection |
||||
- USB 3.0 |
||||
- one Type A port, one Micro-AB port |
||||
- SDHC: connects directly to a full SD/MMC slot |
||||
- DSPI: 64 MB high-speed flash Memory for boot code and storage (up to 108MHz) |
||||
- 4 I2C controllers |
||||
- UART |
||||
- Two 4-pin serial ports at up to 115.2 Kbit/s |
||||
- Two DB9 D-Type connectors supporting one Serial port each |
||||
- ARM JTAG support |
||||
|
||||
Memory map from core's view |
||||
---------------------------- |
||||
Start Address End Address Description Size |
||||
0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB |
||||
0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB |
||||
0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB |
||||
0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB |
||||
0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB |
||||
0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB |
||||
0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB |
||||
0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB |
||||
0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M |
||||
0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M |
||||
0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB |
||||
0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G |
||||
0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G |
||||
0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G |
||||
|
||||
QSPI flash map: |
||||
Start Address End Address Description Size |
||||
0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI 1MB |
||||
0x00_4010_0000 - 0x00_401F_FFFF U-Boot 1MB |
||||
0x00_4020_0000 - 0x00_402F_FFFF U-Boot Env 1MB |
||||
0x00_4030_0000 - 0x00_403F_FFFF FMan ucode 1MB |
||||
0x00_4040_0000 - 0x00_404F_FFFF UEFI 1MB |
||||
0x00_4050_0000 - 0x00_406F_FFFF PPA 2MB |
||||
0x00_4070_0000 - 0x00_408F_FFFF Secure boot header |
||||
+ bootscript 2MB |
||||
0x00_4090_0000 - 0x00_40FF_FFFF Reserved 7MB |
||||
0x00_4100_0000 - 0x00_43FF_FFFF FIT Image 48MB |
||||
|
||||
Booting Options |
||||
--------------- |
||||
a) QSPI boot |
||||
b) SD boot |
||||
c) eMMC boot |
@ -0,0 +1,158 @@ |
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
* |
||||
* Freescale LS1046ARDB board-specific CPLD controlling supports. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <asm/io.h> |
||||
#include "cpld.h" |
||||
|
||||
u8 cpld_read(unsigned int reg) |
||||
{ |
||||
void *p = (void *)CONFIG_SYS_CPLD_BASE; |
||||
|
||||
return in_8(p + reg); |
||||
} |
||||
|
||||
void cpld_write(unsigned int reg, u8 value) |
||||
{ |
||||
void *p = (void *)CONFIG_SYS_CPLD_BASE; |
||||
|
||||
out_8(p + reg, value); |
||||
} |
||||
|
||||
/* Set the boot bank to the alternate bank */ |
||||
void cpld_set_altbank(void) |
||||
{ |
||||
u16 reg = CPLD_CFG_RCW_SRC_QSPI; |
||||
u8 reg4 = CPLD_READ(soft_mux_on); |
||||
u8 reg5 = (u8)(reg >> 1); |
||||
u8 reg6 = (u8)(reg & 1); |
||||
u8 reg7 = CPLD_READ(vbank); |
||||
|
||||
cpld_rev_bit(®5); |
||||
|
||||
CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); |
||||
|
||||
CPLD_WRITE(cfg_rcw_src1, reg5); |
||||
CPLD_WRITE(cfg_rcw_src2, reg6); |
||||
|
||||
reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK; |
||||
CPLD_WRITE(vbank, reg7); |
||||
|
||||
CPLD_WRITE(system_rst, 1); |
||||
} |
||||
|
||||
/* Set the boot bank to the default bank */ |
||||
void cpld_set_defbank(void) |
||||
{ |
||||
u16 reg = CPLD_CFG_RCW_SRC_QSPI; |
||||
u8 reg4 = CPLD_READ(soft_mux_on); |
||||
u8 reg5 = (u8)(reg >> 1); |
||||
u8 reg6 = (u8)(reg & 1); |
||||
|
||||
cpld_rev_bit(®5); |
||||
|
||||
CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); |
||||
|
||||
CPLD_WRITE(cfg_rcw_src1, reg5); |
||||
CPLD_WRITE(cfg_rcw_src2, reg6); |
||||
|
||||
CPLD_WRITE(vbank, 0); |
||||
|
||||
CPLD_WRITE(system_rst, 1); |
||||
} |
||||
|
||||
void cpld_set_sd(void) |
||||
{ |
||||
u16 reg = CPLD_CFG_RCW_SRC_SD; |
||||
u8 reg5 = (u8)(reg >> 1); |
||||
u8 reg6 = (u8)(reg & 1); |
||||
|
||||
cpld_rev_bit(®5); |
||||
|
||||
CPLD_WRITE(soft_mux_on, 1); |
||||
|
||||
CPLD_WRITE(cfg_rcw_src1, reg5); |
||||
CPLD_WRITE(cfg_rcw_src2, reg6); |
||||
|
||||
CPLD_WRITE(system_rst, 1); |
||||
} |
||||
#ifdef DEBUG |
||||
static void cpld_dump_regs(void) |
||||
{ |
||||
printf("cpld_ver = %x\n", CPLD_READ(cpld_ver)); |
||||
printf("cpld_ver_sub = %x\n", CPLD_READ(cpld_ver_sub)); |
||||
printf("pcba_ver = %x\n", CPLD_READ(pcba_ver)); |
||||
printf("soft_mux_on = %x\n", CPLD_READ(soft_mux_on)); |
||||
printf("cfg_rcw_src1 = %x\n", CPLD_READ(cfg_rcw_src1)); |
||||
printf("cfg_rcw_src2 = %x\n", CPLD_READ(cfg_rcw_src2)); |
||||
printf("vbank = %x\n", CPLD_READ(vbank)); |
||||
printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel)); |
||||
printf("uart_sel = %x\n", CPLD_READ(uart_sel)); |
||||
printf("sd1refclk_sel = %x\n", CPLD_READ(sd1refclk_sel)); |
||||
printf("rgmii_1588_sel = %x\n", CPLD_READ(rgmii_1588_sel)); |
||||
printf("1588_clk_sel = %x\n", CPLD_READ(reg_1588_clk_sel)); |
||||
printf("status_led = %x\n", CPLD_READ(status_led)); |
||||
printf("sd_emmc = %x\n", CPLD_READ(sd_emmc)); |
||||
printf("vdd_en = %x\n", CPLD_READ(vdd_en)); |
||||
printf("vdd_sel = %x\n", CPLD_READ(vdd_sel)); |
||||
putc('\n'); |
||||
} |
||||
#endif |
||||
|
||||
void cpld_rev_bit(unsigned char *value) |
||||
{ |
||||
u8 rev_val, val; |
||||
int i; |
||||
|
||||
val = *value; |
||||
rev_val = val & 1; |
||||
for (i = 1; i <= 7; i++) { |
||||
val >>= 1; |
||||
rev_val <<= 1; |
||||
rev_val |= val & 1; |
||||
} |
||||
|
||||
*value = rev_val; |
||||
} |
||||
|
||||
int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
||||
{ |
||||
int rc = 0; |
||||
|
||||
if (argc <= 1) |
||||
return cmd_usage(cmdtp); |
||||
|
||||
if (strcmp(argv[1], "reset") == 0) { |
||||
if (strcmp(argv[2], "altbank") == 0) |
||||
cpld_set_altbank(); |
||||
else if (strcmp(argv[2], "sd") == 0) |
||||
cpld_set_sd(); |
||||
else |
||||
cpld_set_defbank(); |
||||
#ifdef DEBUG |
||||
} else if (strcmp(argv[1], "dump") == 0) { |
||||
cpld_dump_regs(); |
||||
#endif |
||||
} else { |
||||
rc = cmd_usage(cmdtp); |
||||
} |
||||
|
||||
return rc; |
||||
} |
||||
|
||||
U_BOOT_CMD( |
||||
cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, |
||||
"Reset the board or alternate bank", |
||||
"reset: reset to default bank\n" |
||||
"cpld reset altbank: reset to alternate bank\n" |
||||
"cpld reset sd: reset to boot from SD card\n" |
||||
#ifdef DEBUG |
||||
"cpld dump - display the CPLD registers\n" |
||||
#endif |
||||
); |
@ -0,0 +1,49 @@ |
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CPLD_H__ |
||||
#define __CPLD_H__ |
||||
|
||||
/*
|
||||
* CPLD register set of LS1046ARDB board-specific. |
||||
* CPLD Revision: V2.1 |
||||
*/ |
||||
struct cpld_data { |
||||
u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */ |
||||
u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */ |
||||
u8 pcba_ver; /* 0x2 - PCBA Revision Register */ |
||||
u8 system_rst; /* 0x3 - system reset register */ |
||||
u8 soft_mux_on; /* 0x4 - Switch Control Enable Register */ |
||||
u8 cfg_rcw_src1; /* 0x5 - RCW Source Location POR Regsiter 1 */ |
||||
u8 cfg_rcw_src2; /* 0x6 - RCW Source Location POR Regsiter 2 */ |
||||
u8 vbank; /* 0x7 - QSPI Flash Bank Setting Register */ |
||||
u8 sysclk_sel; /* 0x8 - System clock POR Register */ |
||||
u8 uart_sel; /* 0x9 - UART1 Connection Control Register */ |
||||
u8 sd1refclk_sel; /* 0xA - */ |
||||
u8 rgmii_1588_sel; /* 0xB - */ |
||||
u8 reg_1588_clk_sel; /* 0xC - */ |
||||
u8 status_led; /* 0xD - */ |
||||
u8 global_rst; /* 0xE - */ |
||||
u8 sd_emmc; /* 0xF - SD/EMMC Interface Control Regsiter */ |
||||
u8 vdd_en; /* 0x10 - VDD Voltage Control Enable Register */ |
||||
u8 vdd_sel; /* 0x11 - VDD Voltage Control Register */ |
||||
}; |
||||
|
||||
u8 cpld_read(unsigned int reg); |
||||
void cpld_write(unsigned int reg, u8 value); |
||||
void cpld_rev_bit(unsigned char *value); |
||||
|
||||
#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) |
||||
#define CPLD_WRITE(reg, value) \ |
||||
cpld_write(offsetof(struct cpld_data, reg), value) |
||||
|
||||
/* CPLD on IFC */ |
||||
#define CPLD_SW_MUX_BANK_SEL 0x40 |
||||
#define CPLD_BANK_SEL_MASK 0x07 |
||||
#define CPLD_BANK_SEL_ALTBANK 0x04 |
||||
#define CPLD_CFG_RCW_SRC_QSPI 0x044 |
||||
#define CPLD_CFG_RCW_SRC_SD 0x040 |
||||
#endif |
@ -0,0 +1,140 @@ |
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <fsl_ddr_sdram.h> |
||||
#include <fsl_ddr_dimm_params.h> |
||||
#include "ddr.h" |
||||
#ifdef CONFIG_FSL_DEEP_SLEEP |
||||
#include <fsl_sleep.h> |
||||
#endif |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
void fsl_ddr_board_options(memctl_options_t *popts, |
||||
dimm_params_t *pdimm, |
||||
unsigned int ctrl_num) |
||||
{ |
||||
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; |
||||
ulong ddr_freq; |
||||
|
||||
if (ctrl_num > 1) { |
||||
printf("Not supported controller number %d\n", ctrl_num); |
||||
return; |
||||
} |
||||
if (!pdimm->n_ranks) |
||||
return; |
||||
|
||||
pbsp = udimms[0]; |
||||
|
||||
/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
|
||||
* freqency and n_banks specified in board_specific_parameters table. |
||||
*/ |
||||
ddr_freq = get_ddr_freq(0) / 1000000; |
||||
while (pbsp->datarate_mhz_high) { |
||||
if (pbsp->n_ranks == pdimm->n_ranks) { |
||||
if (ddr_freq <= pbsp->datarate_mhz_high) { |
||||
popts->clk_adjust = pbsp->clk_adjust; |
||||
popts->wrlvl_start = pbsp->wrlvl_start; |
||||
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
||||
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
||||
goto found; |
||||
} |
||||
pbsp_highest = pbsp; |
||||
} |
||||
pbsp++; |
||||
} |
||||
|
||||
if (pbsp_highest) { |
||||
printf("Error: board specific timing not found for %lu MT/s\n", |
||||
ddr_freq); |
||||
printf("Trying to use the highest speed (%u) parameters\n", |
||||
pbsp_highest->datarate_mhz_high); |
||||
popts->clk_adjust = pbsp_highest->clk_adjust; |
||||
popts->wrlvl_start = pbsp_highest->wrlvl_start; |
||||
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
||||
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
||||
} else { |
||||
panic("DIMM is not supported by this board"); |
||||
} |
||||
found: |
||||
debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", |
||||
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); |
||||
|
||||
popts->data_bus_width = 0; /* 64-bit data bus */ |
||||
popts->otf_burst_chop_en = 0; |
||||
popts->burst_length = DDR_BL8; |
||||
popts->bstopre = 0; /* enable auto precharge */ |
||||
|
||||
/*
|
||||
* Factors to consider for half-strength driver enable: |
||||
* - number of DIMMs installed |
||||
*/ |
||||
popts->half_strength_driver_enable = 0; |
||||
/*
|
||||
* Write leveling override |
||||
*/ |
||||
popts->wrlvl_override = 1; |
||||
popts->wrlvl_sample = 0xf; |
||||
|
||||
/*
|
||||
* Rtt and Rtt_WR override |
||||
*/ |
||||
popts->rtt_override = 0; |
||||
|
||||
/* Enable ZQ calibration */ |
||||
popts->zq_en = 1; |
||||
|
||||
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); |
||||
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | |
||||
DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2; |
||||
} |
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
phys_size_t dram_size; |
||||
|
||||
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) |
||||
return fsl_ddr_sdram_size(); |
||||
#else |
||||
puts("Initializing DDR....using SPD\n"); |
||||
|
||||
dram_size = fsl_ddr_sdram(); |
||||
#endif |
||||
|
||||
erratum_a008850_post(); |
||||
|
||||
return dram_size; |
||||
} |
||||
|
||||
void dram_init_banksize(void) |
||||
{ |
||||
/*
|
||||
* gd->arch.secure_ram tracks the location of secure memory. |
||||
* It was set as if the memory starts from 0. |
||||
* The address needs to add the offset of its bank. |
||||
*/ |
||||
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; |
||||
if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { |
||||
gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; |
||||
gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; |
||||
gd->bd->bi_dram[1].size = gd->ram_size - |
||||
CONFIG_SYS_DDR_BLOCK1_SIZE; |
||||
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE |
||||
gd->arch.secure_ram = gd->bd->bi_dram[1].start + |
||||
gd->arch.secure_ram - |
||||
CONFIG_SYS_DDR_BLOCK1_SIZE; |
||||
gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; |
||||
#endif |
||||
} else { |
||||
gd->bd->bi_dram[0].size = gd->ram_size; |
||||
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE |
||||
gd->arch.secure_ram = gd->bd->bi_dram[0].start + |
||||
gd->arch.secure_ram; |
||||
gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; |
||||
#endif |
||||
} |
||||
} |
@ -0,0 +1,44 @@ |
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __DDR_H__ |
||||
#define __DDR_H__ |
||||
|
||||
void erratum_a008850_post(void); |
||||
|
||||
struct board_specific_parameters { |
||||
u32 n_ranks; |
||||
u32 datarate_mhz_high; |
||||
u32 rank_gb; |
||||
u32 clk_adjust; |
||||
u32 wrlvl_start; |
||||
u32 wrlvl_ctl_2; |
||||
u32 wrlvl_ctl_3; |
||||
}; |
||||
|
||||
/*
|
||||
* These tables contain all valid speeds we want to override with board |
||||
* specific parameters. datarate_mhz_high values need to be in ascending order |
||||
* for each n_ranks group. |
||||
*/ |
||||
static const struct board_specific_parameters udimm0[] = { |
||||
/*
|
||||
* memory controller 0 |
||||
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
||||
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
||||
*/ |
||||
{2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, |
||||
{2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, |
||||
{2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, |
||||
{2, 2300, 0, 8, 9, 0x0A0B0C10, 0x1213140E,}, |
||||
{} |
||||
}; |
||||
|
||||
static const struct board_specific_parameters *udimms[] = { |
||||
udimm0, |
||||
}; |
||||
|
||||
#endif |
@ -0,0 +1,77 @@ |
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <netdev.h> |
||||
#include <fm_eth.h> |
||||
#include <fsl_dtsec.h> |
||||
#include <fsl_mdio.h> |
||||
#include <malloc.h> |
||||
|
||||
#include "../common/fman.h" |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
#ifdef CONFIG_FMAN_ENET |
||||
int i; |
||||
struct memac_mdio_info dtsec_mdio_info; |
||||
struct memac_mdio_info tgec_mdio_info; |
||||
struct mii_dev *dev; |
||||
u32 srds_s1; |
||||
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
||||
|
||||
srds_s1 = in_be32(&gur->rcwsr[4]) & |
||||
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; |
||||
srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; |
||||
|
||||
dtsec_mdio_info.regs = |
||||
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; |
||||
|
||||
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; |
||||
|
||||
/* Register the 1G MDIO bus */ |
||||
fm_memac_mdio_init(bis, &dtsec_mdio_info); |
||||
|
||||
tgec_mdio_info.regs = |
||||
(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; |
||||
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; |
||||
|
||||
/* Register the 10G MDIO bus */ |
||||
fm_memac_mdio_init(bis, &tgec_mdio_info); |
||||
|
||||
/* Set the two on-board RGMII PHY address */ |
||||
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); |
||||
|
||||
/* Set the two on-board SGMII PHY address */ |
||||
fm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY1_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY2_ADDR); |
||||
|
||||
/* Set the on-board AQ PHY address */ |
||||
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); |
||||
|
||||
switch (srds_s1) { |
||||
case 0x1133: |
||||
break; |
||||
default: |
||||
printf("Invalid SerDes protocol 0x%x for LS1046ARDB\n", |
||||
srds_s1); |
||||
break; |
||||
} |
||||
|
||||
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); |
||||
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) |
||||
fm_info_set_mdio(i, dev); |
||||
|
||||
/* XFI on lane A, MAC 9 */ |
||||
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); |
||||
fm_info_set_mdio(FM1_10GEC1, dev); |
||||
|
||||
cpu_eth_init(bis); |
||||
#endif |
||||
|
||||
return pci_eth_init(bis); |
||||
} |
@ -0,0 +1,136 @@ |
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <i2c.h> |
||||
#include <fdt_support.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/fsl_serdes.h> |
||||
#include <asm/arch/ppa.h> |
||||
#include <asm/arch/soc.h> |
||||
#include <hwconfig.h> |
||||
#include <ahci.h> |
||||
#include <mmc.h> |
||||
#include <scsi.h> |
||||
#include <fm_eth.h> |
||||
#include <fsl_csu.h> |
||||
#include <fsl_esdhc.h> |
||||
#include "cpld.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
static const char *freq[2] = {"100.00MHZ", "156.25MHZ"}; |
||||
u8 cfg_rcw_src1, cfg_rcw_src2; |
||||
u16 cfg_rcw_src; |
||||
u8 sd1refclk_sel; |
||||
|
||||
puts("Board: LS1046ARDB, boot from "); |
||||
|
||||
cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); |
||||
cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); |
||||
cpld_rev_bit(&cfg_rcw_src1); |
||||
cfg_rcw_src = cfg_rcw_src1; |
||||
cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; |
||||
|
||||
if (cfg_rcw_src == 0x44) |
||||
printf("QSPI vBank %d\n", CPLD_READ(vbank)); |
||||
else if (cfg_rcw_src == 0x40) |
||||
puts("SD\n"); |
||||
else |
||||
puts("Invalid setting of SW5\n"); |
||||
|
||||
printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver), |
||||
CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver)); |
||||
|
||||
puts("SERDES Reference Clocks:\n"); |
||||
sd1refclk_sel = CPLD_READ(sd1refclk_sel); |
||||
printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
gd->ram_size = initdram(0); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
fsl_lsch2_early_init_f(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; |
||||
|
||||
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS |
||||
enable_layerscape_ns_access(); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_FSL_LS_PPA |
||||
ppa_init(); |
||||
#endif |
||||
|
||||
/* invert AQR105 IRQ pins polarity */ |
||||
out_be32(&scfg->intpcr, AQR105_IRQ_MASK); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void config_board_mux(void) |
||||
{ |
||||
#ifdef CONFIG_HAS_FSL_XHCI_USB |
||||
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; |
||||
u32 usb_pwrfault; |
||||
|
||||
/* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */ |
||||
out_be32(&scfg->rcwpmuxcr0, 0x3300); |
||||
out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); |
||||
usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << |
||||
SCFG_USBPWRFAULT_USB3_SHIFT) | |
||||
(SCFG_USBPWRFAULT_DEDICATED << |
||||
SCFG_USBPWRFAULT_USB2_SHIFT) | |
||||
(SCFG_USBPWRFAULT_SHARED << |
||||
SCFG_USBPWRFAULT_USB1_SHIFT); |
||||
out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); |
||||
#endif |
||||
} |
||||
|
||||
#ifdef CONFIG_MISC_INIT_R |
||||
int misc_init_r(void) |
||||
{ |
||||
config_board_mux(); |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
int ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
u64 base[CONFIG_NR_DRAM_BANKS]; |
||||
u64 size[CONFIG_NR_DRAM_BANKS]; |
||||
|
||||
/* fixup DT for the two DDR banks */ |
||||
base[0] = gd->bd->bi_dram[0].start; |
||||
size[0] = gd->bd->bi_dram[0].size; |
||||
base[1] = gd->bd->bi_dram[1].start; |
||||
size[1] = gd->bd->bi_dram[1].size; |
||||
|
||||
fdt_fixup_memory_banks(blob, base, size, 2); |
||||
ft_cpu_setup(blob, bd); |
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN |
||||
fdt_fixup_fman_ethernet(blob); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
@ -0,0 +1,22 @@ |
||||
#Configure Scratch register |
||||
09570600 00000000 |
||||
09570604 10000000 |
||||
#Disable CCI barrier tranaction |
||||
09570178 0000e010 |
||||
09180000 00000008 |
||||
#USB PHY frequency sel |
||||
09570418 0000009e |
||||
0957041c 0000009e |
||||
09570420 0000009e |
||||
#Serdes SATA |
||||
09eb1300 80104e20 |
||||
09eb08dc 00502880 |
||||
#PEX gen3 link |
||||
09570158 00000300 |
||||
89400890 01048000 |
||||
89500890 01048000 |
||||
89600890 01048000 |
||||
#Alt base register |
||||
09570158 00001000 |
||||
#flush PBI data |
||||
096100c0 000fffff |
@ -0,0 +1,7 @@ |
||||
#PBL preamble and RCW header |
||||
aa55aa55 01ee0100 |
||||
# RCW |
||||
0c150010 0e000000 00000000 00000000 |
||||
11335559 40000012 60040000 c1000000 |
||||
00000000 00000000 00000000 00238800 |
||||
20124000 00003000 00000096 00000001 |
@ -0,0 +1,7 @@ |
||||
#PBL preamble and RCW header |
||||
aa55aa55 01ee0100 |
||||
# RCW |
||||
0c150010 0e000000 00000000 00000000 |
||||
11335559 40005012 60040000 c1000000 |
||||
00000000 00000000 00000000 00238800 |
||||
20124000 00003101 00000096 00000001 |
@ -0,0 +1,28 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_LS1046AQDS=y |
||||
CONFIG_DM_SPI=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" |
||||
CONFIG_FIT=y |
||||
CONFIG_FIT_VERBOSE=y |
||||
CONFIG_OF_BOARD_SETUP=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" |
||||
CONFIG_BOOTDELAY=10 |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_CMD_BOOTZ=y |
||||
CONFIG_CMD_GREPENV=y |
||||
CONFIG_CMD_MEMTEST=y |
||||
CONFIG_CMD_MEMINFO=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_SF=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_MII=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_EXT2=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_DM=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_SYS_NS16550=y |
||||
CONFIG_FSL_DSPI=y |
@ -0,0 +1,30 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_LS1046AQDS=y |
||||
CONFIG_DM_SPI=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" |
||||
CONFIG_SPL=y |
||||
CONFIG_FIT=y |
||||
CONFIG_FIT_VERBOSE=y |
||||
CONFIG_OF_BOARD_SETUP=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL" |
||||
CONFIG_NAND_BOOT=y |
||||
CONFIG_BOOTDELAY=10 |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_CMD_BOOTZ=y |
||||
CONFIG_CMD_GREPENV=y |
||||
CONFIG_CMD_MEMTEST=y |
||||
CONFIG_CMD_MEMINFO=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_SF=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_MII=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_EXT2=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_DM=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_SYS_NS16550=y |
||||
CONFIG_FSL_DSPI=y |
@ -0,0 +1,31 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_LS1046AQDS=y |
||||
CONFIG_DM_SPI=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" |
||||
CONFIG_FIT=y |
||||
CONFIG_FIT_VERBOSE=y |
||||
CONFIG_OF_BOARD_SETUP=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" |
||||
CONFIG_QSPI_BOOT=y |
||||
CONFIG_BOOTDELAY=10 |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_CMD_BOOTZ=y |
||||
# CONFIG_CMD_IMLS is not set |
||||
CONFIG_CMD_GREPENV=y |
||||
CONFIG_CMD_MEMTEST=y |
||||
CONFIG_CMD_MEMINFO=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_SF=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_MII=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_EXT2=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_DM=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_SYS_NS16550=y |
||||
CONFIG_FSL_DSPI=y |
||||
CONFIG_FSL_QSPI=y |
@ -0,0 +1,30 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_LS1046AQDS=y |
||||
CONFIG_DM_SPI=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" |
||||
CONFIG_SPL=y |
||||
CONFIG_FIT=y |
||||
CONFIG_FIT_VERBOSE=y |
||||
CONFIG_OF_BOARD_SETUP=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL" |
||||
CONFIG_SD_BOOT=y |
||||
CONFIG_BOOTDELAY=10 |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_CMD_BOOTZ=y |
||||
CONFIG_CMD_GREPENV=y |
||||
CONFIG_CMD_MEMTEST=y |
||||
CONFIG_CMD_MEMINFO=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_SF=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_MII=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_EXT2=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_DM=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_SYS_NS16550=y |
||||
CONFIG_FSL_DSPI=y |
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Reference in new issue