Matthias Fuchs
10 years ago
committed by
Tom Rini
parent
e434d5d729
commit
cc6e715f1b
@ -1,12 +0,0 @@ |
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if TARGET_OCRTC |
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config SYS_BOARD |
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default "ocrtc" |
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config SYS_VENDOR |
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default "esd" |
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config SYS_CONFIG_NAME |
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default "OCRTC" |
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endif |
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@ -1,6 +0,0 @@ |
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OCRTC BOARD |
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M: Matthias Fuchs <matthias.fuchs@esd-electronics.com> |
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S: Maintained |
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F: board/esd/ocrtc/ |
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F: include/configs/OCRTC.h |
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F: configs/OCRTC_defconfig |
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@ -1,8 +0,0 @@ |
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#
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# (C) Copyright 2001-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = ocrtc.o flash.o ../common/misc.o cmd_ocrtc.o
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@ -1,68 +0,0 @@ |
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/*
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* (C) Copyright 2003 |
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <pci.h> |
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#include <pci_ids.h> |
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#include <asm/4xx_pci.h> |
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#if defined(CONFIG_CMD_BSP) |
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/*
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* Set device number on pci board |
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*/ |
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int do_setdevice(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
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{ |
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int idx = 1; /* start at 1 (skip device 0) */ |
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pci_dev_t bdf = 0; |
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u32 addr; |
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while (bdf >= 0) { |
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if ((bdf = pci_find_device(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_405GP, idx++)) < 0) { |
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break; |
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} |
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printf("Found device nr %d at %x!\n", idx-1, bdf); |
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pci_read_config_dword(bdf, PCI_BASE_ADDRESS_1, &addr); |
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addr &= ~0xf; |
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*(u32 *)addr = (bdf & 0x0000f800) >> 11; |
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printf("Wrote %x at %x!\n", (bdf & 0x0000f800) >> 11, addr); |
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} |
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return 0; |
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} |
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U_BOOT_CMD( |
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setdevice, 1, 1, do_setdevice, |
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"Set device number on pci adapter boards", |
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"" |
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); |
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/*
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* Get device number on pci board |
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*/ |
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int do_getdevice(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
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{ |
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u32 device; |
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char str[32]; |
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device = *(u32 *)0x0; |
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device = 0x16 - device; /* calculate vxworks bp slot id */ |
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sprintf(str, "%d", device); |
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setenv("slot", str); |
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printf("Variabel slot set to %x\n", device); |
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return 0; |
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} |
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U_BOOT_CMD( |
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getdevice, 1, 1, do_getdevice, |
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"Get device number and set slot env variable", |
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"" |
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); |
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#endif |
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@ -1,140 +0,0 @@ |
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/*
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* (C) Copyright 2001 |
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/ppc4xx.h> |
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#include <asm/processor.h> |
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/*
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* include common flash code (for esd boards) |
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*/ |
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#include "../common/flash.c" |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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static ulong flash_get_size (vu_long * addr, flash_info_t * info); |
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static void flash_get_offsets (ulong base, flash_info_t * info); |
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init (void) |
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{ |
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unsigned long size_b0, size_b1; |
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int i; |
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uint pbcr; |
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unsigned long base_b0, base_b1; |
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int size_val = 0; |
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/* Init: no FLASHes known */ |
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for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { |
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flash_info[i].flash_id = FLASH_UNKNOWN; |
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} |
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/* Static FLASH Bank configuration here - FIXME XXX */ |
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base_b0 = FLASH_BASE0_PRELIM; |
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size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); |
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if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", |
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size_b0, size_b0 << 20); |
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} |
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base_b1 = FLASH_BASE1_PRELIM; |
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size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); |
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/* Re-do sizing to get full correct info */ |
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if (size_b1) { |
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mtdcr (EBC0_CFGADDR, PB0CR); |
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pbcr = mfdcr (EBC0_CFGDATA); |
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mtdcr (EBC0_CFGADDR, PB0CR); |
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base_b1 = -size_b1; |
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switch (size_b1) { |
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case 1 << 20: |
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size_val = 0; |
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break; |
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case 2 << 20: |
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size_val = 1; |
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break; |
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case 4 << 20: |
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size_val = 2; |
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break; |
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case 8 << 20: |
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size_val = 3; |
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break; |
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case 16 << 20: |
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size_val = 4; |
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break; |
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} |
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pbcr = (pbcr & 0x0001ffff) | base_b1 | (size_val << 17); |
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mtdcr (EBC0_CFGDATA, pbcr); |
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/* printf("PB1CR = %x\n", pbcr); */ |
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} |
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if (size_b0) { |
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mtdcr (EBC0_CFGADDR, PB1CR); |
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pbcr = mfdcr (EBC0_CFGDATA); |
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mtdcr (EBC0_CFGADDR, PB1CR); |
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base_b0 = base_b1 - size_b0; |
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switch (size_b1) { |
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case 1 << 20: |
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size_val = 0; |
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break; |
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case 2 << 20: |
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size_val = 1; |
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break; |
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case 4 << 20: |
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size_val = 2; |
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break; |
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case 8 << 20: |
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size_val = 3; |
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break; |
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case 16 << 20: |
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size_val = 4; |
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break; |
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} |
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pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); |
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mtdcr (EBC0_CFGDATA, pbcr); |
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/* printf("PB0CR = %x\n", pbcr); */ |
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} |
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size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); |
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flash_get_offsets (base_b0, &flash_info[0]); |
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/* monitor protection ON by default */ |
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flash_protect (FLAG_PROTECT_SET, |
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base_b0 + size_b0 - monitor_flash_len, |
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base_b0 + size_b0 - 1, &flash_info[0]); |
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if (size_b1) { |
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/* Re-do sizing to get full correct info */ |
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size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); |
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flash_get_offsets (base_b1, &flash_info[1]); |
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/* monitor protection ON by default */ |
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flash_protect (FLAG_PROTECT_SET, |
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base_b1 + size_b1 - monitor_flash_len, |
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base_b1 + size_b1 - 1, &flash_info[1]); |
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/* monitor protection OFF by default (one is enough) */ |
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flash_protect (FLAG_PROTECT_CLEAR, |
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base_b0 + size_b0 - monitor_flash_len, |
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base_b0 + size_b0 - 1, &flash_info[0]); |
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} else { |
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flash_info[1].flash_id = FLASH_UNKNOWN; |
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flash_info[1].sector_count = -1; |
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} |
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flash_info[0].size = size_b0; |
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flash_info[1].size = size_b1; |
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return (size_b0 + size_b1); |
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} |
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@ -1,78 +0,0 @@ |
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/*
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* (C) Copyright 2001 |
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include "ocrtc.h" |
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#include <asm/processor.h> |
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#include <i2c.h> |
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#include <command.h> |
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extern void lxt971_no_sleep(void); |
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int board_early_init_f (void) |
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{ |
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive |
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* IRQ 16 405GP internally generated; active low; level sensitive |
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* IRQ 17-24 RESERVED |
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* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive |
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* IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive |
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* IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive |
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* IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive |
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* IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive |
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* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive |
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* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive |
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*/ |
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mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
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mtdcr (UIC0ER, 0x00000000); /* disable all ints */ |
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mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ |
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mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */ |
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mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ |
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mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ |
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mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ |
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/*
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* EBC Configuration Register: clear EBTC -> high-Z ebc signals between |
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* transfers, set device-paced timeout to 256 cycles |
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*/ |
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mtebc (EBC0_CFG, 0x20400000); |
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return 0; |
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} |
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/*
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* Check Board Identity: |
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*/ |
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int checkboard (void) |
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{ |
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char str[64]; |
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int i = getenv_f("serial#", str, sizeof (str)); |
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puts ("Board: "); |
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if (i == -1) { |
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#ifdef CONFIG_OCRTC |
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puts ("### No HW ID - assuming OCRTC"); |
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#endif |
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#ifdef CONFIG_ORSG |
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puts ("### No HW ID - assuming ORSG"); |
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#endif |
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} else { |
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puts (str); |
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} |
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putc ('\n'); |
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/*
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* Disable sleep mode in LXT971 |
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*/ |
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lxt971_no_sleep(); |
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return (0); |
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} |
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@ -1,28 +0,0 @@ |
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/*
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* (C) Copyright 2001 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/****************************************************************************
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* FLASH Memory Map as used by TQ Monitor: |
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* |
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* Start Address Length |
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* +-----------------------+ 0x4000_0000 Start of Flash ----------------- |
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* | MON8xx code | 0x4000_0100 Reset Vector |
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* +-----------------------+ 0x400?_???? |
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* | (unused) | |
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* +-----------------------+ 0x4001_FF00 |
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* | Ethernet Addresses | 0x78 |
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* +-----------------------+ 0x4001_FF78 |
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* | (Reserved for MON8xx) | 0x44 |
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* +-----------------------+ 0x4001_FFBC |
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* | Lock Address | 0x04 |
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* +-----------------------+ 0x4001_FFC0 ^ |
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* | Hardware Information | 0x40 | MON8xx |
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* +=======================+ 0x4002_0000 (sector border) ----------------- |
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* | Autostart Header | | Applications |
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* | ... | v |
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* |
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*****************************************************************************/ |
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@ -1,3 +0,0 @@ |
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CONFIG_PPC=y |
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CONFIG_4xx=y |
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CONFIG_TARGET_OCRTC=y |
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@ -1,285 +0,0 @@ |
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/*
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* (C) Copyright 2001 |
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/*
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* board/config.h - configuration options, board specific |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/*
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* High Level Configuration Options |
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* (easy to change) |
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*/ |
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#define CONFIG_405GP 1 /* This is a PPC405 CPU */ |
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#define CONFIG_OCRTC 1 /* ...on a OCRTC board */ |
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#define CONFIG_SYS_TEXT_BASE 0xFFFD0000 |
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
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#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ |
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#define CONFIG_BAUDRATE 9600 |
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#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
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#undef CONFIG_BOOTARGS |
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#define CONFIG_BOOTCOMMAND "go fff00100" |
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
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#define CONFIG_PPC4xx_EMAC |
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#define CONFIG_MII 1 /* MII PHY management */ |
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#define CONFIG_PHY_ADDR 0 /* PHY address */ |
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#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
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/*
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* BOOTP options |
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*/ |
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#define CONFIG_BOOTP_BOOTFILESIZE |
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#define CONFIG_BOOTP_BOOTPATH |
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#define CONFIG_BOOTP_GATEWAY |
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#define CONFIG_BOOTP_HOSTNAME |
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/*
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* Command line configuration. |
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*/ |
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#include <config_cmd_default.h> |
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#define CONFIG_CMD_PCI |
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#define CONFIG_CMD_IRQ |
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#define CONFIG_CMD_ASKENV |
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#define CONFIG_CMD_ELF |
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#define CONFIG_CMD_BSP |
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#define CONFIG_CMD_EEPROM |
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#define CONFIG_MAC_PARTITION |
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#define CONFIG_DOS_PARTITION |
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#undef CONFIG_WATCHDOG /* watchdog disabled */ |
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#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
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/*
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* Miscellaneous configurable options |
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*/ |
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#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
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#if defined(CONFIG_CMD_KGDB) |
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
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#else |
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
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#endif |
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
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#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
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#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
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#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
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#define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
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#define CONFIG_SYS_NS16550 |
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#define CONFIG_SYS_NS16550_SERIAL |
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#define CONFIG_SYS_NS16550_REG_SIZE 1 |
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#define CONFIG_SYS_NS16550_CLK get_serial_clock() |
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#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
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#define CONFIG_SYS_BASE_BAUD 691200 |
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/* The following table includes the supported baudrates */ |
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#define CONFIG_SYS_BAUDRATE_TABLE \ |
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{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
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57600, 115200, 230400, 460800, 921600 } |
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
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#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
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/*-----------------------------------------------------------------------
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* PCI stuff |
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*----------------------------------------------------------------------- |
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*/ |
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#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
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#define PCI_HOST_FORCE 1 /* configure as pci host */ |
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
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#define CONFIG_PCI /* include pci support */ |
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#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
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#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ |
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#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
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/* resource configuration */ |
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|
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#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ |
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#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/ |
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
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#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0410 /* PCI Device ID: OCRTC */ |
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#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ |
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#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ |
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#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ |
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#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
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#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ |
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#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ |
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#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ |
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration |
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* (Set up by the startup code) |
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
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*/ |
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
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#define CONFIG_SYS_FLASH_BASE 0xFFFD0000 |
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
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#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ |
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ |
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|
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/*
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* For booting Linux, the board info and command line data |
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* have to be in the first 8 MB of memory, since this is |
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* the maximum mapped by the Linux kernel during initialization. |
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*/ |
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
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/*-----------------------------------------------------------------------
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* FLASH organization |
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*/ |
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
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|
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
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|
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#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
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#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ |
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#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ |
||||
/*
|
||||
* The following defines are added for buggy IOP480 byte interface. |
||||
* All other boards should use the standard values (CPCI405 etc.) |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
||||
#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ |
||||
#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ |
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
||||
|
||||
#if 0 /* Use NVRAM for environment variables */
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM organization |
||||
*/ |
||||
#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ |
||||
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ |
||||
#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ |
||||
#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ |
||||
#define CONFIG_ENV_ADDR \ |
||||
(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */ |
||||
#define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */ |
||||
|
||||
#else /* Use EEPROM for environment variables */ |
||||
|
||||
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
||||
#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ |
||||
#define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ |
||||
/* total size of a CAT24WC08 is 1024 bytes */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C EEPROM (CAT24WC08) for environment |
||||
*/ |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_PPC4XX |
||||
#define CONFIG_SYS_I2C_PPC4XX_CH0 |
||||
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 |
||||
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F |
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
||||
/* mask of address bits that overflow into the "EEPROM chip address" */ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ |
||||
/* 16 byte page write mode using*/ |
||||
/* last 4 bits of the address */ |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ |
||||
#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup |
||||
*/ |
||||
|
||||
/* Memory Bank 0 (Flash Bank 0) initialization */ |
||||
#define CONFIG_SYS_EBC_PB0AP 0x92015480 |
||||
#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ |
||||
|
||||
/* Memory Bank 1 (Flash Bank 1) initialization */ |
||||
#define CONFIG_SYS_EBC_PB1AP 0x92015480 |
||||
#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ |
||||
|
||||
/* Memory Bank 2 (PLD - FPGA-boot) initialization */ |
||||
#define CONFIG_SYS_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ |
||||
/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ |
||||
#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ |
||||
|
||||
/* Memory Bank 3 (PLD - OSL) initialization */ |
||||
#define CONFIG_SYS_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ |
||||
/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ |
||||
#define CONFIG_SYS_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ |
||||
|
||||
/* Memory Bank 4 (Spartan2 1) initialization */ |
||||
#define CONFIG_SYS_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ |
||||
/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ |
||||
#define CONFIG_SYS_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/ |
||||
|
||||
/* Memory Bank 5 (Spartan2 2) initialization */ |
||||
#define CONFIG_SYS_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ |
||||
/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ |
||||
#define CONFIG_SYS_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/ |
||||
|
||||
/* Memory Bank 6 (Virtex 1) initialization */ |
||||
#define CONFIG_SYS_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ |
||||
/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ |
||||
#define CONFIG_SYS_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/ |
||||
|
||||
/* Memory Bank 7 (Virtex 2) initialization */ |
||||
#define CONFIG_SYS_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ |
||||
/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ |
||||
#define CONFIG_SYS_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/ |
||||
|
||||
|
||||
#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
|
||||
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ |
||||
#define CONFIG_SYS_TEMP_STACK_OCM 1 |
||||
|
||||
/* On Chip Memory location */ |
||||
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
||||
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 |
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ |
||||
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue