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firmware: ti_sci: Add support for processor control services

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TI-SCI message protocol provides support for controlling of various
physical cores available in SoC. In order to control which host is
capable of controlling a physical processor core, there is a processor
access control list that needs to be populated as part of the board
configuration data.

Introduce support for the set of TI-SCI message protocol apis that
provide us with this capability of controlling physical cores.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
lime2-spi
Lokesh Vutla 6 years ago committed by Tom Rini
parent f369b0f26c
commit ccbc8b2fdd
3 changed files with 589 additions and 0 deletions
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  1. 371
      drivers/firmware/ti_sci.c
  2. 181
      drivers/firmware/ti_sci.h
  3. 37
      include/linux/soc/ti/ti_sci_protocol.h

371
drivers/firmware/ti_sci.c
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@ -1441,6 +1441,368 @@ static int ti_sci_cmd_core_reboot(const struct ti_sci_handle *handle)
return ret;
}
/**
* ti_sci_cmd_proc_request() - Command to request a physical processor control
* @handle: Pointer to TI SCI handle
* @proc_id: Processor ID this request is for
*
* Return: 0 if all went well, else returns appropriate error value.
*/
static int ti_sci_cmd_proc_request(const struct ti_sci_handle *handle,
u8 proc_id)
{
struct ti_sci_msg_req_proc_request req;
struct ti_sci_msg_hdr *resp;
struct ti_sci_info *info;
struct ti_sci_xfer *xfer;
int ret = 0;
if (IS_ERR(handle))
return PTR_ERR(handle);
if (!handle)
return -EINVAL;
info = handle_to_ti_sci_info(handle);
xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_PROC_REQUEST,
TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
(u32 *)&req, sizeof(req), sizeof(*resp));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
dev_err(info->dev, "Message alloc failed(%d)\n", ret);
return ret;
}
req.processor_id = proc_id;
ret = ti_sci_do_xfer(info, xfer);
if (ret) {
dev_err(info->dev, "Mbox send fail %d\n", ret);
return ret;
}
resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
if (!ti_sci_is_response_ack(resp))
ret = -ENODEV;
return ret;
}
/**
* ti_sci_cmd_proc_release() - Command to release a physical processor control
* @handle: Pointer to TI SCI handle
* @proc_id: Processor ID this request is for
*
* Return: 0 if all went well, else returns appropriate error value.
*/
static int ti_sci_cmd_proc_release(const struct ti_sci_handle *handle,
u8 proc_id)
{
struct ti_sci_msg_req_proc_release req;
struct ti_sci_msg_hdr *resp;
struct ti_sci_info *info;
struct ti_sci_xfer *xfer;
int ret = 0;
if (IS_ERR(handle))
return PTR_ERR(handle);
if (!handle)
return -EINVAL;
info = handle_to_ti_sci_info(handle);
xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_PROC_RELEASE,
TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
(u32 *)&req, sizeof(req), sizeof(*resp));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
dev_err(info->dev, "Message alloc failed(%d)\n", ret);
return ret;
}
req.processor_id = proc_id;
ret = ti_sci_do_xfer(info, xfer);
if (ret) {
dev_err(info->dev, "Mbox send fail %d\n", ret);
return ret;
}
resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
if (!ti_sci_is_response_ack(resp))
ret = -ENODEV;
return ret;
}
/**
* ti_sci_cmd_proc_handover() - Command to handover a physical processor
* control to a host in the processor's access
* control list.
* @handle: Pointer to TI SCI handle
* @proc_id: Processor ID this request is for
* @host_id: Host ID to get the control of the processor
*
* Return: 0 if all went well, else returns appropriate error value.
*/
static int ti_sci_cmd_proc_handover(const struct ti_sci_handle *handle,
u8 proc_id, u8 host_id)
{
struct ti_sci_msg_req_proc_handover req;
struct ti_sci_msg_hdr *resp;
struct ti_sci_info *info;
struct ti_sci_xfer *xfer;
int ret = 0;
if (IS_ERR(handle))
return PTR_ERR(handle);
if (!handle)
return -EINVAL;
info = handle_to_ti_sci_info(handle);
xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_PROC_HANDOVER,
TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
(u32 *)&req, sizeof(req), sizeof(*resp));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
dev_err(info->dev, "Message alloc failed(%d)\n", ret);
return ret;
}
req.processor_id = proc_id;
req.host_id = host_id;
ret = ti_sci_do_xfer(info, xfer);
if (ret) {
dev_err(info->dev, "Mbox send fail %d\n", ret);
return ret;
}
resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
if (!ti_sci_is_response_ack(resp))
ret = -ENODEV;
return ret;
}
/**
* ti_sci_cmd_set_proc_boot_cfg() - Command to set the processor boot
* configuration flags
* @handle: Pointer to TI SCI handle
* @proc_id: Processor ID this request is for
* @config_flags_set: Configuration flags to be set
* @config_flags_clear: Configuration flags to be cleared.
*
* Return: 0 if all went well, else returns appropriate error value.
*/
static int ti_sci_cmd_set_proc_boot_cfg(const struct ti_sci_handle *handle,
u8 proc_id, u64 bootvector,
u32 config_flags_set,
u32 config_flags_clear)
{
struct ti_sci_msg_req_set_proc_boot_config req;
struct ti_sci_msg_hdr *resp;
struct ti_sci_info *info;
struct ti_sci_xfer *xfer;
int ret = 0;
if (IS_ERR(handle))
return PTR_ERR(handle);
if (!handle)
return -EINVAL;
info = handle_to_ti_sci_info(handle);
xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_SET_PROC_BOOT_CONFIG,
TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
(u32 *)&req, sizeof(req), sizeof(*resp));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
dev_err(info->dev, "Message alloc failed(%d)\n", ret);
return ret;
}
req.processor_id = proc_id;
req.bootvector_low = bootvector & TISCI_ADDR_LOW_MASK;
req.bootvector_high = (bootvector & TISCI_ADDR_HIGH_MASK) >>
TISCI_ADDR_HIGH_SHIFT;
req.config_flags_set = config_flags_set;
req.config_flags_clear = config_flags_clear;
ret = ti_sci_do_xfer(info, xfer);
if (ret) {
dev_err(info->dev, "Mbox send fail %d\n", ret);
return ret;
}
resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
if (!ti_sci_is_response_ack(resp))
ret = -ENODEV;
return ret;
}
/**
* ti_sci_cmd_set_proc_boot_ctrl() - Command to set the processor boot
* control flags
* @handle: Pointer to TI SCI handle
* @proc_id: Processor ID this request is for
* @control_flags_set: Control flags to be set
* @control_flags_clear: Control flags to be cleared
*
* Return: 0 if all went well, else returns appropriate error value.
*/
static int ti_sci_cmd_set_proc_boot_ctrl(const struct ti_sci_handle *handle,
u8 proc_id, u32 control_flags_set,
u32 control_flags_clear)
{
struct ti_sci_msg_req_set_proc_boot_ctrl req;
struct ti_sci_msg_hdr *resp;
struct ti_sci_info *info;
struct ti_sci_xfer *xfer;
int ret = 0;
if (IS_ERR(handle))
return PTR_ERR(handle);
if (!handle)
return -EINVAL;
info = handle_to_ti_sci_info(handle);
xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_SET_PROC_BOOT_CTRL,
TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
(u32 *)&req, sizeof(req), sizeof(*resp));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
dev_err(info->dev, "Message alloc failed(%d)\n", ret);
return ret;
}
req.processor_id = proc_id;
req.control_flags_set = control_flags_set;
req.control_flags_clear = control_flags_clear;
ret = ti_sci_do_xfer(info, xfer);
if (ret) {
dev_err(info->dev, "Mbox send fail %d\n", ret);
return ret;
}
resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
if (!ti_sci_is_response_ack(resp))
ret = -ENODEV;
return ret;
}
/**
* ti_sci_cmd_proc_auth_boot_image() - Command to authenticate and load the
* image and then set the processor configuration flags.
* @handle: Pointer to TI SCI handle
* @proc_id: Processor ID this request is for
* @cert_addr: Memory address at which payload image certificate is located.
*
* Return: 0 if all went well, else returns appropriate error value.
*/
static int ti_sci_cmd_proc_auth_boot_image(const struct ti_sci_handle *handle,
u8 proc_id, u64 cert_addr)
{
struct ti_sci_msg_req_proc_auth_boot_image req;
struct ti_sci_msg_hdr *resp;
struct ti_sci_info *info;
struct ti_sci_xfer *xfer;
int ret = 0;
if (IS_ERR(handle))
return PTR_ERR(handle);
if (!handle)
return -EINVAL;
info = handle_to_ti_sci_info(handle);
xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_PROC_AUTH_BOOT_IMIAGE,
TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
(u32 *)&req, sizeof(req), sizeof(*resp));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
dev_err(info->dev, "Message alloc failed(%d)\n", ret);
return ret;
}
req.processor_id = proc_id;
req.cert_addr_low = cert_addr & TISCI_ADDR_LOW_MASK;
req.cert_addr_high = (cert_addr & TISCI_ADDR_HIGH_MASK) >>
TISCI_ADDR_HIGH_SHIFT;
ret = ti_sci_do_xfer(info, xfer);
if (ret) {
dev_err(info->dev, "Mbox send fail %d\n", ret);
return ret;
}
resp = (struct ti_sci_msg_hdr *)xfer->tx_message.buf;
if (!ti_sci_is_response_ack(resp))
ret = -ENODEV;
return ret;
}
/**
* ti_sci_cmd_get_proc_boot_status() - Command to get the processor boot status
* @handle: Pointer to TI SCI handle
* @proc_id: Processor ID this request is for
*
* Return: 0 if all went well, else returns appropriate error value.
*/
static int ti_sci_cmd_get_proc_boot_status(const struct ti_sci_handle *handle,
u8 proc_id, u64 *bv, u32 *cfg_flags,
u32 *ctrl_flags, u32 *sts_flags)
{
struct ti_sci_msg_resp_get_proc_boot_status *resp;
struct ti_sci_msg_req_get_proc_boot_status req;
struct ti_sci_info *info;
struct ti_sci_xfer *xfer;
int ret = 0;
if (IS_ERR(handle))
return PTR_ERR(handle);
if (!handle)
return -EINVAL;
info = handle_to_ti_sci_info(handle);
xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_GET_PROC_BOOT_STATUS,
TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
(u32 *)&req, sizeof(req), sizeof(*resp));
if (IS_ERR(xfer)) {
ret = PTR_ERR(xfer);
dev_err(info->dev, "Message alloc failed(%d)\n", ret);
return ret;
}
req.processor_id = proc_id;
ret = ti_sci_do_xfer(info, xfer);
if (ret) {
dev_err(info->dev, "Mbox send fail %d\n", ret);
return ret;
}
resp = (struct ti_sci_msg_resp_get_proc_boot_status *)
xfer->tx_message.buf;
if (!ti_sci_is_response_ack(resp))
return -ENODEV;
*bv = (resp->bootvector_low & TISCI_ADDR_LOW_MASK) |
(((u64)resp->bootvector_high <<
TISCI_ADDR_HIGH_SHIFT) & TISCI_ADDR_HIGH_MASK);
*cfg_flags = resp->config_flags;
*ctrl_flags = resp->control_flags;
*sts_flags = resp->status_flags;
return ret;
}
/*
* ti_sci_setup_ops() - Setup the operations structures
* @info: pointer to TISCI pointer
@ -1452,6 +1814,7 @@ static void ti_sci_setup_ops(struct ti_sci_info *info)
struct ti_sci_dev_ops *dops = &ops->dev_ops;
struct ti_sci_clk_ops *cops = &ops->clk_ops;
struct ti_sci_core_ops *core_ops = &ops->core_ops;
struct ti_sci_proc_ops *pops = &ops->proc_ops;
bops->board_config = ti_sci_cmd_set_board_config;
bops->board_config_rm = ti_sci_cmd_set_board_config_rm;
@ -1486,6 +1849,14 @@ static void ti_sci_setup_ops(struct ti_sci_info *info)
cops->get_freq = ti_sci_cmd_clk_get_freq;
core_ops->reboot_device = ti_sci_cmd_core_reboot;
pops->proc_request = ti_sci_cmd_proc_request;
pops->proc_release = ti_sci_cmd_proc_release;
pops->proc_handover = ti_sci_cmd_proc_handover;
pops->set_proc_boot_cfg = ti_sci_cmd_set_proc_boot_cfg;
pops->set_proc_boot_ctrl = ti_sci_cmd_set_proc_boot_ctrl;
pops->proc_auth_boot_image = ti_sci_cmd_proc_auth_boot_image;
pops->get_proc_boot_status = ti_sci_cmd_get_proc_boot_status;
}
/**

181
drivers/firmware/ti_sci.h
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@ -41,6 +41,15 @@
#define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d
#define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e
/* Processor Control Messages */
#define TISCI_MSG_PROC_REQUEST 0xc000
#define TISCI_MSG_PROC_RELEASE 0xc001
#define TISCI_MSG_PROC_HANDOVER 0xc005
#define TISCI_MSG_SET_PROC_BOOT_CONFIG 0xc100
#define TISCI_MSG_SET_PROC_BOOT_CTRL 0xc101
#define TISCI_MSG_PROC_AUTH_BOOT_IMIAGE 0xc120
#define TISCI_MSG_GET_PROC_BOOT_STATUS 0xc400
/**
* struct ti_sci_msg_hdr - Generic Message Header for All messages and responses
* @type: Type of messages: One of TI_SCI_MSG* values
@ -496,4 +505,176 @@ struct ti_sci_msg_resp_get_clock_freq {
u64 freq_hz;
} __packed;
#define TISCI_ADDR_LOW_MASK GENMASK_ULL(31, 0)
#define TISCI_ADDR_HIGH_MASK GENMASK_ULL(63, 32)
#define TISCI_ADDR_HIGH_SHIFT 32
/**
* struct ti_sci_msg_req_proc_request - Request a processor
*
* @hdr: Generic Header
* @processor_id: ID of processor
*
* Request type is TISCI_MSG_PROC_REQUEST, response is a generic ACK/NACK
* message.
*/
struct ti_sci_msg_req_proc_request {
struct ti_sci_msg_hdr hdr;
u8 processor_id;
} __packed;
/**
* struct ti_sci_msg_req_proc_release - Release a processor
*
* @hdr: Generic Header
* @processor_id: ID of processor
*
* Request type is TISCI_MSG_PROC_RELEASE, response is a generic ACK/NACK
* message.
*/
struct ti_sci_msg_req_proc_release {
struct ti_sci_msg_hdr hdr;
u8 processor_id;
} __packed;
/**
* struct ti_sci_msg_req_proc_handover - Handover a processor to a host
*
* @hdr: Generic Header
* @processor_id: ID of processor
* @host_id: New Host we want to give control to
*
* Request type is TISCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK
* message.
*/
struct ti_sci_msg_req_proc_handover {
struct ti_sci_msg_hdr hdr;
u8 processor_id;
u8 host_id;
} __packed;
/* A53 Config Flags */
#define PROC_BOOT_CFG_FLAG_ARMV8_DBG_EN 0x00000001
#define PROC_BOOT_CFG_FLAG_ARMV8_DBG_NIDEN 0x00000002
#define PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPIDEN 0x00000004
#define PROC_BOOT_CFG_FLAG_ARMV8_DBG_SPNIDEN 0x00000008
#define PROC_BOOT_CFG_FLAG_ARMV8_AARCH32 0x00000100
/* R5 Config Flags */
#define PROC_BOOT_CFG_FLAG_R5_DBG_EN 0x00000001
#define PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN 0x00000002
#define PROC_BOOT_CFG_FLAG_R5_LOCKSTEP 0x00000100
#define PROC_BOOT_CFG_FLAG_R5_TEINIT 0x00000200
#define PROC_BOOT_CFG_FLAG_R5_NMFI_EN 0x00000400
#define PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE 0x00000800
#define PROC_BOOT_CFG_FLAG_R5_BTCM_EN 0x00001000
#define PROC_BOOT_CFG_FLAG_R5_ATCM_EN 0x00002000
/**
* struct ti_sci_msg_req_set_proc_boot_config - Set Processor boot configuration
* @hdr: Generic Header
* @processor_id: ID of processor
* @bootvector_low: Lower 32bit (Little Endian) of boot vector
* @bootvector_high: Higher 32bit (Little Endian) of boot vector
* @config_flags_set: Optional Processor specific Config Flags to set.
* Setting a bit here implies required bit sets to 1.
* @config_flags_clear: Optional Processor specific Config Flags to clear.
* Setting a bit here implies required bit gets cleared.
*
* Request type is TISCI_MSG_SET_PROC_BOOT_CONFIG, response is a generic
* ACK/NACK message.
*/
struct ti_sci_msg_req_set_proc_boot_config {
struct ti_sci_msg_hdr hdr;
u8 processor_id;
u32 bootvector_low;
u32 bootvector_high;
u32 config_flags_set;
u32 config_flags_clear;
} __packed;
/* R5 Control Flags */
#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001
/**
* struct ti_sci_msg_req_set_proc_boot_ctrl - Set Processor boot control flags
* @hdr: Generic Header
* @processor_id: ID of processor
* @control_flags_set: Optional Processor specific Control Flags to set.
* Setting a bit here implies required bit sets to 1.
* @control_flags_clear:Optional Processor specific Control Flags to clear.
* Setting a bit here implies required bit gets cleared.
*
* Request type is TISCI_MSG_SET_PROC_BOOT_CTRL, response is a generic ACK/NACK
* message.
*/
struct ti_sci_msg_req_set_proc_boot_ctrl {
struct ti_sci_msg_hdr hdr;
u8 processor_id;
u32 control_flags_set;
u32 control_flags_clear;
} __packed;
/**
* struct ti_sci_msg_req_proc_auth_start_image - Authenticate and start image
* @hdr: Generic Header
* @processor_id: ID of processor
* @cert_addr_low: Lower 32bit (Little Endian) of certificate
* @cert_addr_high: Higher 32bit (Little Endian) of certificate
*
* Request type is TISCI_MSG_PROC_AUTH_BOOT_IMAGE, response is a generic
* ACK/NACK message.
*/
struct ti_sci_msg_req_proc_auth_boot_image {
struct ti_sci_msg_hdr hdr;
u8 processor_id;
u32 cert_addr_low;
u32 cert_addr_high;
} __packed;
/**
* struct ti_sci_msg_req_get_proc_boot_status - Get processor boot status
* @hdr: Generic Header
* @processor_id: ID of processor
*
* Request type is TISCI_MSG_GET_PROC_BOOT_STATUS, response is appropriate
* message, or NACK in case of inability to satisfy request.
*/
struct ti_sci_msg_req_get_proc_boot_status {
struct ti_sci_msg_hdr hdr;
u8 processor_id;
} __packed;
/* ARMv8 Status Flags */
#define PROC_BOOT_STATUS_FLAG_ARMV8_WFE 0x00000001
#define PROC_BOOT_STATUS_FLAG_ARMV8_WFI 0x00000002
/* R5 Status Flags */
#define PROC_BOOT_STATUS_FLAG_R5_WFE 0x00000001
#define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002
#define PROC_BOOT_STATUS_FLAG_R5_CLK_GATED 0x00000004
#define PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED 0x00000100
/**
* struct ti_sci_msg_resp_get_proc_boot_status - Processor boot status response
* @hdr: Generic Header
* @processor_id: ID of processor
* @bootvector_low: Lower 32bit (Little Endian) of boot vector
* @bootvector_high: Higher 32bit (Little Endian) of boot vector
* @config_flags: Optional Processor specific Config Flags set.
* @control_flags: Optional Processor specific Control Flags.
* @status_flags: Optional Processor specific Status Flags set.
*
* Response to TISCI_MSG_GET_PROC_BOOT_STATUS.
*/
struct ti_sci_msg_resp_get_proc_boot_status {
struct ti_sci_msg_hdr hdr;
u8 processor_id;
u32 bootvector_low;
u32 bootvector_high;
u32 config_flags;
u32 control_flags;
u32 status_flags;
} __packed;
#endif /* __TI_SCI_H */

37
include/linux/soc/ti/ti_sci_protocol.h
Unescape View File

@ -223,17 +223,54 @@ struct ti_sci_core_ops {
};
/**
* struct ti_sci_proc_ops - Processor specific operations.
*
* @proc_request: Request for controlling a physical processor.
* The requesting host should be in the processor access list.
* @proc_release: Relinquish a physical processor control
* @proc_handover: Handover a physical processor control to another host
* in the permitted list.
* @set_proc_boot_cfg: Base configuration of the processor
* @set_proc_boot_ctrl: Setup limited control flags in specific cases.
* @proc_auth_boot_image:
* @get_proc_boot_status: Get the state of physical processor
*
* NOTE: for all these functions, the following parameters are generic in
* nature:
* -handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
* -pid: Processor ID
*
*/
struct ti_sci_proc_ops {
int (*proc_request)(const struct ti_sci_handle *handle, u8 pid);
int (*proc_release)(const struct ti_sci_handle *handle, u8 pid);
int (*proc_handover)(const struct ti_sci_handle *handle, u8 pid,
u8 hid);
int (*set_proc_boot_cfg)(const struct ti_sci_handle *handle, u8 pid,
u64 bv, u32 cfg_set, u32 cfg_clr);
int (*set_proc_boot_ctrl)(const struct ti_sci_handle *handle, u8 pid,
u32 ctrl_set, u32 ctrl_clr);
int (*proc_auth_boot_image)(const struct ti_sci_handle *handle, u8 pid,
u64 caddr);
int (*get_proc_boot_status)(const struct ti_sci_handle *handle, u8 pid,
u64 *bv, u32 *cfg_flags, u32 *ctrl_flags,
u32 *sts_flags);
};
/**
* struct ti_sci_ops - Function support for TI SCI
* @board_ops: Miscellaneous operations
* @dev_ops: Device specific operations
* @clk_ops: Clock specific operations
* @core_ops: Core specific operations
* @proc_ops: Processor specific operations
*/
struct ti_sci_ops {
struct ti_sci_board_ops board_ops;
struct ti_sci_dev_ops dev_ops;
struct ti_sci_clk_ops clk_ops;
struct ti_sci_core_ops core_ops;
struct ti_sci_proc_ops proc_ops;
};
/**

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