Fix buffer overflow in common/usb.c * Patch by Tolunay Orkun, 10 Feb 2004: Add support for Cogent CSB272 board * Code cleanupmaster
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#
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# (C) Copyright 2000-2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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#OBJS = $(BOARD).o flash.o
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#OBJS = $(BOARD).o strataflash.o
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OBJS = $(BOARD).o
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SOBJS = init.o
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $^
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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sinclude .depend |
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#########################################################################
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@ -0,0 +1,36 @@ |
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#
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# (C) Copyright 2000-2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2004
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# Tolunay Orkun, NextIO Inc., torkun@nextio.com.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# Cogent CSB272 board
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#
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LDFLAGS += $(LINKER_UNDEFS)
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TEXT_BASE := 0xFFFC0000
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#TEXT_BASE := 0x00100000
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PLATFORM_RELFLAGS := $(PLATFORM_RELFLAGS)
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/*
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* (C) Copyright 2004 |
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* Tolunay Orkun, Nextio Inc., torkun@nextio.com |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <asm/u-boot.h> |
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#include <asm/processor.h> |
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#include <common.h> |
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#include <i2c.h> |
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#include <miiphy.h> |
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#include <405gp_enet.h> |
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/*
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* Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator |
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* |
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* CLKA output => Epson LCD Controller |
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* CLKB output => Not Connected |
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* CLKC output => Ethernet |
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* CLKD output => UART external clock |
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* |
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* Note: these values are obtained from device after init by micromonitor |
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*/ |
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uchar pll_fs6377_regs[16] = { |
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0x28, 0xef, 0x53, 0x03, 0x4b, 0x80, 0x32, 0x80, |
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0x94, 0x32, 0x80, 0xd4, 0x56, 0xf6, 0xf6, 0xe0 }; |
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/*
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* pll_init: Initialize AMIS IC FS6377-01 PLL |
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* |
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* PLL supplies Epson LCD Clock, Ethernet Clock and UART external clock |
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* |
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*/ |
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int pll_init(void) |
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{ |
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i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); |
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return i2c_write(CFG_I2C_PLL_ADDR, 0, 1, |
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(uchar *) pll_fs6377_regs, sizeof(pll_fs6377_regs)); |
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} |
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/*
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* board_pre_init: do any preliminary board initialization |
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* |
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*/ |
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int board_pre_init(void) |
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{ |
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/* initialize PLL so UART, LCD, Ethernet clocked at correctly */ |
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(void) get_clocks(); |
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pll_init(); |
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/*-------------------------------------------------------------------------+
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| Interrupt controller setup for the Walnut board. |
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| Note: IRQ 0-15 405GP internally generated; active high; level sensitive |
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| IRQ 16 405GP internally generated; active low; level sensitive |
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| IRQ 17-24 RESERVED |
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| IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive |
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| IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive |
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| IRQ 27 (EXT IRQ 2) Not Used |
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| IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive |
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| IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive |
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| IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive |
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| IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive |
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| Note for Walnut board: |
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| An interrupt taken for the FPGA (IRQ 25) indicates that either |
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| the Mouse, Keyboard, IRDA, or External Expansion caused the |
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| interrupt. The FPGA must be read to determine which device |
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| caused the interrupt. The default setting of the FPGA clears |
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| |
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+-------------------------------------------------------------------------*/ |
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mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ |
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mtdcr (uicer, 0x00000000); /* disable all ints */ |
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mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ |
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mtdcr (uicpr, 0xFFFFFF83); /* set int polarities */ |
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mtdcr (uictr, 0x10000000); /* set int trigger levels */ |
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mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ |
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mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ |
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mtebc (epcr, 0xa8400000); /* EBC always driven */ |
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return 0; /* success */ |
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} |
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/*
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* checkboard: identify/verify the board we are running |
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* |
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* Remark: we just assume it is correct board here! |
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* |
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*/ |
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int checkboard(void) |
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{ |
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printf("BOARD: Cogent CSB272\n"); |
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return 0; /* success */ |
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} |
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/*
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* initram: Determine the size of mounted DRAM |
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* |
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* Size is determined by reading SDRAM configuration registers as |
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* configured by initialization code |
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* |
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*/ |
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long initdram (int board_type) |
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{ |
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ulong tot_size; |
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ulong bank_size; |
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ulong tmp; |
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tot_size = 0; |
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mtdcr (memcfga, mem_mb0cf); |
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tmp = mfdcr (memcfgd); |
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if (tmp & 0x00000001) { |
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bank_size = 0x00400000 << ((tmp >> 17) & 0x7); |
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tot_size += bank_size; |
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} |
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mtdcr (memcfga, mem_mb1cf); |
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tmp = mfdcr (memcfgd); |
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if (tmp & 0x00000001) { |
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bank_size = 0x00400000 << ((tmp >> 17) & 0x7); |
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tot_size += bank_size; |
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} |
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mtdcr (memcfga, mem_mb2cf); |
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tmp = mfdcr (memcfgd); |
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if (tmp & 0x00000001) { |
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bank_size = 0x00400000 << ((tmp >> 17) & 0x7); |
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tot_size += bank_size; |
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} |
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mtdcr (memcfga, mem_mb3cf); |
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tmp = mfdcr (memcfgd); |
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if (tmp & 0x00000001) { |
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bank_size = 0x00400000 << ((tmp >> 17) & 0x7); |
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tot_size += bank_size; |
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} |
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return tot_size; |
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} |
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/*
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* last_stage_init: final configurations (such as PHY etc) |
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* |
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*/ |
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int last_stage_init(void) |
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{ |
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/* initialize the PHY */ |
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miiphy_reset(CONFIG_PHY_ADDR); |
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miiphy_write(CONFIG_PHY_ADDR, PHY_BMCR, |
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PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); /* AUTO neg */ |
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miiphy_write(CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08); /* LEDs */ |
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return 0; /* success */ |
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} |
@ -0,0 +1,216 @@ |
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/****************************************************************************** |
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* |
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* This source code has been made available to you by IBM on an AS-IS |
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* basis. Anyone receiving this source is licensed under IBM |
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* copyrights to use it in any way he or she deems fit, including |
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* copying it, modifying it, compiling it, and redistributing it either |
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* with or without modifications. No license under IBM patents or |
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* patent applications is to be implied by the copyright license. |
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* |
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* Any user of this software should understand that IBM cannot provide |
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* technical support for this software and will not be responsible for |
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* any consequences resulting from the use of this software. |
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* |
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* Any person who transfers this source code or any derivative work |
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* must include the IBM copyright notice, this paragraph, and the |
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* preceding two paragraphs in the transferred software. |
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* |
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* COPYRIGHT I B M CORPORATION 1995 |
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* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M |
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* |
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*****************************************************************************/ |
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#include <config.h> |
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#include <ppc4xx.h> |
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#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ |
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#include <ppc_asm.tmpl> |
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#include <ppc_defs.h> |
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#include <asm/cache.h> |
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#include <asm/mmu.h> |
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#define LI32(reg,val) \ |
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addis reg,0,val@h;\
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ori reg,reg,val@l
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#define WDCR_EBC(reg,val) \ |
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addi r4,0,reg;\
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mtdcr ebccfga,r4;\
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addis r4,0,val@h;\
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ori r4,r4,val@l;\
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mtdcr ebccfgd,r4 |
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#define WDCR_SDRAM(reg,val) \ |
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addi r4,0,reg;\
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mtdcr memcfga,r4;\
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addis r4,0,val@h;\
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ori r4,r4,val@l;\
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mtdcr memcfgd,r4 |
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/****************************************************************************** |
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* Function: ext_bus_cntlr_init |
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* |
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* Description: Configures EBC Controller and a few basic chip selects. |
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* |
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* CS0 is setup to get the Boot Flash out of the addresss range |
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* so that we may setup a stack. CS7 is setup so that we can |
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* access and reset the hardware watchdog. |
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* |
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* IMPORTANT: For pass1 this code must run from |
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* cache since you can not reliably change a peripheral banks |
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* timing register (pbxap) while running code from that bank. |
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* For ex., since we are running from ROM on bank 0, we can NOT |
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* execute the code that modifies bank 0 timings from ROM, so |
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* we run it from cache. |
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* |
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* Notes: Does NOT use the stack. |
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*****************************************************************************/ |
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.section ".text" |
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.align 2
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.globl ext_bus_cntlr_init
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.type ext_bus_cntlr_init, @function
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ext_bus_cntlr_init: |
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mflr r0 |
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/******************************************************************** |
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* Prefetch entire ext_bus_cntrl_init function into the icache. |
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* This is necessary because we are going to change the same CS we |
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* are executing from. Otherwise a CPU lockup may occur. |
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*******************************************************************/ |
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bl ..getAddr |
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..getAddr: |
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mflr r3 /* get address of ..getAddr */ |
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/* Calculate number of cache lines for this function */ |
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addi r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2) |
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mtctr r4 |
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..ebcloop: |
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icbt r0, r3 /* prefetch cache line for addr in r3*/ |
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addi r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */ |
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bdnz ..ebcloop /* continue for $CTR cache lines */ |
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/******************************************************************** |
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* Delay to ensure all accesses to ROM are complete before changing |
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* bank 0 timings. 200usec should be enough. |
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* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles. |
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*******************************************************************/ |
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addis r3, 0, 0x0 |
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ori r3, r3, 0xA000 /* wait 200us from reset */ |
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mtctr r3 |
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..spinlp: |
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bdnz ..spinlp /* spin loop */ |
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/******************************************************************** |
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* SETUP CPC0_CR0 |
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*******************************************************************/ |
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LI32(r4, 0x007000c0) |
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mtdcr cntrl0, r4 |
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/******************************************************************** |
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* Setup CPC0_CR1: Change PCIINT signal to PerWE |
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*******************************************************************/ |
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mfdcr r4, cntrl1 |
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ori r4, r4, 0x4000 |
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mtdcr cntrl1, r4 |
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/******************************************************************** |
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* Setup External Bus Controller (EBC). |
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*******************************************************************/ |
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WDCR_EBC(epcr, 0xd84c0000) |
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/******************************************************************** |
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* Memory Bank 0 (Intel 28F128J3 Flash) initialization |
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*******************************************************************/ |
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/*WDCR_EBC(pb0ap, 0x02869200)*/ |
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WDCR_EBC(pb0ap, 0x07869200) |
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WDCR_EBC(pb0cr, 0xfe0bc000) |
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/******************************************************************** |
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* Memory Bank 1 (Holtek HT6542B PS/2) initialization |
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*******************************************************************/ |
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WDCR_EBC(pb1ap, 0x1f869200) |
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WDCR_EBC(pb1cr, 0xf0818000) |
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/******************************************************************** |
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* Memory Bank 2 (Epson S1D13506) initialization |
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*******************************************************************/ |
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WDCR_EBC(pb2ap, 0x05860300) |
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WDCR_EBC(pb2cr, 0xf045a000) |
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/******************************************************************** |
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* Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization |
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*******************************************************************/ |
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WDCR_EBC(pb3ap, 0x0387d200) |
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WDCR_EBC(pb3cr, 0xf021c000) |
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/******************************************************************** |
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* Memory Bank 4-7 (Unused) initialization |
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*******************************************************************/ |
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WDCR_EBC(pb4ap, 0) |
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WDCR_EBC(pb4cr, 0) |
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WDCR_EBC(pb5ap, 0) |
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WDCR_EBC(pb5cr, 0) |
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WDCR_EBC(pb6ap, 0) |
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WDCR_EBC(pb6cr, 0) |
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WDCR_EBC(pb7ap, 0) |
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WDCR_EBC(pb7cr, 0) |
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/* We are all done */ |
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mtlr r0 /* Restore link register */ |
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blr /* Return to calling function */ |
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.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init |
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/* end ext_bus_cntlr_init() */ |
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/****************************************************************************** |
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* Function: sdram_init |
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* |
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* Description: Configures SDRAM memory banks. |
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* |
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* Notes: Does NOT use the stack. |
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*****************************************************************************/ |
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.section ".text" |
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.align 2
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.globl sdram_init
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.type sdram_init, @function
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sdram_init: |
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/* |
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* Disable memory controller to allow |
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* values to be changed. |
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*/ |
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WDCR_SDRAM(mem_mcopt1, 0x00000000) |
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/* |
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* Configure Memory Banks |
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*/ |
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WDCR_SDRAM(mem_mb0cf, 0x00084001) |
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WDCR_SDRAM(mem_mb1cf, 0x00000000) |
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WDCR_SDRAM(mem_mb2cf, 0x00000000) |
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WDCR_SDRAM(mem_mb3cf, 0x00000000) |
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/* |
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* Set up SDTR1 (SDRAM Timing Register) |
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*/ |
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WDCR_SDRAM(mem_sdtr1, 0x00854009) |
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/* |
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* Set RTR (Refresh Timing Register) |
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*/ |
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WDCR_SDRAM(mem_rtr, 0x10000000) |
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/* WDCR_SDRAM(mem_rtr, 0x05f00000) */ |
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/******************************************************************** |
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* Delay to ensure 200usec have elapsed since reset. Assume worst |
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* case that the core is running 200Mhz: |
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* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles |
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*******************************************************************/ |
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addis r3, 0, 0x0000 |
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ori r3, r3, 0xA000 /* Wait >200us from reset */ |
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mtctr r3 |
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..spinlp2: |
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bdnz ..spinlp2 /* spin loop */ |
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/******************************************************************** |
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* Set memory controller options reg, MCOPT1. |
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*******************************************************************/ |
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WDCR_SDRAM(mem_mcopt1,0x80800000) |
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..sdri_done: |
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blr /* Return to calling function */ |
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.Lfe1: .size sdram_init,.Lfe1-sdram_init |
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/* end sdram_init() */ |
@ -0,0 +1,151 @@ |
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/* |
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* (C) Copyright 2000-2004 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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OUTPUT_ARCH(powerpc) |
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SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
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/* Do we need any of these for elf? |
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__DYNAMIC = 0; */ |
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SECTIONS |
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{ |
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.resetvec 0xFFFFFFFC : |
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{ |
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*(.resetvec) |
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} = 0xffff |
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||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/ppc4xx/start.o (.text) |
||||
board/csb272/init.o (.text) |
||||
cpu/ppc4xx/kgdb.o (.text) |
||||
cpu/ppc4xx/traps.o (.text) |
||||
cpu/ppc4xx/interrupts.o (.text) |
||||
cpu/ppc4xx/serial.o (.text) |
||||
cpu/ppc4xx/cpu_init.o (.text) |
||||
cpu/ppc4xx/speed.o (.text) |
||||
cpu/ppc4xx/405gp_enet.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
|
||||
lib_ppc/extable.o (.text) |
||||
lib_ppc/board.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
/* . = env_offset;*/ |
||||
/* common/environment.o(.text)*/ |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -0,0 +1,313 @@ |
||||
/*
|
||||
* (C) Copyright 2004 |
||||
* Tolunay Orkun, Nextio Inc., torkun@nextio.com |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ |
||||
#define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
||||
#define CONFIG_CSB272 1 /* on a Cogent CSB272 board */ |
||||
#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init() */ |
||||
#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */ |
||||
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ |
||||
|
||||
/*
|
||||
* OS Bootstrap configuration |
||||
* |
||||
*/ |
||||
|
||||
#if 0 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after X seconds */ |
||||
#endif |
||||
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress when bootdelay = 0 */ |
||||
|
||||
#if 1 |
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"setenv bootargs console=ttyS0,38400 debug " \
|
||||
"root=/dev/ram rw ramdisk_size=4096 " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
|
||||
"bootm fe000000 fe100000" |
||||
#endif |
||||
|
||||
#if 0 |
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"bootp; " \
|
||||
"setenv bootargs console=ttyS0,38400 debug " \
|
||||
"root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
|
||||
"bootm" |
||||
#endif |
||||
|
||||
/*
|
||||
* BOOTP/DHCP protocol configuration |
||||
* |
||||
*/ |
||||
#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \ |
||||
CONFIG_BOOTP_DNS2 | \
|
||||
CONFIG_BOOTP_BOOTFILESIZE ) |
||||
/*
|
||||
* U-Boot Monitor Command Line Functions Configuration |
||||
* |
||||
*/ |
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ |
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_BEDBUG | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_DHCP ) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Serial download configuration |
||||
* |
||||
*/ |
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
/*
|
||||
* KGDB Configuration |
||||
* |
||||
*/ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
* |
||||
*/ |
||||
#undef CFG_HUSH_PARSER /* use "hush" command parser */ |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " /* hush shell secondary prompt */ |
||||
#endif |
||||
|
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ |
||||
#define CFG_EXTBDINFO 1 /* To use extended board_info (bd_t) */ |
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*
|
||||
* watchdog configuration |
||||
* |
||||
*/ |
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* UART configuration |
||||
* |
||||
*/ |
||||
#define CFG_EXT_SERIAL_CLOCK 3868400 /* use external serial clock */ |
||||
#undef CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ |
||||
#undef CFG_BASE_BAUD |
||||
#define CONFIG_BAUDRATE 38400 /* Default baud rate */ |
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 } |
||||
|
||||
/*
|
||||
* I2C configuration |
||||
* |
||||
*/ |
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#define CFG_I2C_SPEED 100000 /* I2C speed */ |
||||
#define CFG_I2C_SLAVE 0x7F /* I2C slave address */ |
||||
|
||||
/*
|
||||
* MII PHY configuration |
||||
* |
||||
*/ |
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_PHY_ADDR 0 /* PHY address */ |
||||
#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ |
||||
/* 32usec min. for LXT971A */ |
||||
#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ |
||||
|
||||
/*
|
||||
* RTC configuration |
||||
* |
||||
* Note that DS1307 RTC is limited to 100Khz I2C bus. |
||||
* |
||||
*/ |
||||
#define CONFIG_RTC_DS1307 /* Use Dallas 1307 RTC */ |
||||
|
||||
/*
|
||||
* PCI stuff |
||||
* |
||||
*/ |
||||
#define CONFIG_PCI /* include pci support */ |
||||
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ |
||||
#define PCI_HOST_FORCE 1 /* configure as pci host */ |
||||
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
||||
|
||||
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
/* resource configuration */ |
||||
#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ |
||||
#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ |
||||
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ |
||||
#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ |
||||
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ |
||||
#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ |
||||
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
||||
#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ |
||||
#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ |
||||
#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ |
||||
|
||||
/*
|
||||
* IDE stuff |
||||
* |
||||
*/ |
||||
#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */ |
||||
#undef CONFIG_IDE_LED /* no led for ide supported */ |
||||
#undef CONFIG_IDE_RESET /* no reset for ide supported */ |
||||
|
||||
/*
|
||||
* Environment configuration |
||||
* |
||||
*/ |
||||
#define CFG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */ |
||||
#undef CFG_ENV_IS_IN_NVRAM |
||||
#undef CFG_ENV_IS_IN_EEPROM |
||||
|
||||
/*
|
||||
* General Memory organization |
||||
* |
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0xFE000000 |
||||
#define CFG_FLASH_SIZE 0x02000000 |
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */ |
||||
|
||||
#if CFG_MONITOR_BASE < CFG_FLASH_BASE |
||||
#define CFG_RAMSTART |
||||
#endif |
||||
|
||||
#if defined(CFG_ENV_IS_IN_FLASH) |
||||
#define CFG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */ |
||||
#define CFG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */ |
||||
#define CFG_ENV_SIZE 0x00001000 /* Size of Environment */ |
||||
#define CFG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */ |
||||
#endif |
||||
|
||||
/*
|
||||
* FLASH Device configuration |
||||
* |
||||
*/ |
||||
#define CFG_FLASH_CFI 1 /* flash is CFI conformant */ |
||||
#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */ |
||||
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */ |
||||
#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ |
||||
#define CFG_MAX_FLASH_SECT 128 /* max # of sectors on one chip */ |
||||
#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */ |
||||
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } |
||||
|
||||
/*
|
||||
* On Chip Memory location/size |
||||
* |
||||
*/ |
||||
#define CFG_OCM_DATA_ADDR 0xF8000000 |
||||
#define CFG_OCM_DATA_SIZE 0x1000 |
||||
|
||||
/*
|
||||
* Global info and initial stack |
||||
* |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of on-chip SRAM */ |
||||
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* byte size reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*
|
||||
* Cache configuration |
||||
* |
||||
*/ |
||||
#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ |
||||
/* have only 8kB, 16kB is save here */ |
||||
#define CFG_CACHELINE_SIZE 32 |
||||
|
||||
/*
|
||||
* Miscellaneous board specific definitions |
||||
* |
||||
*/ |
||||
#define CFG_I2C_PLL_ADDR 0x58 /* I2C address of AMIS FS6377-01 PLL */ |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
* |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue