zynq: nand: Runtime detection of nand buswidth through slcr

This patch adds support to check the buswidth on nand flash
at runtime based on nand MIO configurations done by FSBL.

User needs to correctly configure the MIO's based on the
buswidth supported by the nand flash which is present on the board.

Added nand8 and nand16 @periph names on slcr driver.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

arch/arm/mach-zynq/slcr.c

@@ -14,6 +14,9 @@
 #define SLCR_LOCK_MAGIC		0x767B
 #define SLCR_UNLOCK_MAGIC	0xDF0D
 
+#define SLCR_NAND_L2_SEL		0x10
+#define SLCR_NAND_L2_SEL_MASK		0x1F
+
 #define SLCR_USB_L1_SEL			0x04
 
 #define SLCR_IDCODE_MASK	0x1F000
@@ -36,6 +39,14 @@ struct zynq_slcr_mio_get_status {
 	u32 check_val;
 };
 
+static const int nand8_pins[] = {
+	0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
+};
+
+static const int nand16_pins[] = {
+	16, 17, 18, 19, 20, 21, 22, 23
+};
+
 static const int usb0_pins[] = {
 	28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
 };
@@ -46,6 +57,20 @@ static const int usb1_pins[] = {
 
 static const struct zynq_slcr_mio_get_status mio_periphs[] = {
 	{
+		"nand8",
+		nand8_pins,
+		ARRAY_SIZE(nand8_pins),
+		SLCR_NAND_L2_SEL_MASK,
+		SLCR_NAND_L2_SEL,
+	},
+	{
+		"nand16",
+		nand16_pins,
+		ARRAY_SIZE(nand16_pins),
+		SLCR_NAND_L2_SEL_MASK,
+		SLCR_NAND_L2_SEL,
+	},
+	{
 		"usb0",
 		usb0_pins,
 		ARRAY_SIZE(usb0_pins),