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@ -136,6 +136,23 @@ static int eth_init_ar934x(void) |
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return 0; |
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} |
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static int eth_init_qca953x(void) |
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{ |
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void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE, |
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MAP_NOCACHE); |
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const u32 mask = QCA953X_RESET_GE0_MAC | QCA953X_RESET_GE0_MDIO | |
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QCA953X_RESET_GE1_MAC | QCA953X_RESET_GE1_MDIO | |
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QCA953X_RESET_ETH_SWITCH_ANALOG | |
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QCA953X_RESET_ETH_SWITCH; |
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setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask); |
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mdelay(1); |
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clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask); |
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mdelay(1); |
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return 0; |
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} |
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int ath79_eth_reset(void) |
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{ |
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/*
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@ -146,6 +163,8 @@ int ath79_eth_reset(void) |
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return eth_init_ar933x(); |
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if (soc_is_ar934x()) |
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return eth_init_ar934x(); |
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if (soc_is_qca953x()) |
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return eth_init_qca953x(); |
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return -EINVAL; |
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} |
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@ -185,6 +204,35 @@ static int usb_reset_ar934x(void __iomem *reset_regs) |
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return 0; |
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} |
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static int usb_reset_qca953x(void __iomem *reset_regs) |
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{ |
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void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, |
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MAP_NOCACHE); |
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clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG, |
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0xf00, 0x200); |
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mdelay(10); |
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/* Ungate the USB block */ |
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setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE, |
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QCA953X_RESET_USBSUS_OVERRIDE); |
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mdelay(1); |
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clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE, |
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QCA953X_RESET_USB_PHY); |
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mdelay(1); |
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clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE, |
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QCA953X_RESET_USB_PHY_ANALOG); |
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mdelay(1); |
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clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE, |
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QCA953X_RESET_USB_HOST); |
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mdelay(1); |
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clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE, |
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QCA953X_RESET_USB_PHY_PLL_PWD_EXT); |
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mdelay(1); |
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return 0; |
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} |
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int ath79_usb_reset(void) |
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{ |
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void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE, |
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@ -204,6 +252,8 @@ int ath79_usb_reset(void) |
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return usb_reset_ar933x(reset_regs); |
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if (soc_is_ar934x()) |
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return usb_reset_ar934x(reset_regs); |
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if (soc_is_qca953x()) |
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return usb_reset_qca953x(reset_regs); |
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return -EINVAL; |
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} |
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