The SAMA5D27-SiP (System in Package) integrates the SAMA5D2 with 1Gbit DDR2-SDRAM in a single package. The SAMA5D27 SOM1 embeds a 64Mbit QSPI flash, KSZ8081 Phy and Mac-address EEPROM. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>master
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/* |
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* at91-sama5d27_som1_ek.dts - Device Tree file for SAMA5D27 SOM1 EK board |
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* |
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* Copyright (C) 2017 Microchip Corporation |
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* Wenyou Yang <wenyou.yang@microchip.com> |
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* |
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* This file is dual-licensed: you can use it either under the terms |
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* of the GPL or the X11 license, at your option. Note that this dual |
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* licensing only applies to this file, and not this project as a |
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* whole. |
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* |
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* a) This file is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of the |
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* License, or (at your option) any later version. |
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* |
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* This file is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* Or, alternatively, |
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* |
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* b) Permission is hereby granted, free of charge, to any person |
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* obtaining a copy of this software and associated documentation |
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* files (the "Software"), to deal in the Software without |
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* restriction, including without limitation the rights to use, |
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* copy, modify, merge, publish, distribute, sublicense, and/or |
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* sell copies of the Software, and to permit persons to whom the |
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* Software is furnished to do so, subject to the following |
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* conditions: |
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* |
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* The above copyright notice and this permission notice shall be |
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* included in all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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* OTHER DEALINGS IN THE SOFTWARE. |
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*/ |
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/dts-v1/; |
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#include "sama5d27_som1.dtsi" |
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|
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/ { |
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model = "Atmel SAMA5D27 SOM1 EK"; |
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compatible = "atmel,sama5d27-som1-ek", "atmel,sama5d2", "atmel,sama5"; |
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|
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chosen { |
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u-boot,dm-pre-reloc; |
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stdout-path = &uart1; |
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}; |
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|
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ahb { |
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usb1: ohci@00400000 { |
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num-ports = <3>; |
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atmel,vbus-gpio = <&pioA 42 0>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_usb_default>; |
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status = "okay"; |
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}; |
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|
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usb2: ehci@00500000 { |
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status = "okay"; |
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}; |
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|
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sdmmc0: sdio-host@a0000000 { |
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bus-width = <8>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>; |
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status = "okay"; |
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u-boot,dm-pre-reloc; |
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}; |
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|
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sdmmc1: sdio-host@b0000000 { |
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bus-width = <4>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>; |
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status = "okay"; /* conflict with qspi0 */ |
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u-boot,dm-pre-reloc; |
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}; |
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|
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apb { |
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hlcdc: hlcdc@f0000000 { |
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atmel,vl-bpix = <4>; |
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atmel,guard-time = <1>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb666>; |
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status = "okay"; |
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u-boot,dm-pre-reloc; |
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|
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display-timings { |
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u-boot,dm-pre-reloc; |
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480x272 { |
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clock-frequency = <9000000>; |
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hactive = <480>; |
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vactive = <272>; |
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hsync-len = <41>; |
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hfront-porch = <2>; |
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hback-porch = <2>; |
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vfront-porch = <2>; |
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vback-porch = <2>; |
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vsync-len = <11>; |
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u-boot,dm-pre-reloc; |
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}; |
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}; |
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}; |
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|
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uart1: serial@f8020000 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_uart1_default>; |
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status = "okay"; |
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u-boot,dm-pre-reloc; |
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}; |
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|
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pioA: gpio@fc038000 { |
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pinctrl { |
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pinctrl_lcd_base: pinctrl_lcd_base { |
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pinmux = <PIN_PC5__LCDVSYNC>, |
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<PIN_PC6__LCDHSYNC>, |
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<PIN_PC8__LCDDEN>, |
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<PIN_PC7__LCDPCK>; |
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bias-disable; |
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}; |
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|
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pinctrl_lcd_pwm: pinctrl_lcd_pwm { |
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pinmux = <PIN_PC3__LCDPWM>; |
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bias-disable; |
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}; |
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|
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pinctrl_lcd_rgb666: pinctrl_lcd_rgb666 { |
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pinmux = <PIN_PB13__LCDDAT2>, |
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<PIN_PB14__LCDDAT3>, |
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<PIN_PB15__LCDDAT4>, |
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<PIN_PB16__LCDDAT5>, |
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<PIN_PB17__LCDDAT6>, |
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<PIN_PB18__LCDDAT7>, |
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<PIN_PB21__LCDDAT10>, |
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<PIN_PB22__LCDDAT11>, |
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<PIN_PB23__LCDDAT12>, |
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<PIN_PB24__LCDDAT13>, |
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<PIN_PB25__LCDDAT14>, |
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<PIN_PB26__LCDDAT15>, |
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<PIN_PB29__LCDDAT18>, |
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<PIN_PB30__LCDDAT19>, |
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<PIN_PB31__LCDDAT20>, |
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<PIN_PC0__LCDDAT21>, |
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<PIN_PC1__LCDDAT22>, |
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<PIN_PC2__LCDDAT23>; |
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bias-disable; |
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}; |
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|
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pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default { |
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pinmux = <PIN_PA1__SDMMC0_CMD>, |
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<PIN_PA2__SDMMC0_DAT0>, |
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<PIN_PA3__SDMMC0_DAT1>, |
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<PIN_PA4__SDMMC0_DAT2>, |
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<PIN_PA5__SDMMC0_DAT3>, |
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<PIN_PA6__SDMMC0_DAT4>, |
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<PIN_PA7__SDMMC0_DAT5>, |
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<PIN_PA8__SDMMC0_DAT6>, |
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<PIN_PA9__SDMMC0_DAT7>; |
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bias-pull-up; |
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u-boot,dm-pre-reloc; |
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}; |
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|
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pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default { |
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pinmux = <PIN_PA0__SDMMC0_CK>, |
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<PIN_PA10__SDMMC0_RSTN>, |
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<PIN_PA13__SDMMC0_CD>; |
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bias-disable; |
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u-boot,dm-pre-reloc; |
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}; |
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|
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pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default { |
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pinmux = <PIN_PA28__SDMMC1_CMD>, |
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<PIN_PA18__SDMMC1_DAT0>, |
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<PIN_PA19__SDMMC1_DAT1>, |
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<PIN_PA20__SDMMC1_DAT2>, |
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<PIN_PA21__SDMMC1_DAT3>; |
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bias-pull-up; |
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u-boot,dm-pre-reloc; |
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}; |
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|
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pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default { |
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pinmux = <PIN_PA22__SDMMC1_CK>, |
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<PIN_PA30__SDMMC1_CD>; |
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bias-disable; |
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u-boot,dm-pre-reloc; |
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}; |
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|
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pinctrl_uart1_default: uart1_default { |
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pinmux = <PIN_PD2__URXD1>, |
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<PIN_PD3__UTXD1>; |
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bias-disable; |
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u-boot,dm-pre-reloc; |
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}; |
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|
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pinctrl_usb_default: usb_default { |
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pinmux = <PIN_PB10__GPIO>; |
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bias-disable; |
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}; |
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|
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pinctrl_usba_vbus: usba_vbus { |
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pinmux = <PIN_PA31__GPIO>; |
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bias-disable; |
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}; |
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}; |
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}; |
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}; |
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}; |
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}; |
@ -0,0 +1,159 @@ |
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/* |
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* sama5d27_som1.dtsi - Device Tree file for SAMA5D27 SOM1 |
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* |
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* Copyright (C) 2017 Microchip Corporation |
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* Wenyou Yang <wenyou.yang@microchip.com> |
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* |
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* This file is dual-licensed: you can use it either under the terms |
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* of the GPL or the X11 license, at your option. Note that this dual |
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* licensing only applies to this file, and not this project as a |
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* whole. |
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* |
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* a) This file is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of the |
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* License, or (at your option) any later version. |
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* |
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* This file is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* Or, alternatively, |
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* |
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* b) Permission is hereby granted, free of charge, to any person |
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* obtaining a copy of this software and associated documentation |
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* files (the "Software"), to deal in the Software without |
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* restriction, including without limitation the rights to use, |
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* copy, modify, merge, publish, distribute, sublicense, and/or |
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* sell copies of the Software, and to permit persons to whom the |
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* Software is furnished to do so, subject to the following |
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* conditions: |
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* |
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* The above copyright notice and this permission notice shall be |
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* included in all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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* OTHER DEALINGS IN THE SOFTWARE. |
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*/ |
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|
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#include "sama5d2.dtsi" |
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#include "sama5d2-pinfunc.h" |
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/ { |
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model = "Atmel SAMA5D27 SOM1 EK"; |
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compatible = "atmel,sama5d27-som1-ek", "atmel,sama5d2", "atmel,sama5"; |
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|
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memory { |
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reg = <0x20000000 0x8000000>; |
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}; |
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|
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aliases { |
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spi0 = &qspi1; |
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u-boot,dm-pre-reloc; |
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}; |
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|
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ahb { |
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apb { |
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qspi1: spi@f0024000 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_qspi1_sck_cs_default &pinctrl_qspi1_dat_default>; |
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status = "okay"; |
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u-boot,dm-pre-reloc; |
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|
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spi_flash@0 { |
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compatible = "spi-flash"; |
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reg = <0>; |
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spi-max-frequency = <50000000>; |
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spi-rx-bus-width = <4>; |
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spi-tx-bus-width = <4>; |
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u-boot,dm-pre-reloc; |
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}; |
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}; |
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|
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macb0: ethernet@f8008000 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>; |
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phy-mode = "rmii"; |
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status = "okay"; |
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|
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ethernet-phy@1 { |
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reg = <0x1>; |
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}; |
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}; |
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|
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i2c0: i2c@f8028000 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_i2c0_default>; |
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status = "okay"; |
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|
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i2c_eeprom: i2c_eeprom@50 { |
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compatible = "microchip,24aa02e48"; |
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reg = <0x50>; |
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}; |
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}; |
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|
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i2c1: i2c@fc028000 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_i2c1_default>; |
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status = "okay"; |
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}; |
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|
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pioA: gpio@fc038000 { |
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pinctrl { |
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pinctrl_i2c0_default: i2c0_default { |
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pinmux = <PIN_PD21__TWD0>, |
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<PIN_PD22__TWCK0>; |
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bias-disable; |
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}; |
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|
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pinctrl_i2c1_default: i2c1_default { |
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pinmux = <PIN_PD4__TWD1>, |
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<PIN_PD5__TWCK1>; |
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bias-disable; |
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}; |
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|
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pinctrl_macb0_phy_irq: macb0_phy_irq { |
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pinmux = <PIN_PD31__GPIO>; |
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bias-disable; |
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}; |
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|
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pinctrl_macb0_rmii: macb0_rmii { |
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pinmux = <PIN_PD9__GTXCK>, |
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<PIN_PD10__GTXEN>, |
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<PIN_PD11__GRXDV>, |
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<PIN_PD12__GRXER>, |
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<PIN_PD13__GRX0>, |
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<PIN_PD14__GRX1>, |
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<PIN_PD15__GTX0>, |
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<PIN_PD16__GTX1>, |
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<PIN_PD17__GMDC>, |
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<PIN_PD18__GMDIO>; |
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bias-disable; |
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}; |
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|
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pinctrl_qspi1_sck_cs_default: qspi1_sck_cs_default { |
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pinmux = <PIN_PB5__QSPI1_SCK>, |
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<PIN_PB6__QSPI1_CS>; |
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bias-disable; |
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u-boot,dm-pre-reloc; |
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}; |
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|
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pinctrl_qspi1_dat_default: qspi1_dat_default { |
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pinmux = <PIN_PB7__QSPI1_IO0>, |
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<PIN_PB8__QSPI1_IO1>, |
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<PIN_PB9__QSPI1_IO2>, |
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<PIN_PB10__QSPI1_IO3>; |
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bias-pull-up; |
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u-boot,dm-pre-reloc; |
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}; |
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}; |
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}; |
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}; |
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}; |
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}; |
@ -0,0 +1,15 @@ |
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if TARGET_SAMA5D27_SOM1_EK |
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|
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config SYS_BOARD |
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default "sama5d27_som1_ek" |
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|
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config SYS_VENDOR |
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default "atmel" |
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|
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config SYS_SOC |
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default "at91" |
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|
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config SYS_CONFIG_NAME |
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default "sama5d27_som1_ek" |
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|
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endif |
@ -0,0 +1,6 @@ |
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SAMA5D27 SOM1 EK BOARD |
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M: Wenyou Yang <wenyou.yang@microchip.com> |
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S: Maintained |
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F: board/atmel/sama5d27_som1_ek/ |
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F: include/configs/sama5d27_som1_ek.h |
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F: configs/sama5d27_som1_ek_mmc_defconfig |
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#
|
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# Copyright (C) 2017 Microchip Corporation
|
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# Wenyou Yang <wenyou.yang@microchip.com>
|
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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|
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obj-y += sama5d27_som1_ek.o
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@ -0,0 +1,189 @@ |
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/*
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* Copyright (C) 2017 Microchip Corporation |
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* Wenyou.Yang <wenyou.yang@microchip.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <debug_uart.h> |
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#include <asm/io.h> |
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#include <asm/arch/at91_common.h> |
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#include <asm/arch/atmel_pio4.h> |
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#include <asm/arch/atmel_mpddrc.h> |
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#include <asm/arch/atmel_sdhci.h> |
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#include <asm/arch/clk.h> |
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#include <asm/arch/gpio.h> |
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#include <asm/arch/sama5d2.h> |
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|
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DECLARE_GLOBAL_DATA_PTR; |
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|
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static void board_usb_hw_init(void) |
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{ |
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atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1); |
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} |
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|
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#ifdef CONFIG_BOARD_LATE_INIT |
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int board_late_init(void) |
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{ |
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#ifdef CONFIG_DM_VIDEO |
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at91_video_show_board_info(); |
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#endif |
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return 0; |
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} |
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#endif |
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|
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT |
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static void board_uart1_hw_init(void) |
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{ |
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atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1); /* URXD1 */ |
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atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */ |
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|
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at91_periph_clk_enable(ATMEL_ID_UART1); |
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} |
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|
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void board_debug_uart_init(void) |
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{ |
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board_uart1_hw_init(); |
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} |
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#endif |
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|
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#ifdef CONFIG_BOARD_EARLY_INIT_F |
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int board_early_init_f(void) |
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{ |
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#ifdef CONFIG_DEBUG_UART |
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debug_uart_init(); |
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#endif |
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|
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return 0; |
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} |
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#endif |
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|
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int board_init(void) |
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{ |
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/* address of boot parameters */ |
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
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|
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#ifdef CONFIG_CMD_USB |
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board_usb_hw_init(); |
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#endif |
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|
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return 0; |
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} |
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|
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int dram_init(void) |
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{ |
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, |
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CONFIG_SYS_SDRAM_SIZE); |
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return 0; |
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} |
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|
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#define MAC24AA_MAC_OFFSET 0xfa |
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|
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#ifdef CONFIG_MISC_INIT_R |
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int misc_init_r(void) |
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{ |
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#ifdef CONFIG_I2C_EEPROM |
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at91_set_ethaddr(MAC24AA_MAC_OFFSET); |
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#endif |
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return 0; |
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} |
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#endif |
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|
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/* SPL */ |
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#ifdef CONFIG_SPL_BUILD |
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void spl_board_init(void) |
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{ |
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} |
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|
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static void ddrc_conf(struct atmel_mpddrc_config *ddrc) |
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{ |
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ddrc->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); |
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|
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ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | |
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ATMEL_MPDDRC_CR_NR_ROW_13 | |
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ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | |
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ATMEL_MPDDRC_CR_DIC_DS | |
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ATMEL_MPDDRC_CR_ZQ_LONG | |
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ATMEL_MPDDRC_CR_NB_8BANKS | |
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ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | |
||||
ATMEL_MPDDRC_CR_UNAL_SUPPORTED); |
||||
|
||||
ddrc->rtr = 0x511; |
||||
|
||||
ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) | |
||||
(3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) | |
||||
(3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) | |
||||
(9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) | |
||||
(3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) | |
||||
(4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) | |
||||
(4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) | |
||||
(2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET)); |
||||
|
||||
ddrc->tpr1 = ((22 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) | |
||||
(23 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) | |
||||
(200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) | |
||||
(3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET)); |
||||
|
||||
ddrc->tpr2 = ((2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) | |
||||
(8 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) | |
||||
(4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) | |
||||
(4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) | |
||||
(8 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET)); |
||||
} |
||||
|
||||
void mem_init(void) |
||||
{ |
||||
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; |
||||
struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; |
||||
struct atmel_mpddrc_config ddrc_config; |
||||
u32 reg; |
||||
|
||||
ddrc_conf(&ddrc_config); |
||||
|
||||
at91_periph_clk_enable(ATMEL_ID_MPDDRC); |
||||
writel(AT91_PMC_DDR, &pmc->scer); |
||||
|
||||
reg = readl(&mpddrc->io_calibr); |
||||
reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV; |
||||
reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55; |
||||
reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO; |
||||
reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(101); |
||||
writel(reg, &mpddrc->io_calibr); |
||||
|
||||
writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE, |
||||
&mpddrc->rd_data_path); |
||||
|
||||
ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config); |
||||
|
||||
writel(0x3, &mpddrc->cal_mr4); |
||||
writel(64, &mpddrc->tim_cal); |
||||
} |
||||
|
||||
void at91_pmc_init(void) |
||||
{ |
||||
u32 tmp; |
||||
|
||||
/*
|
||||
* while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz |
||||
* so we need to slow down and configure MCKR accordingly. |
||||
* This is why we have a special flavor of the switching function. |
||||
*/ |
||||
tmp = AT91_PMC_MCKR_PLLADIV_2 | |
||||
AT91_PMC_MCKR_MDIV_3 | |
||||
AT91_PMC_MCKR_CSS_MAIN; |
||||
at91_mck_init_down(tmp); |
||||
|
||||
tmp = AT91_PMC_PLLAR_29 | |
||||
AT91_PMC_PLLXR_PLLCOUNT(0x3f) | |
||||
AT91_PMC_PLLXR_MUL(40) | |
||||
AT91_PMC_PLLXR_DIV(1); |
||||
at91_plla_init(tmp); |
||||
|
||||
tmp = AT91_PMC_MCKR_H32MXDIV | |
||||
AT91_PMC_MCKR_PLLADIV_2 | |
||||
AT91_PMC_MCKR_MDIV_3 | |
||||
AT91_PMC_MCKR_CSS_PLLA; |
||||
at91_mck_init(tmp); |
||||
} |
||||
#endif |
@ -0,0 +1,88 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_AT91=y |
||||
CONFIG_TARGET_SAMA5D27_SOM1_EK=y |
||||
CONFIG_SPL_GPIO_SUPPORT=y |
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y |
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y |
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000 |
||||
CONFIG_SPL_MMC_SUPPORT=y |
||||
CONFIG_SPL_SERIAL_SUPPORT=y |
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y |
||||
CONFIG_SPL_LIBDISK_SUPPORT=y |
||||
CONFIG_SPL_FAT_SUPPORT=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek" |
||||
CONFIG_DEBUG_UART=y |
||||
CONFIG_FIT=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" |
||||
CONFIG_SD_BOOT=y |
||||
CONFIG_BOOTDELAY=3 |
||||
# CONFIG_DISPLAY_BOARDINFO is not set |
||||
CONFIG_SPL=y |
||||
CONFIG_SPL_SEPARATE_BSS=y |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_CMD_BOOTZ=y |
||||
# CONFIG_CMD_IMI is not set |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_FLASH is not set |
||||
# CONFIG_CMD_FPGA is not set |
||||
CONFIG_CMD_I2C=y |
||||
# CONFIG_CMD_LOADS is not set |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_SF=y |
||||
CONFIG_CMD_USB=y |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_EXT4=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_SPL_OF_CONTROL=y |
||||
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" |
||||
CONFIG_ENV_IS_IN_FAT=y |
||||
CONFIG_DM=y |
||||
CONFIG_SPL_DM=y |
||||
CONFIG_SPL_DM_SEQ_ALIAS=y |
||||
CONFIG_CLK=y |
||||
CONFIG_SPL_CLK=y |
||||
CONFIG_CLK_AT91=y |
||||
CONFIG_AT91_UTMI=y |
||||
CONFIG_AT91_H32MX=y |
||||
CONFIG_AT91_GENERIC_CLK=y |
||||
CONFIG_DM_GPIO=y |
||||
CONFIG_ATMEL_PIO4=y |
||||
CONFIG_DM_I2C=y |
||||
CONFIG_SYS_I2C_AT91=y |
||||
CONFIG_I2C_EEPROM=y |
||||
CONFIG_DM_MMC=y |
||||
CONFIG_MMC_SDHCI=y |
||||
CONFIG_MMC_SDHCI_ATMEL=y |
||||
CONFIG_DM_SPI_FLASH=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_SPI_FLASH_ATMEL=y |
||||
CONFIG_SPI_FLASH_MACRONIX=y |
||||
CONFIG_SPI_FLASH_STMICRO=y |
||||
CONFIG_SPI_FLASH_SST=y |
||||
CONFIG_DM_ETH=y |
||||
CONFIG_MACB=y |
||||
CONFIG_PINCTRL=y |
||||
CONFIG_SPL_PINCTRL=y |
||||
CONFIG_PINCTRL_AT91PIO4=y |
||||
CONFIG_DM_SERIAL=y |
||||
CONFIG_DEBUG_UART_ATMEL=y |
||||
CONFIG_DEBUG_UART_BASE=0xf8020000 |
||||
CONFIG_DEBUG_UART_CLOCK=82000000 |
||||
CONFIG_DEBUG_UART_BOARD_INIT=y |
||||
CONFIG_DEBUG_UART_ANNOUNCE=y |
||||
CONFIG_ATMEL_USART=y |
||||
CONFIG_DM_SPI=y |
||||
CONFIG_ATMEL_SPI=y |
||||
CONFIG_TIMER=y |
||||
CONFIG_SPL_TIMER=y |
||||
CONFIG_ATMEL_PIT_TIMER=y |
||||
CONFIG_USB=y |
||||
CONFIG_DM_USB=y |
||||
CONFIG_USB_EHCI_HCD=y |
||||
CONFIG_USB_STORAGE=y |
||||
CONFIG_USB_GADGET=y |
||||
CONFIG_USB_GADGET_ATMEL_USBA=y |
||||
CONFIG_DM_VIDEO=y |
||||
CONFIG_ATMEL_HLCD=y |
@ -0,0 +1,92 @@ |
||||
/*
|
||||
* Configuration file for the SAMA5D27 SOM1 EK Board. |
||||
* |
||||
* Copyright (C) 2017 Microchip Corporation |
||||
* Wenyou Yang <wenyou.yang@microchip.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#include "at91-sama5_common.h" |
||||
|
||||
#undef CONFIG_SYS_TEXT_BASE |
||||
#undef CONFIG_SYS_AT91_MAIN_CLOCK |
||||
#define CONFIG_SYS_TEXT_BASE 0x23f00000 |
||||
#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ |
||||
|
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
/* SDRAM */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define CONFIG_SYS_SDRAM_BASE 0x20000000 |
||||
#define CONFIG_SYS_SDRAM_SIZE 0x8000000 |
||||
|
||||
#ifdef CONFIG_SPL_BUILD |
||||
#define CONFIG_SYS_INIT_SP_ADDR 0x218000 |
||||
#else |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ |
||||
|
||||
/* NAND flash */ |
||||
#undef CONFIG_CMD_NAND |
||||
|
||||
/* SPI flash */ |
||||
#define CONFIG_SF_DEFAULT_SPEED 66000000 |
||||
|
||||
#undef CONFIG_BOOTCOMMAND |
||||
#ifdef CONFIG_SD_BOOT |
||||
/* u-boot env in sd/mmc card */ |
||||
#define FAT_ENV_INTERFACE "mmc" |
||||
#define FAT_ENV_DEVICE_AND_PART "0" |
||||
#define FAT_ENV_FILE "uboot.env" |
||||
#define CONFIG_ENV_SIZE 0x4000 |
||||
/* bootstrap + u-boot + env in sd card */ |
||||
#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d27_som1_ek.dtb; " \ |
||||
"fatload mmc 0:1 0x22000000 zImage; " \
|
||||
"bootz 0x22000000 - 0x21000000" |
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_BOOTARGS \ |
||||
"console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait" |
||||
#endif |
||||
|
||||
#ifdef CONFIG_QSPI_BOOT |
||||
#define CONFIG_ENV_OFFSET 0xb0000 |
||||
#define CONFIG_ENV_SIZE 0x10000 |
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 |
||||
#define CONFIG_BOOTCOMMAND "sf probe 0; " \ |
||||
"sf read 0x21000000 0xc0000 0x20000; " \
|
||||
"sf read 0x22000000 0xe0000 0x400000; " \
|
||||
"bootz 0x22000000 - 0x21000000" |
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_BOOTARGS \ |
||||
"console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait" |
||||
#endif |
||||
|
||||
/* SPL */ |
||||
#define CONFIG_SPL_FRAMEWORK |
||||
#define CONFIG_SPL_TEXT_BASE 0x200000 |
||||
#define CONFIG_SPL_MAX_SIZE 0x10000 |
||||
#define CONFIG_SPL_BSS_START_ADDR 0x20000000 |
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 |
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 |
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 << 10) |
||||
|
||||
#ifdef CONFIG_SD_BOOT |
||||
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 |
||||
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
||||
#endif |
||||
|
||||
#ifdef CONFIG_QSPI_BOOT |
||||
#define CONFIG_SPL_SPI_LOAD |
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 |
||||
#endif |
||||
|
||||
#endif |
Loading…
Reference in new issue