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@ -29,26 +29,35 @@ void bfin_reset(void) |
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*/ |
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__builtin_bfin_ssync(); |
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while (1) { |
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/* The bootrom checks to see how it was reset and will
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* automatically perform a software reset for us when |
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* it starts executing after the core reset. |
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*/ |
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if (ANOMALY_05000353 || ANOMALY_05000386) { |
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/* Initiate System software reset. */ |
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bfin_write_SWRST(0x7); |
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/* Due to the way reset is handled in the hardware, we need
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* to delay for 7 SCLKS. The only reliable way to do this is |
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* to calculate the CCLK/SCLK ratio and multiply 7. For now, |
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* to delay for 10 SCLKS. The only reliable way to do this is |
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* to calculate the CCLK/SCLK ratio and multiply 10. For now, |
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* we'll assume worse case which is a 1:15 ratio. |
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*/ |
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asm( |
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"LSETUP (1f, 1f) LC0 = %0\n" |
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"1: nop;" |
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: |
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: "a" (15 * 7) |
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: "a" (15 * 10) |
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: "LC0", "LB0", "LT0" |
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); |
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/* Clear System software reset */ |
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bfin_write_SWRST(0); |
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/* The BF526 ROM will crash during reset */ |
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#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__) |
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bfin_read_SWRST(); |
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#endif |
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/* Wait for the SWRST write to complete. Cannot rely on SSYNC
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* though as the System state is all reset now. |
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*/ |
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@ -59,10 +68,11 @@ void bfin_reset(void) |
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: "a" (15 * 1) |
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: "LC1", "LB1", "LT1" |
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); |
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} |
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while (1) |
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/* Issue core reset */ |
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asm("raise 1"); |
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} |
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} |
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/* We need to trampoline ourselves up into L1 since our linker
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