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@ -45,8 +45,6 @@ |
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
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#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */ |
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#define CONFIG_BOARD_TYPES 1 /* support board types */ |
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#define CONFIG_PREBOOT "echo;" \ |
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@ -75,6 +73,8 @@ |
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"" |
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#define CONFIG_BOOTCOMMAND "run flash_self" |
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#define CONFIG_MISC_INIT_R 1 |
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
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#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
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@ -252,15 +252,8 @@ |
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*----------------------------------------------------------------------- |
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* Reset PLL lock status sticky bit, timer expired status bit and timer |
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* interrupt status bit |
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* |
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* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! |
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*/ |
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#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ |
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#define CFG_PLPRCR \ |
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( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) |
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#else /* up to 66 MHz we use a 1:1 clock */ |
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#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
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#endif /* CONFIG_80MHz */ |
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27 |
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@ -269,17 +262,9 @@ |
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* power management and some other internal clocks |
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*/ |
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#define SCCR_MASK SCCR_EBDF11 |
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#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ |
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#define CFG_SCCR (/* SCCR_TBS | */ \ |
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SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
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SCCR_DFALCD00) |
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#else /* up to 66 MHz we use a 1:1 clock */ |
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#define CFG_SCCR (SCCR_TBS | \ |
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SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
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SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
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SCCR_DFALCD00) |
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#endif /* CONFIG_80MHz */ |
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/*-----------------------------------------------------------------------
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* PCMCIA stuff |
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@ -355,19 +340,8 @@ |
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/*
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* FLASH timing: |
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*/ |
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#if defined(CONFIG_80MHz) |
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/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ |
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#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \ |
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OR_SCY_3_CLK | OR_EHTR | OR_BI) |
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#elif defined(CONFIG_66MHz) |
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/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */ |
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#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ |
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OR_SCY_3_CLK | OR_EHTR | OR_BI) |
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#else /* 50 MHz */ |
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/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */ |
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#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ |
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OR_SCY_2_CLK | OR_EHTR | OR_BI) |
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#endif /*CONFIG_??MHz */ |
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#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) |
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#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) |
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@ -437,13 +411,9 @@ |
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* 66 Mhz => 66.000.000 / Divider = 129 |
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* 80 Mhz => 80.000.000 / Divider = 156 |
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*/ |
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#if defined(CONFIG_80MHz) |
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#define CFG_MAMR_PTA 156 |
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#elif defined(CONFIG_66MHz) |
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#define CFG_MAMR_PTA 129 |
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#else /* 50 MHz */ |
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#define CFG_MAMR_PTA 98 |
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#endif /*CONFIG_??MHz */ |
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#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) |
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#define CFG_MAMR_PTA 98 |
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/*
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* For 16 MBit, refresh rates could be 31.3 us |
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