@ -28,7 +28,6 @@
# include <asm/arch/crm_regs.h>
# include <asm/io.h>
# include <asm/arch/sys_proto.h>
# include <asm/arch/mx6-ddr.h>
# include <spl.h>
DECLARE_GLOBAL_DATA_PTR ;
@ -59,22 +58,22 @@ int dram_init(void)
}
static iomux_v3_cfg_t const uart1_pads [ ] = {
MX6 _PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL ( UART_PAD_CTRL ) ,
MX6 _PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL ( UART_PAD_CTRL ) ,
IO MU X_PADS ( PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL ( UART_PAD_CTRL ) ) ,
IO MU X_PADS ( PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL ( UART_PAD_CTRL ) ) ,
} ;
static iomux_v3_cfg_t const usdhc2_pads [ ] = {
MX6 _PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ,
MX6 _PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ,
MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ,
MX6 _PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ,
MX6 _PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ,
MX6 _PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ,
IO MU X_PADS ( PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ) ,
IO MU X_PADS ( PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ) ,
IOMUX_PADS ( PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ) ,
IO MU X_PADS ( PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ) ,
IO MU X_PADS ( PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ) ,
IO MU X_PADS ( PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL ( USDHC_PAD_CTRL ) ) ,
} ;
static void setup_iomux_uart ( void )
{
imx_iomux_v3_setup_multiple_pads ( uart1_pads , ARRAY_SIZE ( uart1_pads ) ) ;
SETUP_IOMUX_PADS ( uart1_pads ) ;
}
static struct fsl_esdhc_cfg usdhc_cfg [ 1 ] = {
@ -88,7 +87,7 @@ int board_mmc_getcd(struct mmc *mmc)
int board_mmc_init ( bd_t * bis )
{
imx_iomux_v3_setup_multiple_pads ( usdhc2_pads , ARRAY_SIZE ( usdhc2_pads ) ) ;
SETUP_IOMUX_PADS ( usdhc2_pads ) ;
usdhc_cfg [ 0 ] . esdhc_base = USDHC2_BASE_ADDR ;
usdhc_cfg [ 0 ] . sdhc_clk = mxc_get_clock ( MXC_ESDHC2_CLK ) ;
gd - > arch . sdhc_clk = usdhc_cfg [ 0 ] . sdhc_clk ;
@ -97,33 +96,33 @@ int board_mmc_init(bd_t *bis)
}
static iomux_v3_cfg_t const enet_pads [ ] = {
MX6 _PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL ( ENET_PAD_CTRL ) ,
MX6 _PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL ( ENET_PAD_CTRL ) ,
IO MU X_PADS ( PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL ( ENET_PAD_CTRL ) ) ,
IO MU X_PADS ( PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL ( ENET_PAD_CTRL ) ) ,
/* AR8035 reset */
MX6 _PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL ( ENET_PAD_CTRL_PD ) ,
IO MU X_PADS ( PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL ( ENET_PAD_CTRL_PD ) ) ,
/* AR8035 interrupt */
MX6 _PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL ( NO_PAD_CTRL ) ,
IO MU X_PADS ( PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL ( NO_PAD_CTRL ) ) ,
/* GPIO16 -> AR8035 25MHz */
MX6 _PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL ( NO_PAD_CTRL ) ,
MX6 _PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL ( NO_PAD_CTRL ) ,
MX6 _PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL ( ENET_PAD_CTRL ) ,
MX6 _PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL ( ENET_PAD_CTRL ) ,
MX6 _PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL ( ENET_PAD_CTRL ) ,
MX6 _PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL ( ENET_PAD_CTRL ) ,
MX6 _PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL ( ENET_PAD_CTRL ) ,
IO MU X_PADS ( PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL ( NO_PAD_CTRL ) ) ,
IO MU X_PADS ( PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL ( NO_PAD_CTRL ) ) ,
IO MU X_PADS ( PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL ( ENET_PAD_CTRL ) ) ,
IO MU X_PADS ( PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL ( ENET_PAD_CTRL ) ) ,
IO MU X_PADS ( PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL ( ENET_PAD_CTRL ) ) ,
IO MU X_PADS ( PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL ( ENET_PAD_CTRL ) ) ,
IO MU X_PADS ( PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL ( ENET_PAD_CTRL ) ) ,
/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
MX6 _PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL ( ENET_PAD_CTRL_CLK ) ,
MX6 _PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL ( ENET_PAD_CTRL ) ,
MX6 _PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL ( ENET_PAD_CTRL_PD ) ,
MX6 _PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL ( ENET_PAD_CTRL_PD ) ,
MX6 _PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL ( ENET_PAD_CTRL ) ,
MX6 _PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL ( ENET_PAD_CTRL ) ,
MX6 _PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL ( ENET_PAD_CTRL_PD ) ,
IO MU X_PADS ( PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL ( ENET_PAD_CTRL_CLK ) ) ,
IO MU X_PADS ( PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL ( ENET_PAD_CTRL ) ) ,
IO MU X_PADS ( PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL ( ENET_PAD_CTRL_PD ) ) ,
IO MU X_PADS ( PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL ( ENET_PAD_CTRL_PD ) ) ,
IO MU X_PADS ( PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL ( ENET_PAD_CTRL ) ) ,
IO MU X_PADS ( PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL ( ENET_PAD_CTRL ) ) ,
IO MU X_PADS ( PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL ( ENET_PAD_CTRL_PD ) ) ,
} ;
static void setup_iomux_enet ( void )
{
imx_iomux_v3_setup_multiple_pads ( enet_pads , ARRAY_SIZE ( enet_pads ) ) ;
SETUP_IOMUX_PADS ( enet_pads ) ;
gpio_direction_output ( ETH_PHY_RESET , 0 ) ;
mdelay ( 2 ) ;
@ -175,6 +174,7 @@ int checkboard(void)
}
# ifdef CONFIG_SPL_BUILD
# include <asm/arch/mx6-ddr.h>
static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
. dram_sdclk_0 = 0x00020030 ,
. dram_sdclk_1 = 0x00020030 ,