From 3313ae668e0071f91cdf305fedb39b960beab62d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 18 Jul 2018 14:33:15 +0200 Subject: [PATCH 01/14] spl: fpga: Implement fpga bistream loading with fpga_load This patch partially reverts: "spl: fit: Add support for loading FPGA bitstream" (sha1: 26a642238bdecc53527142dc043b29e21c5cc94c) There shouldn't be a need to call private spl_load_fpga_image function because the whole sequence should be already handled by fpga framework. If there is missing loading bistream by chunks it should be done via fpga framework instead of having private hooks. Also spl_load_fpga_image() weak function is not used anywhere and opening a way for not reviewed hacks out of mainline U-Boot is not the right way to go. Signed-off-by: Michal Simek --- common/spl/spl_fit.c | 34 ++++++++++++++++------------------ 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index cb0cc52..faf4ddb 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -140,14 +141,6 @@ static int get_aligned_image_size(struct spl_load_info *info, int data_size, return (data_size + info->bl_len - 1) / info->bl_len; } -#ifdef CONFIG_SPL_FPGA_SUPPORT -__weak int spl_load_fpga_image(struct spl_load_info *info, size_t length, - int nr_sectors, int sector_offset) -{ - return 0; -} -#endif - /** * spl_load_fit_image(): load the image described in a certain FIT node * @info: points to information about the device to load data from @@ -169,7 +162,7 @@ static int spl_load_fit_image(struct spl_load_info *info, ulong sector, void *fit, ulong base_offset, int node, struct spl_image_info *image_info) { - int offset, sector_offset; + int offset; size_t length; int len; ulong size; @@ -217,16 +210,9 @@ static int spl_load_fit_image(struct spl_load_info *info, ulong sector, overhead = get_aligned_image_overhead(info, offset); nr_sectors = get_aligned_image_size(info, length, offset); - sector_offset = sector + get_aligned_image_offset(info, offset); - -#ifdef CONFIG_SPL_FPGA_SUPPORT - if (type == IH_TYPE_FPGA) { - return spl_load_fpga_image(info, length, nr_sectors, - sector_offset); - } -#endif - if (info->read(info, sector_offset, + if (info->read(info, + sector + get_aligned_image_offset(info, offset), nr_sectors, (void *)load_ptr) != nr_sectors) return -EIO; @@ -409,6 +395,18 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, printf("%s: Cannot load the FPGA: %i\n", __func__, ret); return ret; } + + debug("FPGA bitstream at: %x, size: %x\n", + (u32)spl_image->load_addr, spl_image->size); + + ret = fpga_load(0, (const void *)spl_image->load_addr, + spl_image->size, BIT_FULL); + if (ret) { + printf("%s: Cannot load the image to the FPGA\n", + __func__); + return ret; + } + puts("FPGA image loaded from FIT\n"); node = -1; } From 0e4c1dd29026ee76b2ae8fb27a99366ac7d0b289 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 18 Jul 2018 13:27:24 +0200 Subject: [PATCH 02/14] arm: zynq: Enable FIT fpga loading in SPL for zc706 Enable loading FPGA from FIT image in SPL. Signed-off-by: Michal Simek --- configs/zynq_zc706_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index 6191900..bcbfa65 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -12,9 +12,12 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_PRINT=y +CONFIG_SPL_LOAD_FIT=y CONFIG_IMAGE_FORMAT_LEGACY=y CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" CONFIG_SPL_STACK_R=y +CONFIG_SPL_FPGA_SUPPORT=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_PROMPT="Zynq> " @@ -78,3 +81,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y CONFIG_WDT=y CONFIG_WDT_CDNS=y +CONFIG_SPL_GZIP=y From 6bfe3fffac1bb15b95f9e047224ac57441e46b7e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 13 Sep 2018 08:44:02 +0200 Subject: [PATCH 03/14] arm: zynq: Add support for DLC20 board Xilinx DLC20 has I2C0 with EEPROM(1KB), UART1, GPIO, SD0 (EMMC 4GB), USB0 device, ENET0, QSPI (16MB) and DDR(two of 256MB each). Boards have mix of Winbond/ST QSPIs. Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 1 + arch/arm/dts/zynq-dlc20-rev1.0.dts | 103 ++++++++ board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c | 280 +++++++++++++++++++++ configs/zynq_dlc20_rev1_0_defconfig | 74 ++++++ 4 files changed, 458 insertions(+) create mode 100644 arch/arm/dts/zynq-dlc20-rev1.0.dts create mode 100644 board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c create mode 100644 configs/zynq_dlc20_rev1_0_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index dfe9335..8e6f8e9 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -135,6 +135,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-cse-nand.dtb \ zynq-cse-nor.dtb \ zynq-cse-qspi-single.dtb \ + zynq-dlc20-rev1.0.dtb \ zynq-microzed.dtb \ zynq-minized.dtb \ zynq-picozed.dtb \ diff --git a/arch/arm/dts/zynq-dlc20-rev1.0.dts b/arch/arm/dts/zynq-dlc20-rev1.0.dts new file mode 100644 index 0000000..39ebcee --- /dev/null +++ b/arch/arm/dts/zynq-dlc20-rev1.0.dts @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Xilinx, Inc. + * + * Michal Simek + */ +/dts-v1/; +#include "zynq-7000.dtsi" + +/ { + model = "Zynq DLC20 Rev1.0"; + compatible = "xlnx,zynq-dlc20-rev1.0", "xlnx,zynq-dlc20", + "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + i2c0 = &i2c0; + serial0 = &uart1; + spi0 = &qspi; + mmc0 = &sdhci0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x20000000>; + }; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0@e0002000 { + compatible = "ulpi-phy"; + #phy-cells = <0>; + reg = <0xe0002000 0x1000>; + view-port = <0x0170>; + drv-vbus; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; /* U7 */ +}; + +&gem0 { + status = "okay"; /* MIO16-MIO27, MDIO MIO52/53 */ + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@7 { /* rtl8211e - U25 */ + reg = <1>; + }; +}; + +&i2c0 { + status = "okay"; /* MIO14/15 */ + clock-frequency = <400000>; + /* U46 - m24c08 */ + eeprom: eeprom@54 { + compatible = "atmel,24c08"; + reg = <0x54>; + }; +}; + +&qspi { + u-boot,dm-pre-reloc; + status = "okay"; + is-dual = <0>; + num-cs = <1>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + flash@0 { + /* Rev1.0 W25Q128FWSIG, RevC N25Q128A */ + compatible = "n25q128a11", "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + }; +}; + +&sdhci0 { + u-boot,dm-pre-reloc; + status = "okay"; /* EMMC MTFC4GACAJCN - MIO40-MIO45 */ + non-removable; + bus-width = <4>; +}; + +&uart1 { + u-boot,dm-pre-reloc; + status = "okay"; /* MIO8/9 */ +}; + +&usb0 { + status = "okay"; /* MIO28-MIO39 */ + dr_mode = "device"; + usb-phy = <&usb_phy0>; +}; + +&watchdog0 { + reset-on-timeout; +}; diff --git a/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c b/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c new file mode 100644 index 0000000..5366956 --- /dev/null +++ b/board/xilinx/zynq/zynq-dlc20-rev1.0/ps7_init_gpl.c @@ -0,0 +1,280 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. + */ + +#include + +static unsigned long ps7_pll_init_data_3_0[] = { + EMIT_WRITE(0xF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U), + EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U), + EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000001U), + EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U), + EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U), + EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U), + EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000002U), + EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U), + EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U), + EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U), + EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000004U), + EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U), + EMIT_WRITE(0xF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_clock_init_data_3_0[] = { + EMIT_WRITE(0xF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U), + EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U), + EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U), + EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00000A01U), + EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000A02U), + EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U), + EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00200500U), + EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01EC044DU), + EMIT_WRITE(0xF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_ddr_init_data_3_0[] = { + EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U), + EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U), + EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU), + EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U), + EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U), + EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004159AU), + EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D2U), + EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U), + EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U), + EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U), + EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U), + EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U), + EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U), + EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U), + EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U), + EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U), + EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0FF66666U), + EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U), + EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U), + EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U), + EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U), + EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU), + EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U), + EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U), + EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U), + EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U), + EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U), + EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U), + EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U), + EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU), + EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U), + EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U), + EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U), + EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U), + EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x00029000U), + EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00029000U), + EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x00029000U), + EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00029000U), + EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x00000080U), + EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x00000080U), + EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x00000080U), + EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x00000080U), + EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x000000F9U), + EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x000000F9U), + EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x000000F9U), + EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x000000F9U), + EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000C0U), + EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000C0U), + EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000C0U), + EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000C0U), + EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U), + EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U), + EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U), + EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U), + EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U), + EMIT_MASKPOLL(0xF8000B74, 0x00002000U), + EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U), + EMIT_MASKPOLL(0xF8006054, 0x00000007U), + EMIT_EXIT(), +}; + +static unsigned long ps7_mio_init_data_3_0[] = { + EMIT_WRITE(0xF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C068U), + EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F98068U), + EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U), + EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U), + EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U), + EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001200U), + EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000202U), + EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000202U), + EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000202U), + EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000202U), + EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000202U), + EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000200U), + EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x000002E0U), + EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x000012E1U), + EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x00001200U), + EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x00001200U), + EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001200U), + EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001200U), + EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001240U), + EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001240U), + EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001202U), + EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001203U), + EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001205U), + EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001205U), + EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001205U), + EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001204U), + EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007B8, 0x00003F01U, 0x00001201U), + EMIT_MASKWRITE(0xF80007BC, 0x00003F01U, 0x00001201U), + EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x00001200U), + EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x00001200U), + EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00001218U), + EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00001200U), + EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001280U), + EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x002E002FU), + EMIT_WRITE(0xF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_peripherals_init_data_3_0[] = { + EMIT_WRITE(0xF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), + EMIT_WRITE(0xF8000004, 0x0000767BU), + EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U), + EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_EXIT(), +}; + +static unsigned long ps7_post_config_3_0[] = { + EMIT_WRITE(0xF8000008, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU), + EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U), + EMIT_WRITE(0xF8000004, 0x0000767BU), + EMIT_EXIT(), +}; + +int ps7_post_config(void) +{ + int ret = -1; + + ret = ps7_config(ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + return PS7_INIT_SUCCESS; +} + +int ps7_init(void) +{ + int ret; + + ret = ps7_config(ps7_mio_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_pll_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_clock_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_ddr_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + ret = ps7_config(ps7_peripherals_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + return PS7_INIT_SUCCESS; +} diff --git a/configs/zynq_dlc20_rev1_0_defconfig b/configs/zynq_dlc20_rev1_0_defconfig new file mode 100644 index 0000000..4b9fdfe --- /dev/null +++ b/configs/zynq_dlc20_rev1_0_defconfig @@ -0,0 +1,74 @@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQ=y +CONFIG_SYS_TEXT_BASE=0x4000000 +CONFIG_SPL=y +CONFIG_DEBUG_UART_BASE=0xe0001000 +CONFIG_DEBUG_UART_CLOCK=50000000 +CONFIG_IDENT_STRING=" Xilinx Zynq DLC20 Rev1.0" +CONFIG_SPL_STACK_R_ADDR=0x200000 +CONFIG_DEBUG_UART=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_PROMPT="Zynq> " +CONFIG_CMD_THOR_DOWNLOAD=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADFS=y +CONFIG_CMD_FPGA_LOADMK=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="zynq-dlc20-rev1.0" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQPL=y +CONFIG_DM_GPIO=y +CONFIG_SYS_I2C_ZYNQ=y +CONFIG_ZYNQ_I2C0=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_REALTEK=y +CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ZYNQ_SERIAL=y +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Xilinx" +CONFIG_USB_GADGET_VENDOR_NUM=0x03fd +CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_THOR=y From e7f327fe4d3a30c36f871354b2cd3d64394fec40 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 28 Feb 2017 11:46:37 +0100 Subject: [PATCH 04/14] arm: zynq: Add efuse node for Zynq-7000S devices Add access to efuse for Zynq-7000S device detection. Signed-off-by: Michal Simek --- arch/arm/dts/zynq-7000.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 47e8c18..286059d 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -323,6 +323,11 @@ syscon = <&slcr>; }; + efuse: efuse@f800d000 { + compatible = "xlnx,zynq-efuse"; + reg = <0xf800d000 0x20>; + }; + global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; From 7e029e970596000efbe9f0e1b9251cf7c835651a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 4 Oct 2018 09:41:54 +0200 Subject: [PATCH 05/14] xilinx: Sync defconfigs with current Kconfig There are some inconsistencies which should be fixed. Signed-off-by: Michal Simek --- configs/avnet_ultra96_rev1_defconfig | 2 +- configs/microblaze-generic_defconfig | 2 +- configs/xilinx_zynqmp_zcu100_revC_defconfig | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/configs/avnet_ultra96_rev1_defconfig b/configs/avnet_ultra96_rev1_defconfig index a86719b..7c325dd 100644 --- a/configs/avnet_ultra96_rev1_defconfig +++ b/configs/avnet_ultra96_rev1_defconfig @@ -20,7 +20,6 @@ CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_BOOTMENU=y -CONFIG_CMD_POWEROFF=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y @@ -30,6 +29,7 @@ CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 7cd5e6d..ae61c25 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -44,9 +44,9 @@ CONFIG_DM_GPIO=y CONFIG_XILINX_GPIO=y CONFIG_LED=y CONFIG_LED_GPIO=y +CONFIG_MTD_PARTITIONS=y CONFIG_MTD_NOR_FLASH=y CONFIG_MTD_DEVICE=y -CONFIG_MTD_PARTITIONS=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_DAVICOM=y diff --git a/configs/xilinx_zynqmp_zcu100_revC_defconfig b/configs/xilinx_zynqmp_zcu100_revC_defconfig index 48508b5..ad8c8f7 100644 --- a/configs/xilinx_zynqmp_zcu100_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu100_revC_defconfig @@ -20,7 +20,6 @@ CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_ATF=y CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_BOOTMENU=y -CONFIG_CMD_POWEROFF=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y @@ -30,6 +29,7 @@ CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y From 3d80a1771240e5a4b42a4a04713cf487a08136e9 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 27 Jun 2018 15:53:59 +0200 Subject: [PATCH 06/14] arm64: zynqmp: Enable CDC ethernet gadget for zcu100/Ultra96 Ethernet is not present on this board that's why there are two other options how to wire the board to ethernet. The first is asix_eth usb host converter which is already enabled by default. The second option is to use USB CDC/RNDIS ethernet gadget. This patch is enabling CDC which is working with Linux. With new bind/unbind command there is no need to call usb_ether_init() from platform code and use for example these commands: bind /amba/usb0@ff9d0000/dwc3@fe200000 usb_ether dhcp unbind /amba/usb0@ff9d0000/dwc3@fe200000 Signed-off-by: Michal Simek --- configs/avnet_ultra96_rev1_defconfig | 5 +++++ configs/xilinx_zynqmp_zcu100_revC_defconfig | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/configs/avnet_ultra96_rev1_defconfig b/configs/avnet_ultra96_rev1_defconfig index 7c325dd..5a34cde 100644 --- a/configs/avnet_ultra96_rev1_defconfig +++ b/configs/avnet_ultra96_rev1_defconfig @@ -21,6 +21,7 @@ CONFIG_SPL_ATF=y CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_BOOTMENU=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_BIND=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set @@ -66,6 +67,8 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_DM_ETH=y +# CONFIG_NETDEVICES is not set CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y @@ -84,6 +87,8 @@ CONFIG_USB_ULPI=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_ETHER=y +CONFIG_USB_ETH_CDC=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_WDT=y diff --git a/configs/xilinx_zynqmp_zcu100_revC_defconfig b/configs/xilinx_zynqmp_zcu100_revC_defconfig index ad8c8f7..abaaa34 100644 --- a/configs/xilinx_zynqmp_zcu100_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu100_revC_defconfig @@ -21,6 +21,7 @@ CONFIG_SPL_ATF=y CONFIG_SYS_PROMPT="ZynqMP> " CONFIG_CMD_BOOTMENU=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_BIND=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y # CONFIG_CMD_FLASH is not set @@ -66,6 +67,8 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_DM_ETH=y +# CONFIG_NETDEVICES is not set CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y @@ -84,6 +87,8 @@ CONFIG_USB_ULPI=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_ETHER=y +CONFIG_USB_ETH_CDC=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_WDT=y From e6149576e8dab0684e885b206b0fcde0c16402c1 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 7 Sep 2017 09:20:32 +0200 Subject: [PATCH 07/14] arm64: gic: Do gicv3 secure initialization based on EL level Do gic cpu initialization based on EL level which u-boot enters. U-Boot can't access EL3 regs when runs in EL2/EL1, etc. Signed-off-by: Michal Simek --- arch/arm/lib/gic_64.S | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S index 745c785..155212a 100644 --- a/arch/arm/lib/gic_64.S +++ b/arch/arm/lib/gic_64.S @@ -107,6 +107,8 @@ ENTRY(gic_init_secure_percpu) mov w11, #0x1 /* Enable SGI 0 */ str w11, [x10, GICR_ISENABLERn] + switch_el x10, 3f, 2f, 1f +3: /* Initialize Cpu Interface */ mrs x10, ICC_SRE_EL3 orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */ @@ -114,19 +116,19 @@ ENTRY(gic_init_secure_percpu) msr ICC_SRE_EL3, x10 isb - mrs x10, ICC_SRE_EL2 - orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */ - /* Allow EL1 access to ICC_SRE_EL1 */ - msr ICC_SRE_EL2, x10 - isb - mov x10, #0x3 /* EnableGrp1NS | EnableGrp1S */ msr ICC_IGRPEN1_EL3, x10 isb msr ICC_CTLR_EL3, xzr isb - +2: + mrs x10, ICC_SRE_EL2 + orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */ + /* Allow EL1 access to ICC_SRE_EL1 */ + msr ICC_SRE_EL2, x10 + isb +1: msr ICC_CTLR_EL1, xzr /* NonSecure ICC_CTLR_EL1 */ isb From ec48b6c991f400c8583ac2f875d65a8539f0b437 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 22 Aug 2018 14:55:27 +0200 Subject: [PATCH 08/14] arm64: versal: Add support for new Xilinx Versal ACAPs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex™-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. The patch is adding necessary infrastructure in place without enabling platform which is done in separate patch. Signed-off-by: Michal Simek --- Kconfig | 2 +- MAINTAINERS | 6 ++ arch/arm/Kconfig | 10 +++ arch/arm/Makefile | 1 + arch/arm/mach-versal/Kconfig | 39 ++++++++++++ arch/arm/mach-versal/Makefile | 8 +++ arch/arm/mach-versal/clk.c | 30 +++++++++ arch/arm/mach-versal/cpu.c | 69 ++++++++++++++++++++ arch/arm/mach-versal/include/mach/gpio.h | 6 ++ arch/arm/mach-versal/include/mach/hardware.h | 34 ++++++++++ arch/arm/mach-versal/include/mach/sys_proto.h | 6 ++ board/xilinx/versal/MAINTAINERS | 7 +++ board/xilinx/versal/Makefile | 7 +++ board/xilinx/versal/board.c | 81 ++++++++++++++++++++++++ drivers/mmc/Kconfig | 2 +- drivers/net/Kconfig | 2 +- drivers/spi/Kconfig | 4 +- env/Kconfig | 4 +- include/configs/xilinx_versal.h | 91 +++++++++++++++++++++++++++ 19 files changed, 402 insertions(+), 7 deletions(-) create mode 100644 arch/arm/mach-versal/Kconfig create mode 100644 arch/arm/mach-versal/Makefile create mode 100644 arch/arm/mach-versal/clk.c create mode 100644 arch/arm/mach-versal/cpu.c create mode 100644 arch/arm/mach-versal/include/mach/gpio.h create mode 100644 arch/arm/mach-versal/include/mach/hardware.h create mode 100644 arch/arm/mach-versal/include/mach/sys_proto.h create mode 100644 board/xilinx/versal/MAINTAINERS create mode 100644 board/xilinx/versal/Makefile create mode 100644 board/xilinx/versal/board.c create mode 100644 include/configs/xilinx_versal.h diff --git a/Kconfig b/Kconfig index 1aadf5d..dca9bb4 100644 --- a/Kconfig +++ b/Kconfig @@ -144,7 +144,7 @@ config SYS_MALLOC_F_LEN config SYS_MALLOC_LEN hex "Define memory for Dynamic allocation" - depends on ARCH_ZYNQ + depends on ARCH_ZYNQ || ARCH_VERSAL help This defines memory to be allocated for Dynamic allocation TODO: Use for other architectures diff --git a/MAINTAINERS b/MAINTAINERS index ace7d9a..fcb963e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -287,6 +287,12 @@ F: arch/arm/mach-uniphier/ F: configs/uniphier_*_defconfig N: uniphier +ARM VERSAL +M: Michal Simek +S: Maintained +T: git git://git.denx.de/u-boot-microblaze.git +F: arch/arm/mach-versal/ + ARM VERSATILE EXPRESS DRIVERS M: Liviu Dudau S: Maintained diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ccf2a84..3ba8efd 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -853,6 +853,14 @@ config ARCH_SUNXI imply SPL_SERIAL_SUPPORT imply USB_GADGET +config ARCH_VERSAL + bool "Support Xilinx Versal Platform" + select ARM64 + select CLK + select DM + select DM_SERIAL + select OF_CONTROL + config ARCH_VF610 bool "Freescale Vybrid" select CPU_V7A @@ -1449,6 +1457,8 @@ source "arch/arm/cpu/armv7/vf610/Kconfig" source "arch/arm/mach-zynq/Kconfig" +source "arch/arm/mach-versal/Kconfig" + source "arch/arm/mach-zynqmp-r5/Kconfig" source "arch/arm/cpu/armv7/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 8f50560..e52a35d 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -80,6 +80,7 @@ machine-$(CONFIG_ARCH_STM32MP) += stm32mp machine-$(CONFIG_TEGRA) += tegra machine-$(CONFIG_ARCH_UNIPHIER) += uniphier machine-$(CONFIG_ARCH_ZYNQ) += zynq +machine-$(CONFIG_ARCH_VERSAL) += versal machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig new file mode 100644 index 0000000..04dbaea --- /dev/null +++ b/arch/arm/mach-versal/Kconfig @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0+ + +if ARCH_VERSAL + +config SYS_BOARD + string "Board name" + default "versal" + +config SYS_VENDOR + string "Vendor name" + default "xilinx" + +config SYS_SOC + default "versal" + +config SYS_CONFIG_NAME + string "Board configuration name" + default "xilinx_versal" + help + This option contains information about board configuration name. + Based on this option include/configs/.h header + will be used for board configuration. + +config GICV3 + def_bool y + +config SYS_MALLOC_LEN + default 0x2000000 + +config COUNTER_FREQUENCY + int "Timer clock frequency" + default 0 + help + Setup time clock frequency for certain platform + +config ZYNQ_SDHCI_MAX_FREQ + default 200000000 + +endif diff --git a/arch/arm/mach-versal/Makefile b/arch/arm/mach-versal/Makefile new file mode 100644 index 0000000..c230239 --- /dev/null +++ b/arch/arm/mach-versal/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2016 - 2018 Xilinx, Inc. +# Michal Simek +# + +obj-y += clk.o +obj-y += cpu.o diff --git a/arch/arm/mach-versal/clk.c b/arch/arm/mach-versal/clk.c new file mode 100644 index 0000000..b82cea4 --- /dev/null +++ b/arch/arm/mach-versal/clk.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 - 2018 Xilinx, Inc. + * Michal Simek + */ + +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_CLOCKS +/** + * set_cpu_clk_info - Initialize clock framework + * + * Return: 0 always. + * + * This function is called from common code after relocation and sets up the + * clock framework. The framework must not be used before this function had been + * called. + */ +int set_cpu_clk_info(void) +{ + gd->cpu_clk = get_tbclk(); + + gd->bd->bi_arm_freq = gd->cpu_clk / 1000000; + gd->bd->bi_dsp_freq = 0; + + return 0; +} +#endif diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c new file mode 100644 index 0000000..959570e --- /dev/null +++ b/arch/arm/mach-versal/cpu.c @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 - 2018 Xilinx, Inc. + * Michal Simek + */ + +#include +#include +#include + +static struct mm_region versal_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x70000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0xf0000000UL, + .phys = 0xf0000000UL, + .size = 0x0fe00000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0xffe00000UL, + .phys = 0xffe00000UL, + .size = 0x00200000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x400000000UL, + .phys = 0x400000000UL, + .size = 0x200000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x600000000UL, + .phys = 0x600000000UL, + .size = 0x800000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xe00000000UL, + .phys = 0xe00000000UL, + .size = 0xf200000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = versal_mem_map; + +u64 get_page_table_size(void) +{ + return 0x14000; +} diff --git a/arch/arm/mach-versal/include/mach/gpio.h b/arch/arm/mach-versal/include/mach/gpio.h new file mode 100644 index 0000000..677facb --- /dev/null +++ b/arch/arm/mach-versal/include/mach/gpio.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 - 2018 Xilinx, Inc. + */ + +/* Empty file - for compilation */ diff --git a/arch/arm/mach-versal/include/mach/hardware.h b/arch/arm/mach-versal/include/mach/hardware.h new file mode 100644 index 0000000..aad7426 --- /dev/null +++ b/arch/arm/mach-versal/include/mach/hardware.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 - 2018 Xilinx, Inc. + */ + +#define VERSAL_CRL_APB_BASEADDR 0xFF5E0000 + +#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT BIT(25) + +#define IOU_SWITCH_CTRL_CLKACT_BIT BIT(25) +#define IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 + +struct crlapb_regs { + u32 reserved0[69]; + u32 iou_switch_ctrl; /* 0x114 */ + u32 reserved1[13]; + u32 timestamp_ref_ctrl; /* 0x14c */ + u32 reserved2[126]; + u32 rst_timestamp; /* 0x348 */ +}; + +#define crlapb_base ((struct crlapb_regs *)VERSAL_CRL_APB_BASEADDR) + +#define VERSAL_IOU_SCNTR_SECURE 0xFF140000 + +#define IOU_SCNTRS_CONTROL_EN 1 + +struct iou_scntrs_regs { + u32 counter_control_register; /* 0x0 */ + u32 reserved0[7]; + u32 base_frequency_id_register; /* 0x20 */ +}; + +#define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL_IOU_SCNTR_SECURE) diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h new file mode 100644 index 0000000..677facb --- /dev/null +++ b/arch/arm/mach-versal/include/mach/sys_proto.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 - 2018 Xilinx, Inc. + */ + +/* Empty file - for compilation */ diff --git a/board/xilinx/versal/MAINTAINERS b/board/xilinx/versal/MAINTAINERS new file mode 100644 index 0000000..2d2b808 --- /dev/null +++ b/board/xilinx/versal/MAINTAINERS @@ -0,0 +1,7 @@ +XILINX_VERSAL BOARDS +M: Michal Simek +S: Maintained +F: arch/arm/dts/versal* +F: board/xilinx/versal/ +F: include/configs/xilinx_versal* +F: configs/xilinx_versal* diff --git a/board/xilinx/versal/Makefile b/board/xilinx/versal/Makefile new file mode 100644 index 0000000..2b81276 --- /dev/null +++ b/board/xilinx/versal/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2016 - 2018 Xilinx, Inc. +# Michal Simek +# + +obj-y := board.o diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c new file mode 100644 index 0000000..2b3a40b --- /dev/null +++ b/board/xilinx/versal/board.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2014 - 2018 Xilinx, Inc. + * Michal Simek + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + printf("EL Level:\tEL%d\n", current_el()); + + return 0; +} + +int board_early_init_r(void) +{ + if (current_el() == 3) { + u32 val; + + writel(IOU_SWITCH_CTRL_CLKACT_BIT | + (0x20 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), + &crlapb_base->iou_switch_ctrl); + + /* Global timer init - Program time stamp reference clk */ + val = readl(&crlapb_base->timestamp_ref_ctrl); + val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; + writel(val, &crlapb_base->timestamp_ref_ctrl); + + debug("ref ctrl 0x%x\n", + readl(&crlapb_base->timestamp_ref_ctrl)); + + /* Clear reset of timestamp reg */ + writel(0, &crlapb_base->rst_timestamp); + + /* + * Program freq register in System counter and + * enable system counter. + */ + writel(COUNTER_FREQUENCY, + &iou_scntr_secure->base_frequency_id_register); + + debug("counter val 0x%x\n", + readl(&iou_scntr_secure->base_frequency_id_register)); + + writel(IOU_SCNTRS_CONTROL_EN, + &iou_scntr_secure->counter_control_register); + + debug("scntrs control 0x%x\n", + readl(&iou_scntr_secure->counter_control_register)); + debug("timer 0x%llx\n", get_ticks()); + debug("timer 0x%llx\n", get_ticks()); + } + + return 0; +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + + return 0; +} + +int dram_init(void) +{ + if (fdtdec_setup_mem_size_base() != 0) + return -EINVAL; + + return 0; +} + +void reset_cpu(ulong addr) +{ +} diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 0a0d4aa..27246ee 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -538,7 +538,7 @@ config MMC_SDHCI_TEGRA config MMC_SDHCI_ZYNQ bool "Arasan SDHCI controller support" - depends on ARCH_ZYNQ || ARCH_ZYNQMP + depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL depends on DM_MMC && OF_CONTROL && BLK depends on MMC_SDHCI help diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 5441da4..f1f0e2d 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -344,7 +344,7 @@ config XILINX_EMACLITE This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs. config ZYNQ_GEM - depends on DM_ETH && (ARCH_ZYNQ || ARCH_ZYNQMP) + depends on DM_ETH && (ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL) select PHYLIB bool "Xilinx Ethernet GEM" help diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 1df6876..516188e 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -243,7 +243,7 @@ config XILINX_SPI config ZYNQ_SPI bool "Zynq SPI driver" - depends on ARCH_ZYNQ || ARCH_ZYNQMP + depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL help Enable the Zynq SPI driver. This driver can be used to access the SPI NOR flash on platforms embedding this Zynq @@ -260,7 +260,7 @@ config ZYNQ_QSPI config ZYNQMP_GQSPI bool "Configure ZynqMP Generic QSPI" - depends on ARCH_ZYNQMP + depends on ARCH_ZYNQMP || ARCH_VERSAL help This option is used to enable ZynqMP QSPI controller driver which is used to communicate with qspi flash devices. diff --git a/env/Kconfig b/env/Kconfig index f23be00..9011109 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -431,7 +431,7 @@ config ENV_EXT4_FILE It's a string of the EXT4 file name. This file use to store the environment (explicit path to the file) -if ARCH_ROCKCHIP || ARCH_SUNXI || ARCH_ZYNQ || ARCH_ZYNQMP +if ARCH_ROCKCHIP || ARCH_SUNXI || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL config ENV_OFFSET hex "Environment Offset" @@ -448,7 +448,7 @@ config ENV_SIZE hex "Environment Size" default 0x40000 if ENV_IS_IN_SPI_FLASH && ARCH_ZYNQMP default 0x20000 if ARCH_SUNXI || ARCH_ZYNQ - default 0x8000 if ARCH_ROCKCHIP || ARCH_ZYNQMP + default 0x8000 if ARCH_ROCKCHIP || ARCH_ZYNQMP || ARCH_VERSAL help Size of the environment storage area diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h new file mode 100644 index 0000000..bfe4c43 --- /dev/null +++ b/include/configs/xilinx_versal.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration for Xilinx Versal + * (C) Copyright 2016 - 2018 Xilinx, Inc. + * Michal Simek + * + * Based on Configuration for Xilinx ZynqMP + */ + +#ifndef __XILINX_VERSAL_H +#define __XILINX_VERSAL_H + +#define CONFIG_REMAKE_ELF + +/* #define CONFIG_ARMV8_SWITCH_TO_EL1 */ + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0xF9000000 +#define GICR_BASE 0xF9080000 + +#define CONFIG_SYS_MEMTEST_SCRATCH 0xfffc0000 + +#define CONFIG_SYS_MEMTEST_START 0 +#define CONFIG_SYS_MEMTEST_END 1000 + +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE + +/* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */ +#if CONFIG_COUNTER_FREQUENCY +# define COUNTER_FREQUENCY CONFIG_COUNTER_FREQUENCY +#endif + +/* Serial setup */ +#define CONFIG_ARM_DCC +#define CONFIG_CPU_ARMV8 + +#define CONFIG_SYS_BAUDRATE_TABLE \ + { 4800, 9600, 19200, 38400, 57600, 115200 } + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MAY_FAIL + +#define CONFIG_IP_DEFRAG +#define CONFIG_TFTP_BLOCKSIZE 4096 + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR 0x8000000 + +/* Monitor Command Prompt */ +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_MAXARGS 64 + +/* Ethernet driver */ +#if defined(CONFIG_ZYNQ_GEM) +# define CONFIG_NET_MULTI +# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +# define PHY_ANEG_TIMEOUT 20000 +#endif + +#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) + +#define CONFIG_CLOCKS + +#define ENV_MEM_LAYOUT_SETTINGS \ + "fdt_high=10000000\0" \ + "initrd_high=10000000\0" \ + "fdt_addr_r=0x40000000\0" \ + "pxefile_addr_r=0x10000000\0" \ + "kernel_addr_r=0x18000000\0" \ + "scriptaddr=0x02000000\0" \ + "ramdisk_addr_r=0x02100000\0" + +#define BOOT_TARGET_DEVICES(func) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include + +/* Initial environment variables */ +#ifndef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + BOOTENV +#endif + +#endif /* __XILINX_VERSAL_H */ From 3dc80934f4651a3ef243a393be04b1f7f71daf24 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 22 Aug 2018 16:18:34 +0200 Subject: [PATCH 09/14] net: gem: Do not setup any clock for Xilinx SoC Versal Xilinx SoC Versal is using fixed clock where setting rate is not supported. That's why workaround the driver till real clock driver is supported. Signed-off-by: Michal Simek --- drivers/net/zynq_gem.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index e22d048..bc33126 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -461,6 +461,7 @@ static int zynq_gem_init(struct udevice *dev) break; } +#if !defined(CONFIG_ARCH_VERSAL) ret = clk_set_rate(&priv->clk, clk_rate); if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) { dev_err(dev, "failed to set tx clock rate\n"); @@ -472,6 +473,9 @@ static int zynq_gem_init(struct udevice *dev) dev_err(dev, "failed to enable tx clock\n"); return ret; } +#else + debug("requested clk_rate %ld\n", clk_rate); +#endif setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | ZYNQ_GEM_NWCTRL_TXEN_MASK); From ddccf5ef90b6df10fe7a58fe112d2d4013e4f154 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 18 Sep 2018 14:58:16 +0200 Subject: [PATCH 10/14] arm64: versal: Add Xilinx Versal Virtual QEMU board Virtual QEMU board is generating DTB self and putting it to VERSAL_QEMU_DTB_ADDR address. Board is using CONFIG_OF_BOARD which ensures that u-boot is aligned with board created by QEMU. Signed-off-by: Michal Simek --- arch/arm/mach-versal/Kconfig | 5 +++ arch/arm/mach-versal/cpu.c | 14 ++++++++ configs/xilinx_versal_virt_defconfig | 68 ++++++++++++++++++++++++++++++++++++ 3 files changed, 87 insertions(+) create mode 100644 configs/xilinx_versal_virt_defconfig diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig index 04dbaea..9cee97b 100644 --- a/arch/arm/mach-versal/Kconfig +++ b/arch/arm/mach-versal/Kconfig @@ -36,4 +36,9 @@ config COUNTER_FREQUENCY config ZYNQ_SDHCI_MAX_FREQ default 200000000 +config VERSAL_OF_BOARD_DTB_ADDR + hex + default 0x1000 + depends on OF_BOARD + endif diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index 959570e..1fd3c24 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -67,3 +67,17 @@ u64 get_page_table_size(void) { return 0x14000; } + +#if defined(CONFIG_OF_BOARD) +void *board_fdt_blob_setup(void) +{ + static void *fw_dtb = (void *)CONFIG_VERSAL_OF_BOARD_DTB_ADDR; + + if (fdt_magic(fw_dtb) != FDT_MAGIC) { + printf("DTB is not passed via %llx\n", (u64)fw_dtb); + return NULL; + } + + return fw_dtb; +} +#endif diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig new file mode 100644 index 0000000..668c313 --- /dev/null +++ b/configs/xilinx_versal_virt_defconfig @@ -0,0 +1,68 @@ +CONFIG_ARM=y +CONFIG_ARCH_VERSAL=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=0 +CONFIG_COUNTER_FREQUENCY=62500000 +CONFIG_DEBUG_UART=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_BOOTDELAY=-1 +CONFIG_SUPPORT_RAW_INITRD=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Versal> " +CONFIG_CMD_BOOTMENU=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +# CONFIG_PARTITION_UUIDS is not set +CONFIG_OF_BOARD=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DM_GPIO=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_MII=y +CONFIG_ZYNQ_GEM=y +CONFIG_DEBUG_UART_PL011=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_PL01X_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FAT_WRITE=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y From 12ad2994a5f01f949c3865851898bdae5ded1ddc Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Fri, 5 Oct 2018 15:09:04 +0530 Subject: [PATCH 11/14] arm64: zynqmp: Move TCM initialization to a separate routine This patch moves TCM initialization to a separate routine to make it modular and can be reused if required. It also prints warning message now as it writes to TCM. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- arch/arm/cpu/armv8/zynqmp/cpu.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index 43ba739..3ed631e 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -105,10 +105,16 @@ u64 get_page_table_size(void) } #ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU -int reserve_mmu(void) +static void tcm_init(u8 mode) { - initialize_tcm(TCM_LOCK); + puts("WARNING: Initializing TCM overwrites TCM content\n"); + initialize_tcm(mode); memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE); +} + +int reserve_mmu(void) +{ + tcm_init(TCM_LOCK); gd->arch.tlb_size = PGTABLE_SIZE; gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR; From 5860bc16b918bb5456a4a77930eafd7c858f70db Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Fri, 5 Oct 2018 15:09:05 +0530 Subject: [PATCH 12/14] arm64: zynqmp: Add new command for TCM initialization This patch adds new zynqmp command "zynqmp tcminit mode" to initialize TCM. TCM needs to be initialized before accessing to avoid ECC errors. This new command helps to perform the same. It also makes tcm_init() as global and uses it for doing the TCM initialization. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- arch/arm/cpu/armv8/zynqmp/cpu.c | 6 +++-- arch/arm/include/asm/arch-zynqmp/sys_proto.h | 3 +++ board/xilinx/zynqmp/cmds.c | 37 +++++++++++++++++++++++++++- 3 files changed, 43 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index 3ed631e..4ee8e3f 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -104,14 +104,16 @@ u64 get_page_table_size(void) return 0x14000; } -#ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU -static void tcm_init(u8 mode) +#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP) +void tcm_init(u8 mode) { puts("WARNING: Initializing TCM overwrites TCM content\n"); initialize_tcm(mode); memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE); } +#endif +#ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU int reserve_mmu(void) { tcm_init(TCM_LOCK); diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index 9fa44d0..385c882 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -68,5 +68,8 @@ int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, void initialize_tcm(bool mode); void mem_map_fill(void); int chip_id(unsigned char id); +#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP) +void tcm_init(u8 mode); +#endif #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c index f8c8674..3e039cc 100644 --- a/board/xilinx/zynqmp/cmds.c +++ b/board/xilinx/zynqmp/cmds.c @@ -6,6 +6,7 @@ #include #include +#include #include #include @@ -102,10 +103,36 @@ static int do_zynqmp_mmio_write(cmd_tbl_t *cmdtp, int flag, int argc, return ret; } +#ifdef CONFIG_DEFINE_TCM_OCM_MMAP +static int do_zynqmp_tcm_init(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + u8 mode; + + if (argc != cmdtp->maxargs) + return CMD_RET_USAGE; + + mode = simple_strtoul(argv[2], NULL, 16); + if (mode != TCM_LOCK && mode != TCM_SPLIT) { + printf("Mode should be either 0(lock)/1(split)\n"); + return CMD_RET_FAILURE; + } + + dcache_disable(); + tcm_init(mode); + dcache_enable(); + + return CMD_RET_SUCCESS; +} +#endif + static cmd_tbl_t cmd_zynqmp_sub[] = { U_BOOT_CMD_MKENT(secure, 5, 0, do_zynqmp_verify_secure, "", ""), U_BOOT_CMD_MKENT(mmio_read, 3, 0, do_zynqmp_mmio_read, "", ""), U_BOOT_CMD_MKENT(mmio_write, 5, 0, do_zynqmp_mmio_write, "", ""), +#ifdef CONFIG_DEFINE_TCM_OCM_MMAP + U_BOOT_CMD_MKENT(tcminit, 3, 0, do_zynqmp_tcm_init, "", ""), +#endif }; /** @@ -145,7 +172,15 @@ static char zynqmp_help_text[] = " be used for decryption\n" "zynqmp mmio_read address - read from address\n" "zynqmp mmio_write address mask value - write value after masking to\n" - " address\n"; + " address\n" +#ifdef CONFIG_DEFINE_TCM_OCM_MMAP + "zynqmp tcminit mode - Initialize the TCM with zeros. TCM needs to be\n" + " initialized before accessing to avoid ECC\n" + " errors. mode specifies in which mode TCM has\n" + " to be initialized. Supported modes will be\n" + " lock(0)/split(1)\n" +#endif + ; #endif U_BOOT_CMD( From 22270ca03665c55e713eca2e3b0a31ed6addd621 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 4 Oct 2018 14:26:13 +0200 Subject: [PATCH 13/14] arm64: zynqmp: Enable MP by default via Kconfig Simplify defconfig for ZynqMP but keep option not to enable it for mini targets. Signed-off-by: Michal Simek --- arch/arm/Kconfig | 1 + configs/avnet_ultra96_rev1_defconfig | 1 - configs/xilinx_zynqmp_mini_emmc0_defconfig | 1 + configs/xilinx_zynqmp_mini_emmc1_defconfig | 1 + configs/xilinx_zynqmp_mini_nand_defconfig | 1 + configs/xilinx_zynqmp_mini_qspi_defconfig | 1 - configs/xilinx_zynqmp_zc1232_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1254_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1275_revA_defconfig | 1 - configs/xilinx_zynqmp_zc1275_revB_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 - configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 1 - configs/xilinx_zynqmp_zcu100_revC_defconfig | 1 - configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 - configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu104_revC_defconfig | 1 - configs/xilinx_zynqmp_zcu106_revA_defconfig | 1 - configs/xilinx_zynqmp_zcu111_revA_defconfig | 1 - 23 files changed, 4 insertions(+), 19 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3ba8efd..c7168e0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -919,6 +919,7 @@ config ARCH_ZYNQMP imply BOARD_LATE_INIT imply CMD_DM imply FAT_WRITE + imply MP config TEGRA bool "NVIDIA Tegra" diff --git a/configs/avnet_ultra96_rev1_defconfig b/configs/avnet_ultra96_rev1_defconfig index 5a34cde..c49c9f2 100644 --- a/configs/avnet_ultra96_rev1_defconfig +++ b/configs/avnet_ultra96_rev1_defconfig @@ -36,7 +36,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y -CONFIG_MP=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig index c0ec79c..917637d 100644 --- a/configs/xilinx_zynqmp_mini_emmc0_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig @@ -39,6 +39,7 @@ CONFIG_CMD_MMC=y # CONFIG_CMD_ITEST is not set # CONFIG_CMD_SOURCE is not set # CONFIG_CMD_SETEXPR is not set +# CONFIG_MP is not set CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_EMBED=y diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig index c1f5e64..1ffa528 100644 --- a/configs/xilinx_zynqmp_mini_emmc1_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig @@ -39,6 +39,7 @@ CONFIG_CMD_MMC=y # CONFIG_CMD_ITEST is not set # CONFIG_CMD_SOURCE is not set # CONFIG_CMD_SETEXPR is not set +# CONFIG_MP is not set CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_EMBED=y diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig index e119ec1..74ba0c9 100644 --- a/configs/xilinx_zynqmp_mini_nand_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_defconfig @@ -39,6 +39,7 @@ CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_ITEST is not set # CONFIG_CMD_SOURCE is not set # CONFIG_CMD_SETEXPR is not set +# CONFIG_MP is not set # CONFIG_PARTITIONS is not set CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand" diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index 9fcc7c2..db129b6 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -42,7 +42,6 @@ CONFIG_CMD_SF=y # CONFIG_CMD_SOURCE is not set # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_MISC is not set -CONFIG_MP=y # CONFIG_PARTITIONS is not set CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-qspi" diff --git a/configs/xilinx_zynqmp_zc1232_revA_defconfig b/configs/xilinx_zynqmp_zc1232_revA_defconfig index 2aeee19..7521fc4 100644 --- a/configs/xilinx_zynqmp_zc1232_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1232_revA_defconfig @@ -25,7 +25,6 @@ CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y # CONFIG_CMD_NET is not set CONFIG_CMD_TIME=y -CONFIG_MP=y CONFIG_CMD_TIMER=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y diff --git a/configs/xilinx_zynqmp_zc1254_revA_defconfig b/configs/xilinx_zynqmp_zc1254_revA_defconfig index e72808d..e0822b9 100644 --- a/configs/xilinx_zynqmp_zc1254_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1254_revA_defconfig @@ -25,7 +25,6 @@ CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y # CONFIG_CMD_NET is not set CONFIG_CMD_TIME=y -CONFIG_MP=y CONFIG_CMD_TIMER=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y diff --git a/configs/xilinx_zynqmp_zc1275_revA_defconfig b/configs/xilinx_zynqmp_zc1275_revA_defconfig index c8746b9..3afed69 100644 --- a/configs/xilinx_zynqmp_zc1275_revA_defconfig +++ b/configs/xilinx_zynqmp_zc1275_revA_defconfig @@ -25,7 +25,6 @@ CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y # CONFIG_CMD_NET is not set CONFIG_CMD_TIME=y -CONFIG_MP=y CONFIG_CMD_TIMER=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y diff --git a/configs/xilinx_zynqmp_zc1275_revB_defconfig b/configs/xilinx_zynqmp_zc1275_revB_defconfig index 053afa7..7e31b11 100644 --- a/configs/xilinx_zynqmp_zc1275_revB_defconfig +++ b/configs/xilinx_zynqmp_zc1275_revB_defconfig @@ -27,7 +27,6 @@ CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_MMC=y # CONFIG_CMD_NET is not set CONFIG_CMD_TIME=y -CONFIG_MP=y CONFIG_CMD_TIMER=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index 28dabdd..ec26dd7 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -35,7 +35,6 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y -CONFIG_MP=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index 89da50d..c2b3d18 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -35,7 +35,6 @@ CONFIG_CMD_NAND_LOCK_UNLOCK=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y -CONFIG_MP=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig index e9af979..b853e2f 100644 --- a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig @@ -32,7 +32,6 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y -CONFIG_MP=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig index 445b6b0..a0bbc0f 100644 --- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig @@ -27,7 +27,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y -CONFIG_MP=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig index 491619c..0625d19 100644 --- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig @@ -28,7 +28,6 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y -CONFIG_MP=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/xilinx_zynqmp_zcu100_revC_defconfig b/configs/xilinx_zynqmp_zcu100_revC_defconfig index abaaa34..dc1e7cd 100644 --- a/configs/xilinx_zynqmp_zcu100_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu100_revC_defconfig @@ -36,7 +36,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y -CONFIG_MP=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig index 409067b..e41366e 100644 --- a/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig +++ b/configs/xilinx_zynqmp_zcu102_rev1_0_defconfig @@ -39,7 +39,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y -CONFIG_MP=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig index 066d6de..02dd5ed 100644 --- a/configs/xilinx_zynqmp_zcu102_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig @@ -38,7 +38,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y -CONFIG_MP=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index bd0bc6d..78deb6a 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -38,7 +38,6 @@ CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y -CONFIG_MP=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/xilinx_zynqmp_zcu104_revA_defconfig b/configs/xilinx_zynqmp_zcu104_revA_defconfig index 86670e1..ff57ca8 100644 --- a/configs/xilinx_zynqmp_zcu104_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revA_defconfig @@ -33,7 +33,6 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y -CONFIG_MP=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/xilinx_zynqmp_zcu104_revC_defconfig b/configs/xilinx_zynqmp_zcu104_revC_defconfig index e566c4a..33258e4 100644 --- a/configs/xilinx_zynqmp_zcu104_revC_defconfig +++ b/configs/xilinx_zynqmp_zcu104_revC_defconfig @@ -33,7 +33,6 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y -CONFIG_MP=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/xilinx_zynqmp_zcu106_revA_defconfig b/configs/xilinx_zynqmp_zcu106_revA_defconfig index f4f923e..210c9a3 100644 --- a/configs/xilinx_zynqmp_zcu106_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu106_revA_defconfig @@ -34,7 +34,6 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y -CONFIG_MP=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/xilinx_zynqmp_zcu111_revA_defconfig b/configs/xilinx_zynqmp_zcu111_revA_defconfig index e643d9f..8bace6d 100644 --- a/configs/xilinx_zynqmp_zcu111_revA_defconfig +++ b/configs/xilinx_zynqmp_zcu111_revA_defconfig @@ -32,7 +32,6 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_TIME=y -CONFIG_MP=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y CONFIG_SPL_OF_CONTROL=y From b92055064e56207e284ae966dbd7bd407a7b0e8d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 4 Oct 2018 14:26:13 +0200 Subject: [PATCH 14/14] cmd: kgdb: Enable kgdb only for PPC Only PPC supports this option that's why there should be proper dependency setup via Kconfig. Signed-off-by: Michal Simek --- cmd/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/cmd/Kconfig b/cmd/Kconfig index 7ed3c9c..d66f710 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1811,6 +1811,7 @@ config CMD_IRQ config CMD_KGDB bool "kgdb - Allow debugging of U-Boot with gdb" + depends on PPC help This enables a 'kgdb' command which allows gdb to connect to U-Boot over a serial link for debugging purposes. This allows