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@ -40,23 +40,21 @@ void init_pllx(void) |
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u32 reg; |
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/* If PLLX is already enabled, just return */ |
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reg = readl(&pll->pll_base); |
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if (reg & PLL_ENABLE) |
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if (readl(&pll->pll_base) & PLL_ENABLE_MASK) |
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return; |
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/* Set PLLX_MISC */ |
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reg = CPCON; /* CPCON[11:8] = 0001 */ |
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writel(reg, &pll->pll_misc); |
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writel(1 << PLL_CPCON_SHIFT, &pll->pll_misc); |
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/* Use 12MHz clock here */ |
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reg = (PLL_BYPASS | PLL_DIVM_VALUE); |
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reg |= (1000 << 8); /* DIVN = 0x3E8 */ |
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reg = PLL_BYPASS_MASK | (12 << PLL_DIVM_SHIFT); |
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reg |= 1000 << PLL_DIVN_SHIFT; |
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writel(reg, &pll->pll_base); |
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reg |= PLL_ENABLE; |
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reg |= PLL_ENABLE_MASK; |
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writel(reg, &pll->pll_base); |
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reg &= ~PLL_BYPASS; |
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reg &= ~PLL_BYPASS_MASK; |
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writel(reg, &pll->pll_base); |
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} |
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@ -90,16 +88,11 @@ static void enable_cpu_clock(int enable) |
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* always stop the clock to CPU 1. |
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*/ |
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clk = readl(&clkrst->crc_clk_cpu_cmplx); |
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clk |= CPU1_CLK_STP; |
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if (enable) { |
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/* Unstop the CPU clock */ |
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clk &= ~CPU0_CLK_STP; |
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} else { |
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/* Stop the CPU clock */ |
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clk |= CPU0_CLK_STP; |
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} |
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clk |= 1 << CPU1_CLK_STP_SHIFT; |
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/* Stop/Unstop the CPU clock */ |
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clk &= ~CPU0_CLK_STP_MASK; |
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clk |= !enable << CPU0_CLK_STP_SHIFT; |
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writel(clk, &clkrst->crc_clk_cpu_cmplx); |
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clock_enable(PERIPH_ID_CPU); |
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@ -177,9 +170,6 @@ static void enable_cpu_power_rail(void) |
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static void reset_A9_cpu(int reset) |
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{ |
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; |
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u32 cpu; |
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/*
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* NOTE: Regardless of whether the request is to hold the CPU in reset |
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* or take it out of reset, every processor in the CPU complex |
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@ -188,19 +178,10 @@ static void reset_A9_cpu(int reset) |
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* are multiple processors in the CPU complex. |
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*/ |
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/* Hold CPU 1 in reset */ |
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cpu = SET_DBGRESET1 | SET_DERESET1 | SET_CPURESET1; |
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writel(cpu, &clkrst->crc_cpu_cmplx_set); |
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if (reset) { |
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/* Now place CPU0 into reset */ |
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cpu |= SET_DBGRESET0 | SET_DERESET0 | SET_CPURESET0; |
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writel(cpu, &clkrst->crc_cpu_cmplx_set); |
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} else { |
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/* Take CPU0 out of reset */ |
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cpu = CLR_DBGRESET0 | CLR_DERESET0 | CLR_CPURESET0; |
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writel(cpu, &clkrst->crc_cpu_cmplx_clr); |
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} |
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/* Hold CPU 1 in reset, and CPU 0 if asked */ |
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reset_cmplx_set_enable(1, crc_rst_cpu | crc_rst_de | crc_rst_debug, 1); |
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reset_cmplx_set_enable(0, crc_rst_cpu | crc_rst_de | crc_rst_debug, |
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reset); |
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/* Enable/Disable master CPU reset */ |
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reset_set_enable(PERIPH_ID_CPU, reset); |
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