Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>master
Magnus Lilja
15 years ago
committed by
Jean-Christophe PLAGNIOL-VILLARD
parent
78eabb90b7
commit
d08e5ca301
@ -1 +1,5 @@ |
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ifdef CONFIG_NAND_SPL |
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TEXT_BASE = 0x87ec0000
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else |
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TEXT_BASE = 0x87f00000
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endif |
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@ -0,0 +1,93 @@ |
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/* |
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* (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <config.h> |
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#include <asm/arch/mx31-regs.h> |
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#include <asm/macro.h> |
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.globl lowlevel_init
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lowlevel_init: |
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/* Also setup the Peripheral Port Remap register inside the core */ |
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ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */ |
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mcr p15, 0, r0, c15, c2, 4 |
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write32 IPU_CONF, IPU_CONF_DI_EN |
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write32 CCM_CCMR, CCM_CCMR_SETUP |
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wait_timer 0x40000 |
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write32 CCM_CCMR, CCM_CCMR_SETUP | CCMR_MPE |
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write32 CCM_CCMR, (CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS |
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/* Set up clock to 532MHz */ |
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write32 CCM_PDR0, CCM_PDR0_SETUP_532MHZ |
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write32 CCM_MPCTL, CCM_MPCTL_SETUP_532MHZ |
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write32 CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1) |
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/* Set up MX31 DDR pins */ |
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write32 IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B, 0 |
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write32 IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0, 0 |
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write32 IOMUXC_SW_PAD_CTL_BCLK_RW_RAS, 0 |
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write32 IOMUXC_SW_PAD_CTL_CS2_CS3_CS4, 0x1000 |
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write32 IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1, 0 |
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write32 IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2, 0 |
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write32 IOMUXC_SW_PAD_CTL_SD29_SD30_SD31, 0 |
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write32 IOMUXC_SW_PAD_CTL_SD26_SD27_SD28, 0 |
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write32 IOMUXC_SW_PAD_CTL_SD23_SD24_SD25, 0 |
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write32 IOMUXC_SW_PAD_CTL_SD20_SD21_SD22, 0 |
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write32 IOMUXC_SW_PAD_CTL_SD17_SD18_SD19, 0 |
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write32 IOMUXC_SW_PAD_CTL_SD14_SD15_SD16, 0 |
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write32 IOMUXC_SW_PAD_CTL_SD11_SD12_SD13, 0 |
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write32 IOMUXC_SW_PAD_CTL_SD8_SD9_SD10, 0 |
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write32 IOMUXC_SW_PAD_CTL_SD5_SD6_SD7, 0 |
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write32 IOMUXC_SW_PAD_CTL_SD2_SD3_SD4, 0 |
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write32 IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1, 0 |
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write32 IOMUXC_SW_PAD_CTL_A24_A25_SDBA1, 0 |
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write32 IOMUXC_SW_PAD_CTL_A21_A22_A23, 0 |
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write32 IOMUXC_SW_PAD_CTL_A18_A19_A20, 0 |
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write32 IOMUXC_SW_PAD_CTL_A15_A16_A17, 0 |
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write32 IOMUXC_SW_PAD_CTL_A12_A13_A14, 0 |
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write32 IOMUXC_SW_PAD_CTL_A10_MA10_A11, 0 |
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write32 IOMUXC_SW_PAD_CTL_A7_A8_A9, 0 |
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write32 IOMUXC_SW_PAD_CTL_A4_A5_A6, 0 |
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write32 IOMUXC_SW_PAD_CTL_A1_A2_A3, 0 |
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write32 IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0, 0 |
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/* Set up MX31 DDR Memory Controller */ |
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write32 WEIM_ESDMISC, ESDMISC_MDDR_SETUP |
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write32 WEIM_ESDCFG0, ESDCFG0_MDDR_SETUP |
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/* Perform DDR init sequence */ |
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write32 WEIM_ESDCTL0, ESDCTL_PRECHARGE |
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write32 CSD0_BASE | 0x0f00, 0x12344321 |
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write32 WEIM_ESDCTL0, ESDCTL_AUTOREFRESH |
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write32 CSD0_BASE, 0x12344321 |
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write32 CSD0_BASE, 0x12344321 |
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write32 WEIM_ESDCTL0, ESDCTL_LOADMODEREG |
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write8 CSD0_BASE | 0x00000033, 0xda |
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write8 CSD0_BASE | 0x01000000, 0xff |
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write32 WEIM_ESDCTL0, ESDCTL_RW |
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write32 CSD0_BASE, 0xDEADBEEF |
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write32 WEIM_ESDMISC, ESDMISC_MDDR_RESET_DL |
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mov pc, lr |
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@ -0,0 +1,54 @@ |
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CONFIG_NAND_SPL = y
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include $(TOPDIR)/config.mk |
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include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk |
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LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
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LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
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AFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL
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CFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL
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SOBJS = start.o lowlevel_init.o
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COBJS = nand_boot_fsl_nfc.o
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SRCS := $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c
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SRCS += $(SRCTREE)/cpu/arm1136/start.S
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SRCS += $(SRCTREE)/board/freescale/mx31pdk/lowlevel_init.S
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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__OBJS := $(SOBJS) $(COBJS)
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LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
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nandobj := $(OBJTREE)/nand_spl/
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ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
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all: $(obj).depend $(ALL) |
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$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl |
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$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
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$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl |
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$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
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$(nandobj)u-boot-spl: $(OBJS) |
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cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
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-Map $(nandobj)u-boot-spl.map \
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-o $@
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#########################################################################
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$(obj)%.o: $(SRCTREE)/cpu/arm1136/%.S |
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$(CC) $(AFLAGS) -c -o $@ $<
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$(obj)%.o: $(SRCTREE)/board/freescale/mx31pdk/%.S |
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$(CC) $(AFLAGS) -c -o $@ $<
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$(obj)%.o: $(SRCTREE)/nand_spl/%.c |
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$(CC) $(CFLAGS) -c -o $@ $<
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1 @@ |
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PAD_TO := 2048
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@ -0,0 +1,36 @@ |
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
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OUTPUT_ARCH(arm) |
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ENTRY(_start) |
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SECTIONS |
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{ |
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. = 0x00000000; |
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. = ALIGN(4); |
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.text : |
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{ |
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start.o (.text) |
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lowlevel_init.o (.text) |
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nand_boot_fsl_nfc.o (.text) |
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*(.text) |
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. = 2K; |
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} |
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. = ALIGN(4); |
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.rodata : { *(.rodata) } |
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. = ALIGN(4); |
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.data : { *(.data) } |
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. = ALIGN(4); |
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.got : { *(.got) } |
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. = .; |
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__u_boot_cmd_start = .; |
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.u_boot_cmd : { *(.u_boot_cmd) } |
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__u_boot_cmd_end = .; |
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. = ALIGN(4); |
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__bss_start = .; |
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.bss : { *(.bss) } |
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_end = .; |
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} |
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