Without this change, kernel fails at calling function cache_clean_flush during kernel early boot. Aprocryphally, intended for T114 only, so I check for a T114 SoC. Works (i.e. dalmore 3.8 kernel now starts printing to console). Signed-off-by: Tom Warren <twarren@nvidia.com>master
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/*
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* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms and conditions of the GNU General Public License, |
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* version 2, as published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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* more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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/* Tegra cache routines */ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch-tegra/ap.h> |
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#include <asm/arch/gp_padctrl.h> |
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void config_cache(void) |
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{ |
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struct apb_misc_gp_ctlr *gp = |
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(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; |
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u32 reg = 0; |
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/* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */ |
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asm volatile( |
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"mrc p15, 0, r0, c1, c0, 1\n" |
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"orr r0, r0, #0x41\n" |
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"mcr p15, 0, r0, c1, c0, 1\n"); |
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/* Currently, only T114 needs this L2 cache change to boot Linux */ |
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reg = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK); |
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if (reg != (CHIPID_TEGRA114 << HIDREV_CHIPID_SHIFT)) |
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return; |
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/*
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* Systems with an architectural L2 cache must not use the PL310. |
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* Config L2CTLR here for a data RAM latency of 3 cycles. |
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*/ |
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asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg)); |
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reg &= ~7; |
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reg |= 2; |
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asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg)); |
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} |
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