Merge branch 'master' of http://www.denx.de/git/u-boot
Jon Loeliger
19 years ago
commit
d22200f020
@ -0,0 +1,50 @@ |
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#
|
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# (C) Copyright 2003-2006
|
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
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include $(TOPDIR)/config.mk |
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|
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LIB = $(obj)lib$(BOARD).a
|
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|
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COBJS := $(BOARD).o ethaddr.o
|
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|
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
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OBJS := $(addprefix $(obj),$(COBJS))
|
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SOBJS := $(addprefix $(obj),$(SOBJS))
|
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|
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$(LIB): $(obj).depend $(OBJS) |
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$(AR) crv $@ $(OBJS)
|
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|
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clean: |
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rm -f $(SOBJS) $(OBJS)
|
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|
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
|
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|
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#########################################################################
|
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|
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# defines $(obj).depend target
|
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include $(SRCTREE)/rules.mk |
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|
||||
sinclude $(obj).depend |
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|
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#########################################################################
|
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@ -0,0 +1,32 @@ |
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#
|
||||
# (C) Copyright 2003-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# MarelV38B board
|
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#
|
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|
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sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp |
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|
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TEXT_BASE = 0xFF000000
|
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|
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PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
|
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@ -0,0 +1,254 @@ |
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/*
|
||||
* |
||||
* (C) Copyright 2006 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
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|
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#include <common.h> |
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#include <mpc5xxx.h> |
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|
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#define GPIO_ENABLE (MPC5XXX_WU_GPIO) |
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|
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/* Open Drain Emulation Register */ |
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#define GPIO_ODR (MPC5XXX_WU_GPIO + 0x04) |
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|
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/* Data Direction Register */ |
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#define GPIO_DDR (MPC5XXX_WU_GPIO + 0x08) |
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|
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/* Data Value Out Register */ |
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#define GPIO_DVOR (MPC5XXX_WU_GPIO + 0x0C) |
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|
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/* Interrupt Enable Register */ |
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#define GPIO_IER (MPC5XXX_WU_GPIO + 0x10) |
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|
||||
/* Individual Interrupt Enable Register */ |
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#define GPIO_IIER (MPC5XXX_WU_GPIO + 0x14) |
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|
||||
/* Interrupt Type Register */ |
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#define GPIO_ITR (MPC5XXX_WU_GPIO + 0x18) |
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|
||||
/* Master Enable Register */ |
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#define GPIO_MER (MPC5XXX_WU_GPIO + 0x1C) |
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|
||||
/* Data Input Value Register */ |
||||
#define GPIO_DIVR (MPC5XXX_WU_GPIO + 0x20) |
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|
||||
/* Status Register */ |
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#define GPIO_SR (MPC5XXX_WU_GPIO + 0x24) |
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|
||||
#define PSC6_0 0x10000000 |
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#define WKUP_7 0x80000000 |
||||
|
||||
/* For NS4 A/B board define WKUP_7, for V38B board PSC_6 */ |
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#define GPIO_PIN PSC6_0 |
||||
|
||||
#define NO_ERROR 0 |
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#define ERR_NO_NUMBER 1 |
||||
#define ERR_BAD_NUMBER 2 |
||||
|
||||
typedef volatile unsigned long GPIO_REG; |
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typedef GPIO_REG *GPIO_REG_PTR; |
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|
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static int is_high(void); |
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static int check_device(void); |
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static void io_out(int value); |
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static void io_input(void); |
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static void io_output(void); |
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static void init_gpio(void); |
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static void read_byte(unsigned char *data); |
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static void write_byte(unsigned char command); |
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|
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void read_2501_memory(unsigned char *psernum, unsigned char *perr); |
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void board_get_enetaddr(uchar *enetaddr); |
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|
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static int is_high() |
||||
{ |
||||
return (* ((vu_long *) GPIO_DIVR) & GPIO_PIN); |
||||
} |
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|
||||
static void io_out(int value) |
||||
{ |
||||
if (value) |
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*((vu_long *) GPIO_DVOR) |= GPIO_PIN; |
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else |
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*((vu_long *) GPIO_DVOR) &= ~GPIO_PIN; |
||||
} |
||||
|
||||
static void io_input() |
||||
{ |
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*((vu_long *) GPIO_DDR) &= ~GPIO_PIN; |
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udelay(3); /* allow input to settle */ |
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} |
||||
|
||||
static void io_output() |
||||
{ |
||||
*((vu_long *) GPIO_DDR) |= GPIO_PIN; |
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} |
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|
||||
static void init_gpio() |
||||
{ |
||||
*((vu_long *) GPIO_ENABLE) |= GPIO_PIN; /* Enable appropriate pin */ |
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} |
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|
||||
void read_2501_memory(unsigned char *psernum, unsigned char *perr) |
||||
{ |
||||
#define NBYTES 28 |
||||
unsigned char crcval, i; |
||||
unsigned char buf[NBYTES]; |
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|
||||
*perr = 0; |
||||
crcval = 0; |
||||
|
||||
for (i=0; i<NBYTES; i++) |
||||
|
||||
|
||||
if (!check_device()) |
||||
*perr = ERR_NO_NUMBER; |
||||
else { |
||||
*perr = NO_ERROR; |
||||
write_byte(0xCC); /* skip ROM (0xCC) */ |
||||
write_byte(0xF0); /* Read memory command 0xF0 */ |
||||
write_byte(0x00); /* Address TA1=0, TA2=0 */ |
||||
write_byte(0x00); |
||||
read_byte(&crcval); /* Read CRC of address and command */ |
||||
|
||||
for (i=0; i<NBYTES; i++) |
||||
read_byte( &buf[i] ); |
||||
} |
||||
if (strncmp((const char*) &buf[11], "MAREL IEEE 802.3", 16)) { |
||||
*perr = ERR_BAD_NUMBER; |
||||
psernum[0] = 0x00; |
||||
psernum[1] = 0xE0; |
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psernum[2] = 0xEE; |
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psernum[3] = 0xFF; |
||||
psernum[4] = 0xFF; |
||||
psernum[5] = 0xFF; |
||||
} |
||||
else { |
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psernum[0] = 0x00; |
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psernum[1] = 0xE0; |
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psernum[2] = 0xEE; |
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psernum[3] = buf[7]; |
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psernum[4] = buf[6]; |
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psernum[5] = buf[5]; |
||||
} |
||||
} |
||||
|
||||
static int check_device() |
||||
{ |
||||
int found; |
||||
|
||||
io_output(); |
||||
io_out(0); |
||||
udelay(500); /* must be at least 480 us low pulse */ |
||||
|
||||
io_input(); |
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udelay(60); |
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|
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found = (is_high() == 0) ? 1 : 0; |
||||
udelay(500); /* must be at least 480 us low pulse */ |
||||
|
||||
return found; |
||||
} |
||||
|
||||
static void write_byte(unsigned char command) |
||||
{ |
||||
char i; |
||||
|
||||
for (i=0; i<8; i++) { |
||||
/* 1 us to 15 us low pulse starts bit slot */ |
||||
/* Start with high pulse for 3 us */ |
||||
io_input(); |
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|
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udelay(3); |
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|
||||
io_out(0); |
||||
io_output(); |
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|
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udelay(3); |
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|
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if (command & 0x01) { |
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/* 60 us high for 1-bit */ |
||||
io_input(); |
||||
udelay(60); |
||||
} |
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else { |
||||
/* 60 us low for 0-bit */ |
||||
udelay(60); |
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} |
||||
/* Leave pin as input */ |
||||
io_input(); |
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|
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command = command >> 1; |
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} |
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} |
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|
||||
static void read_byte(unsigned char *data) |
||||
{ |
||||
unsigned char i, rdat = 0; |
||||
|
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for (i=0; i<8; i++) { |
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/* read one bit from one-wire device */ |
||||
|
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/* 1 - 15 us low starts bit slot */ |
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io_out(0); |
||||
io_output(); |
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udelay(0); |
||||
|
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/* allow line to be pulled high */ |
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io_input(); |
||||
|
||||
/* delay 10 us */ |
||||
udelay(10); |
||||
|
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/* now sample input status */ |
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if (is_high()) |
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rdat = (rdat >> 1) | 0x80; |
||||
else |
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rdat = rdat >> 1; |
||||
|
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udelay(60); /* at least 60 us */ |
||||
} |
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/* copy the return value */ |
||||
*data = rdat; |
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} |
||||
|
||||
void board_get_enetaddr(uchar *enetaddr) |
||||
{ |
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unsigned char sn[6], err=NO_ERROR; |
||||
|
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init_gpio(); |
||||
|
||||
read_2501_memory(sn, &err); |
||||
|
||||
if (err == NO_ERROR) { |
||||
sprintf(enetaddr, "%02x:%02x:%02x:%02x:%02x:%02x", |
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sn[0], sn[1], sn[2], sn[3], sn[4], sn[5]); |
||||
printf("MAC address: %s\n", enetaddr); |
||||
setenv("ethaddr", enetaddr); |
||||
} |
||||
else { |
||||
sprintf(enetaddr, "00:01:02:03:04:05"); |
||||
printf("Error reading MAC address.\n"); |
||||
printf("Setting default to %s\n", enetaddr); |
||||
setenv("ethaddr", enetaddr); |
||||
} |
||||
} |
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@ -0,0 +1,122 @@ |
||||
/* |
||||
* (C) Copyright 2003-2006 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc5xxx/start.o (.text) |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
. = ALIGN(16); |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
@ -0,0 +1,252 @@ |
||||
/*
|
||||
* (C) Copyright 2003-2006 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* (C) Copyright 2004 |
||||
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <mpc5xxx.h> |
||||
#include <asm/processor.h> |
||||
|
||||
#ifndef CFG_RAMBOOT |
||||
static void sdram_start(int hi_addr) |
||||
{ |
||||
long hi_addr_bit = hi_addr ? 0x01000000 : 0; |
||||
|
||||
/* unlock mode register */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* precharge all banks */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
#if SDRAM_DDR |
||||
/* set mode register: extended mode */ |
||||
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* set mode register: reset DLL */ |
||||
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; |
||||
__asm__ volatile ("sync"); |
||||
#endif /* SDRAM_DDR */ |
||||
|
||||
/* precharge all banks */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* auto refresh */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* set mode register */ |
||||
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* normal operation */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; |
||||
__asm__ volatile ("sync"); |
||||
} |
||||
#endif /* !CFG_RAMBOOT */ |
||||
|
||||
|
||||
long int initdram(int board_type) |
||||
{ |
||||
ulong dramsize = 0; |
||||
ulong dramsize2 = 0; |
||||
uint svr, pvr; |
||||
|
||||
#ifndef CFG_RAMBOOT |
||||
ulong test1, test2; |
||||
|
||||
/* setup SDRAM chip selects */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* setup config registers */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; |
||||
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
#if SDRAM_DDR |
||||
/* set tap delay */ |
||||
*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; |
||||
__asm__ volatile ("sync"); |
||||
#endif /* SDRAM_DDR */ |
||||
|
||||
/* find RAM size using SDRAM CS0 only */ |
||||
sdram_start(0); |
||||
test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); |
||||
sdram_start(1); |
||||
test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); |
||||
if (test1 > test2) { |
||||
sdram_start(0); |
||||
dramsize = test1; |
||||
} else |
||||
dramsize = test2; |
||||
|
||||
/* memory smaller than 1MB is impossible */ |
||||
if (dramsize < (1 << 20)) |
||||
dramsize = 0; |
||||
|
||||
/* set SDRAM CS0 size according to the amount of RAM found */ |
||||
if (dramsize > 0) |
||||
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; |
||||
else |
||||
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ |
||||
|
||||
/* let SDRAM CS1 start right after CS0 */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ |
||||
|
||||
/* find RAM size using SDRAM CS1 only */ |
||||
if (!dramsize) |
||||
sdram_start(0); |
||||
test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); |
||||
if (!dramsize) { |
||||
sdram_start(1); |
||||
test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); |
||||
} |
||||
if (test1 > test2) { |
||||
sdram_start(0); |
||||
dramsize2 = test1; |
||||
} else |
||||
dramsize2 = test2; |
||||
|
||||
/* memory smaller than 1MB is impossible */ |
||||
if (dramsize2 < (1 << 20)) |
||||
dramsize2 = 0; |
||||
|
||||
/* set SDRAM CS1 size according to the amount of RAM found */ |
||||
if (dramsize2 > 0) |
||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize |
||||
| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); |
||||
else |
||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ |
||||
|
||||
#else /* CFG_RAMBOOT */ |
||||
|
||||
/* retrieve size of memory connected to SDRAM CS0 */ |
||||
dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; |
||||
if (dramsize >= 0x13) |
||||
dramsize = (1 << (dramsize - 0x13)) << 20; |
||||
else |
||||
dramsize = 0; |
||||
|
||||
/* retrieve size of memory connected to SDRAM CS1 */ |
||||
dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; |
||||
if (dramsize2 >= 0x13) |
||||
dramsize2 = (1 << (dramsize2 - 0x13)) << 20; |
||||
else |
||||
dramsize2 = 0; |
||||
|
||||
#endif /* CFG_RAMBOOT */ |
||||
|
||||
/*
|
||||
* On MPC5200B we need to set the special configuration delay in the |
||||
* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM |
||||
* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: |
||||
* |
||||
* "The SDelay should be written to a value of 0x00000004. It is |
||||
* required to account for changes caused by normal wafer processing |
||||
* parameters." |
||||
*/ |
||||
svr = get_svr(); |
||||
pvr = get_pvr(); |
||||
if ((SVR_MJREV(svr) >= 2) && |
||||
(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { |
||||
|
||||
*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; |
||||
__asm__ volatile ("sync"); |
||||
} |
||||
|
||||
return dramsize + dramsize2; |
||||
} |
||||
|
||||
|
||||
int checkboard (void) |
||||
{ |
||||
puts("Board: MarelV38B\n"); |
||||
return 0; |
||||
} |
||||
|
||||
|
||||
int board_early_init_r(void) |
||||
{ |
||||
/*
|
||||
* Now, when we are in RAM, enable flash write access for detection process. |
||||
* Note that CS_BOOT cannot be cleared when executing in flash. |
||||
*/ |
||||
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ |
||||
return 0; |
||||
} |
||||
|
||||
|
||||
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) |
||||
|
||||
#define GPIO_PSC1_4 0x01000000UL |
||||
|
||||
void init_ide_reset(void) |
||||
{ |
||||
debug("init_ide_reset\n"); |
||||
|
||||
/* Configure PSC1_4 as GPIO output for ATA reset */ |
||||
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; |
||||
*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; |
||||
/* Deassert reset */ |
||||
*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; |
||||
} |
||||
|
||||
|
||||
void ide_set_reset(int idereset) |
||||
{ |
||||
debug("ide_reset(%d)\n", idereset); |
||||
|
||||
if (idereset) { |
||||
*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; |
||||
/* Make a delay. MPC5200 spec says 25 usec min */ |
||||
udelay(500000); |
||||
} else |
||||
*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; |
||||
} |
||||
#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ |
||||
|
||||
|
||||
void led_d4_on(void) |
||||
{ |
||||
/* TIMER7 as GPIO output low */ |
||||
*(vu_long *) (MPC5XXX_GPT + 0x70) |= 0x24; |
||||
} |
||||
|
||||
|
||||
void led_d4_off(void) |
||||
{ |
||||
/* TIMER7 as GPIO output high */ |
||||
*(vu_long *) (MPC5XXX_GPT + 0x70) |= 0x34; |
||||
} |
||||
|
||||
|
||||
void hw_watchdog_reset(void) |
||||
{ |
||||
/* TODO fill this in */ |
||||
} |
||||
@ -0,0 +1,368 @@ |
||||
/*
|
||||
* (C) Copyright 2003-2004 Wolfgang Denk, DENX Software Engineering, |
||||
* wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify it |
||||
* under the terms of the GNU General Public License as published by the Free |
||||
* Software Foundation; either version 2 of the License, or (at your option) |
||||
* any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, but WITHOUT |
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
||||
* for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License along |
||||
* with this program; if not, write to the Free Software Foundation, Inc., 59 |
||||
* Temple Place, Suite 330, Boston, MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#if 0 |
||||
#define DEBUG 0xFFF |
||||
#endif |
||||
|
||||
#if 0 |
||||
#define DEBUG 0x01 |
||||
#endif |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ |
||||
#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ |
||||
#define CONFIG_V38B 1 /* ... on V38B board */ |
||||
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
||||
|
||||
#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ |
||||
#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ |
||||
#define CONFIG_HW_WATCHDOG 1 /* has watchdog */ |
||||
|
||||
#define CONFIG_NETCONSOLE 1 |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_R 1 /* make flash read/write */ |
||||
|
||||
#define CFG_XLB_PIPELINING 1 /* gives better performance */ |
||||
|
||||
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Serial console configuration |
||||
*/ |
||||
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ |
||||
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
||||
|
||||
|
||||
/*
|
||||
* DDR |
||||
*/ |
||||
#define SDRAM_DDR 1 /* is DDR */ |
||||
/* Settings for XLB = 132 MHz */ |
||||
#define SDRAM_MODE 0x018D0000 |
||||
#define SDRAM_EMODE 0x40090000 |
||||
#define SDRAM_CONTROL 0x704f0f00 |
||||
#define SDRAM_CONFIG1 0x73722930 |
||||
#define SDRAM_CONFIG2 0x47770000 |
||||
#define SDRAM_TAPDELAY 0x10000000 |
||||
|
||||
|
||||
/*
|
||||
* PCI - no suport |
||||
*/ |
||||
#undef CONFIG_PCI |
||||
|
||||
/*
|
||||
* Partitions |
||||
*/ |
||||
#define CONFIG_MAC_PARTITION 1 |
||||
#define CONFIG_DOS_PARTITION 1 |
||||
|
||||
/*
|
||||
* USB |
||||
*/ |
||||
#define CONFIG_USB_OHCI |
||||
#define CONFIG_USB_STORAGE |
||||
|
||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
||||
|
||||
/*
|
||||
* Supported commands |
||||
*/ |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_FAT | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_IDE | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DIAG | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_JFFS2 | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_SDRAMi | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_USB | \
|
||||
CFG_CMD_FAT) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Boot low with 16 MB Flash |
||||
*/ |
||||
# define CFG_LOWBOOT 1 |
||||
# define CFG_LOWBOOT16 1 |
||||
|
||||
/*
|
||||
* Autobooting |
||||
*/ |
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
||||
|
||||
#define CONFIG_PREBOOT "echo;" \ |
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"devno=5\0" \
|
||||
"hostname=V38B_$(devno)\0" \
|
||||
"ipaddr=10.100.99.$(devno)\0" \
|
||||
"netmask=255.255.0.0\0" \
|
||||
"serverip=10.100.10.90\0" \
|
||||
"gatewayip=10.100.254.254\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"rootpath=/opt/eldk/ppc_6xx\0" \
|
||||
"bootfile=mpc5200/uImage\0" \
|
||||
"bootcmd=run net_nfs\0" \
|
||||
"addip=setenv bootargs $(bootargs) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):" \
|
||||
"$(netmask):$(hostname):$(netdev):off panic=1\0" \
|
||||
"flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
|
||||
"flash_self=run ramargs addip;bootm $(kernel_addr) " \
|
||||
"$(ramdisk_addr)\0" \
|
||||
"net_nfs=tftp 200000 $(bootfile);run nfsargs " \
|
||||
"addip;bootm\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$(serverip):$(rootpath)\0" \
|
||||
"" |
||||
|
||||
#define CONFIG_BOOTCOMMAND "run net_nfs" |
||||
|
||||
#if defined(CONFIG_MPC5200) |
||||
/*
|
||||
* IPB Bus clocking configuration. |
||||
*/ |
||||
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ |
||||
#endif |
||||
/*
|
||||
* I2C configuration |
||||
*/ |
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ |
||||
|
||||
#define CFG_I2C_SPEED 100000 /* 100 kHz */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
/*
|
||||
* EEPROM configuration |
||||
*/ |
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 3 |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 |
||||
|
||||
/*
|
||||
* RTC configuration |
||||
*/ |
||||
#define CFG_I2C_RTC_ADDR 0x51 |
||||
|
||||
/*
|
||||
* Flash configuration - use CFI driver |
||||
*/ |
||||
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ |
||||
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
||||
#define CFG_FLASH_CFI_AMD_RESET 1 |
||||
#define CFG_FLASH_BASE 0xFF000000 |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ |
||||
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } |
||||
#define CFG_FLASH_SIZE 0x01000000 /* 16 MiB */ |
||||
#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ |
||||
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ |
||||
|
||||
/*
|
||||
* Environment settings |
||||
*/ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000) |
||||
#define CFG_ENV_SIZE 0x10000 |
||||
#define CFG_ENV_SECT_SIZE 0x10000 |
||||
#define CONFIG_ENV_OVERWRITE 1 |
||||
|
||||
/*
|
||||
* Memory map |
||||
*/ |
||||
#define CFG_MBAR 0xF0000000 |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_DEFAULT_MBAR 0x80000000 |
||||
|
||||
/* Use SRAM until RAM will be available */ |
||||
#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM |
||||
#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ |
||||
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
||||
# define CFG_RAMBOOT 1 |
||||
#endif |
||||
|
||||
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*
|
||||
* Ethernet configuration |
||||
*/ |
||||
#define CONFIG_MPC5xxx_FEC 1 |
||||
#define CONFIG_PHY_ADDR 0x00 |
||||
#define CONFIG_MII 1 |
||||
|
||||
/*
|
||||
* GPIO configuration |
||||
*/ |
||||
#define CFG_GPS_PORT_CONFIG 0x90000404 |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
/*
|
||||
* Various low-level settings |
||||
*/ |
||||
#if defined(CONFIG_MPC5200) |
||||
#define CFG_HID0_INIT HID0_ICE | HID0_ICFI |
||||
#define CFG_HID0_FINAL HID0_ICE |
||||
#else |
||||
#define CFG_HID0_INIT 0 |
||||
#define CFG_HID0_FINAL 0 |
||||
#endif |
||||
|
||||
|
||||
#define CFG_BOOTCS_START CFG_FLASH_BASE |
||||
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE |
||||
#define CFG_BOOTCS_CFG 0x00047801 |
||||
#define CFG_CS0_START CFG_FLASH_BASE |
||||
#define CFG_CS0_SIZE CFG_FLASH_SIZE |
||||
|
||||
#define CFG_CS_BURST 0x00000000 |
||||
#define CFG_CS_DEADCYCLE 0x33333333 |
||||
|
||||
#define CFG_RESET_ADDRESS 0xff000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* USB stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_USB_CLOCK 0x0001BBBB |
||||
#define CONFIG_USB_CONFIG 0x00001000 |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff Supports IDE harddisk |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ |
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */ |
||||
|
||||
#define CONFIG_IDE_RESET /* reset for ide supported */ |
||||
#define CONFIG_IDE_PREINIT |
||||
|
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
||||
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
||||
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000 |
||||
|
||||
#define CFG_ATA_BASE_ADDR MPC5XXX_ATA |
||||
|
||||
/* Offset for data I/O */ |
||||
#define CFG_ATA_DATA_OFFSET (0x0060) |
||||
|
||||
/* Offset for normal register accesses */ |
||||
#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) |
||||
|
||||
/* Offset for alternate registers */ |
||||
#define CFG_ATA_ALT_OFFSET (0x005C) |
||||
|
||||
/* Interval between registers */ |
||||
#define CFG_ATA_STRIDE 4 |
||||
|
||||
/* Status LED */ |
||||
|
||||
#define CONFIG_STATUS_LED /* Status LED enabled */ |
||||
#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ |
||||
|
||||
#define CFG_LED_BASE (0xf0000600 + 0x70) /* Timer 7 GPIO */ |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
/* LEDs */ |
||||
typedef unsigned int led_id_t; |
||||
|
||||
#define __led_toggle(_msk) \ |
||||
do { \
|
||||
*((volatile long *) (CFG_LED_BASE)) ^= (_msk); \
|
||||
} while(0) |
||||
|
||||
#define __led_set(_msk, _st) \ |
||||
do { \
|
||||
if ((_st)) \
|
||||
*((volatile long *) (CFG_LED_BASE)) &= ~(_msk); \
|
||||
else \
|
||||
*((volatile long *) (CFG_LED_BASE)) |= (_msk); \
|
||||
} while(0) |
||||
|
||||
#define __led_init(_msk, st) \ |
||||
{ \
|
||||
*((volatile long *) (CFG_LED_BASE)) |= 0x34; \
|
||||
} |
||||
|
||||
#endif |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue