-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJbrkmLAAoJEO1FWZTaC520lWIQAIrcTTzZn6VOhLwqrcTLK39r Jskw1eeucNO/msP3zy7zNO5T0Prx/N7d2sQcoze0E2qlg0CRiBhXVcdM9itz/5cf yvmmxr9rsUoK85Zz7pmEZHYxKVwxlmtSZ9b8kFNBo3Kb1GSqM4MlL5fmxzeVeZmL yKe0wz1n8CVTVNNRoKrBKrlBBIOcKfidu9B/5rN6yDsybmEPzhAv5eBg7AjmRvrc n+pvC2SIiP5ki7o2uLEHkqGFLoWwYTLILXJQUL3busXtzAwjfLH+8yakPJmjVk0B 9fwg8UNSriXewuyaXYxE4uEwJ2lkqcNx+gawXgnrt4NypshYwqRkBSoaDtg0pRWh +fBwTN8St5bvug/bk4I94jmdf2ezNMj9+tDXZDR3Hc9ZuG2Cv9wPsXBNdIpKPKaM Mb1Uvz0w1oyEi6IwLCE0Q6cgDZRc2mi0qfXv4uCXzJNlxgHQvfxH01c7A4tO/rcd KsV+PIECSFgsirClE1mdNH0fBIqo1B+TOH9RqghZRAmhVEit/YGipdmewWkdyVed U234gdH62aHqsPKQ8uvilx+oNa3aNzo1CaZc3P07AKGVOnvr+nndmlYNPfyWvbcU 0Y8P+wlHOuWSWDw/msGTon15W7vQFx8+6eWUlacDgAfbhMCKqjH9JOILXQ5Gs4El +zv0J7ginApiao6sg8Jy =Eqms -----END PGP SIGNATURE----- Merge tag 'mpc85xx-for-v2018.11-rc1' of git://git.denx.de/u-boot-mpc85xx Use device tree for mpc85xx with binman. Enabled for T2080QDS.lime2-spi
Tom Rini
6 years ago
commit
d29a583161
@ -0,0 +1,14 @@ |
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# SPDX-License-Identifier: GPL-2.0+
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dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
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targets += $(dtb-y)
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# Add any required device tree compiler flags here
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DTC_FLAGS +=
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PHONY += dtbs
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dtbs: $(addprefix $(obj)/, $(dtb-y)) |
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@:
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clean-files := *.dtb
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@ -0,0 +1,39 @@ |
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// SPDX-License-Identifier: GPL-2.0+ OR X11 |
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/* |
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* e6500 Power ISA Device Tree Source (include) |
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* |
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* Copyright 2013 Freescale Semiconductor Inc. |
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* Copyright 2018 NXP |
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*/ |
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/ { |
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cpus { |
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power-isa-version = "2.06"; |
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power-isa-b; // Base |
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power-isa-e; // Embedded |
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power-isa-atb; // Alternate Time Base |
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power-isa-cs; // Cache Specification |
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power-isa-ds; // Decorated Storage |
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power-isa-e.ed; // Embedded.Enhanced Debug |
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power-isa-e.pd; // Embedded.External PID |
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power-isa-e.hv; // Embedded.Hypervisor |
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power-isa-e.le; // Embedded.Little-Endian |
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power-isa-e.pm; // Embedded.Performance Monitor |
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power-isa-e.pc; // Embedded.Processor Control |
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power-isa-ecl; // Embedded Cache Locking |
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power-isa-exp; // External Proxy |
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power-isa-fp; // Floating Point |
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power-isa-fp.r; // Floating Point.Record |
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power-isa-mmc; // Memory Coherence |
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power-isa-scpm; // Store Conditional Page Mobility |
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power-isa-wt; // Wait |
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power-isa-64; // 64-bit |
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power-isa-e.pt; // Embedded.Page Table |
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power-isa-e.hv.lrat; // Embedded.Hypervisor.LRAT |
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power-isa-e.em; // Embedded Multi-Threading |
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power-isa-v; // Vector (AltiVec) |
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fsl,eref-er; // Enhanced Reservations |
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fsl,eref-deo; // Data Cache Extended Operations |
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mmu-type = "power-embedded"; |
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}; |
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}; |
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@ -0,0 +1,62 @@ |
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// SPDX-License-Identifier: GPL-2.0+ OR X11 |
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/* |
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* T2080/T2081 Silicon/SoC Device Tree Source (pre include) |
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* |
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* Copyright 2013 Freescale Semiconductor Inc. |
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* Copyright 2018 NXP |
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*/ |
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/dts-v1/; |
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/include/ "e6500_power_isa.dtsi" |
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/ { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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interrupt-parent = <&mpic>; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu0: PowerPC,e6500@0 { |
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device_type = "cpu"; |
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reg = <0 1>; |
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fsl,portid-mapping = <0x80000000>; |
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}; |
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cpu1: PowerPC,e6500@2 { |
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device_type = "cpu"; |
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reg = <2 3>; |
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fsl,portid-mapping = <0x80000000>; |
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}; |
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cpu2: PowerPC,e6500@4 { |
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device_type = "cpu"; |
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reg = <4 5>; |
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fsl,portid-mapping = <0x80000000>; |
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}; |
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cpu3: PowerPC,e6500@6 { |
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device_type = "cpu"; |
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reg = <6 7>; |
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fsl,portid-mapping = <0x80000000>; |
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}; |
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}; |
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soc: soc@ffe000000 { |
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ranges = <0x00000000 0xf 0xfe000000 0x1000000>; |
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reg = <0xf 0xfe000000 0 0x00001000>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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device_type = "soc"; |
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compatible = "simple-bus"; |
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mpic: pic@40000 { |
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interrupt-controller; |
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#address-cells = <0>; |
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#interrupt-cells = <4>; |
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reg = <0x40000 0x40000>; |
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compatible = "fsl,mpic"; |
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device_type = "open-pic"; |
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clock-frequency = <0x0>; |
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}; |
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}; |
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}; |
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@ -0,0 +1,17 @@ |
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// SPDX-License-Identifier: GPL-2.0+ OR X11 |
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/* |
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* T2080QDS Device Tree Source |
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* |
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* Copyright 2013 - 2015 Freescale Semiconductor Inc. |
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* Copyright 2018 NXP |
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*/ |
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/include/ "t2080.dtsi" |
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/ { |
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model = "fsl,T2080QDS"; |
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compatible = "fsl,T2080QDS"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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interrupt-parent = <&mpic>; |
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}; |
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@ -0,0 +1,32 @@ |
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// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright 2018 NXP |
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*/ |
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#include <config.h> |
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/ { |
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binman { |
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filename = "u-boot-with-dtb.bin"; |
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skip-at-start = <CONFIG_SYS_TEXT_BASE>; |
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sort-by-offset; |
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pad-byte = <0xff>; |
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size = <CONFIG_SYS_MONITOR_LEN>; |
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u-boot-with-ucode-ptr { |
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offset = <CONFIG_SYS_TEXT_BASE>; |
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optional-ucode; |
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}; |
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u-boot-dtb-with-ucode { |
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#ifdef CONFIG_MPC85xx |
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align = <256>; |
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#endif |
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}; |
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#ifdef CONFIG_MPC85XX_HAVE_RESET_VECTOR |
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powerpc-mpc85xx-bootpg-resetvec { |
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offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>; |
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}; |
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#endif |
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}; |
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}; |
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@ -0,0 +1,25 @@ |
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# SPDX-License-Identifier: GPL-2.0+ |
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# Copyright 2018 NXP |
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# |
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# Entry-type module for the PowerPC mpc85xx bootpg and resetvec code for U-Boot |
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# |
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from entry import Entry |
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from blob import Entry_blob |
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class Entry_powerpc_mpc85xx_bootpg_resetvec(Entry_blob): |
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"""PowerPC mpc85xx bootpg + resetvec code for U-Boot |
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Properties / Entry arguments: |
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- filename: Filename of u-boot-br.bin (default 'u-boot-br.bin') |
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This enrty is valid for PowerPC mpc85xx cpus. This entry holds |
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'bootpg + resetvec' code for PowerPC mpc85xx CPUs which needs to be |
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placed at offset 'RESET_VECTOR_ADDRESS - 0xffc'. |
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""" |
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def __init__(self, section, etype, node): |
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Entry_blob.__init__(self, section, etype, node) |
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def GetDefaultFilename(self): |
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return 'u-boot-br.bin' |
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@ -0,0 +1,21 @@ |
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// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright 2018 NXP |
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*/ |
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/dts-v1/; |
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/ { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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binman { |
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size = <32>; |
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sort-by-offset; |
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end-at-4gb; |
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skip-at-start = <0xffffffe0>; |
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u-boot { |
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offset = <0xffffffe0>; |
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}; |
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}; |
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}; |
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@ -0,0 +1,16 @@ |
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// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright 2018 NXP |
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*/ |
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/dts-v1/; |
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/ { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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binman { |
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powerpc-mpc85xx-bootpg-resetvec { |
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}; |
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}; |
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}; |
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