The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of
P3041DS/P5020DS ("Hydra") reference board.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
master
Timur Tabi
13 years ago
committed by
Andy Fleming
parent
1956e431f8
commit
d31e53b42c
@ -0,0 +1,722 @@ |
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/*
|
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* Copyright 2009-2011 Freescale Semiconductor, Inc. |
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* Author: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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/*
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* This file handles the board muxing between the Fman Ethernet MACs and |
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* the RGMII/SGMII/XGMII PHYs on a Freescale P5040 "Super Hydra" reference |
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* board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are |
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* provided by the standard Freescale four-port SGMII riser card. The 10Gb |
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* XGMII PHYs are provided via the XAUI riser card. The P5040 has 2 FMans |
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* and 5 1G interfaces and 10G interface per FMan. Based on the options in |
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* the RCW, we could have upto 3 SGMII cards and 1 XAUI card at a time. |
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* |
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* Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control |
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* muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is |
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* always the same (0). The value for SGMII depends on which slot the riser is |
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* inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII, |
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* the value is based on which slot the XAUI is inserted in. |
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* |
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* The SERDES configuration is used to determine where the SGMII and XAUI cards |
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* exist, and also which Fman's MACs are routed to which PHYs. So for a given |
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* Fman MAC, there is one and only PHY it connects to. MACs cannot be routed |
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* to PHYs dynamically. |
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* |
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* |
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* This file also updates the device tree in three ways: |
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* |
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* 1) The status of each virtual MDIO node that is referenced by an Ethernet |
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* node is set to "okay". |
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* |
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* 2) The phy-handle property of each active Ethernet MAC node is set to the |
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* appropriate PHY node. |
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* |
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* 3) The "mux value" for each virtual MDIO node is set to the correct value, |
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* if necessary. Some virtual MDIO nodes do not have configurable mux |
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* values, so those values are hard-coded in the DTS. On the HYDRA board, |
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* the virtual MDIO node for the SGMII card needs to be updated. |
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* |
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* For all this to work, the device tree needs to have the following: |
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* |
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* 1) An alias for each PHY node that an Ethernet node could be routed to. |
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* |
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* 2) An alias for each real and virtual MDIO node that is disabled by default |
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* and might need to be enabled, and also might need to have its mux-value |
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* updated. |
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*/ |
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#include <common.h> |
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#include <netdev.h> |
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#include <asm/fsl_serdes.h> |
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#include <fm_eth.h> |
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#include <fsl_mdio.h> |
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#include <malloc.h> |
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#include <fdt_support.h> |
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#include <asm/fsl_dtsec.h> |
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#include "../common/ngpixis.h" |
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#include "../common/fman.h" |
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#ifdef CONFIG_FMAN_ENET |
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#define BRDCFG1_EMI1_SEL_MASK 0x70 |
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#define BRDCFG1_EMI1_SEL_SLOT1 0x10 |
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#define BRDCFG1_EMI1_SEL_SLOT2 0x20 |
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#define BRDCFG1_EMI1_SEL_SLOT5 0x30 |
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#define BRDCFG1_EMI1_SEL_SLOT6 0x40 |
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#define BRDCFG1_EMI1_SEL_SLOT7 0x50 |
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#define BRDCFG1_EMI1_SEL_SLOT3 0x60 |
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#define BRDCFG1_EMI1_SEL_RGMII 0x00 |
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#define BRDCFG1_EMI1_EN 0x08 |
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#define BRDCFG1_EMI2_SEL_MASK 0x06 |
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#define BRDCFG1_EMI2_SEL_SLOT1 0x00 |
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#define BRDCFG1_EMI2_SEL_SLOT2 0x02 |
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#define BRDCFG2_REG_GPIO_SEL 0x20 |
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/*
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* BRDCFG1 mask and value for each MAC |
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* |
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* This array contains the BRDCFG1 values (in mask/val format) that route the |
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* MDIO bus to a particular RGMII or SGMII PHY. |
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*/ |
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static struct { |
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u8 mask; |
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u8 val; |
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} mdio_mux[NUM_FM_PORTS]; |
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|
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/*
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* Mapping of all 18 SERDES lanes to board slots. A value of '0' here means |
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* that the mapping must be determined dynamically, or that the lane maps to |
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* something other than a board slot |
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*/ |
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static u8 lane_to_slot[] = { |
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7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0 |
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}; |
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/*
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* Set the board muxing for a given MAC |
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* |
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* The MDIO layer calls this function every time it wants to talk to a PHY. |
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*/ |
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void super_hydra_mux_mdio(u8 mask, u8 val) |
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{ |
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clrsetbits_8(&pixis->brdcfg1, mask, val); |
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} |
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struct super_hydra_mdio { |
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u8 mask; |
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u8 val; |
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struct mii_dev *realbus; |
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}; |
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static int super_hydra_mdio_read(struct mii_dev *bus, int addr, int devad, |
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int regnum) |
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{ |
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struct super_hydra_mdio *priv = bus->priv; |
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super_hydra_mux_mdio(priv->mask, priv->val); |
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return priv->realbus->read(priv->realbus, addr, devad, regnum); |
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} |
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static int super_hydra_mdio_write(struct mii_dev *bus, int addr, int devad, |
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int regnum, u16 value) |
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{ |
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struct super_hydra_mdio *priv = bus->priv; |
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super_hydra_mux_mdio(priv->mask, priv->val); |
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return priv->realbus->write(priv->realbus, addr, devad, regnum, value); |
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} |
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static int super_hydra_mdio_reset(struct mii_dev *bus) |
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{ |
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struct super_hydra_mdio *priv = bus->priv; |
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return priv->realbus->reset(priv->realbus); |
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} |
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static void super_hydra_mdio_set_mux(char *name, u8 mask, u8 val) |
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{ |
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struct mii_dev *bus = miiphy_get_dev_by_name(name); |
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struct super_hydra_mdio *priv = bus->priv; |
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priv->mask = mask; |
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priv->val = val; |
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} |
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static int super_hydra_mdio_init(char *realbusname, char *fakebusname) |
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{ |
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struct super_hydra_mdio *hmdio; |
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struct mii_dev *bus = mdio_alloc(); |
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if (!bus) { |
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printf("Failed to allocate Hydra MDIO bus\n"); |
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return -1; |
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} |
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hmdio = malloc(sizeof(*hmdio)); |
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if (!hmdio) { |
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printf("Failed to allocate Hydra private data\n"); |
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free(bus); |
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return -1; |
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} |
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bus->read = super_hydra_mdio_read; |
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bus->write = super_hydra_mdio_write; |
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bus->reset = super_hydra_mdio_reset; |
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sprintf(bus->name, fakebusname); |
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hmdio->realbus = miiphy_get_dev_by_name(realbusname); |
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if (!hmdio->realbus) { |
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printf("No bus with name %s\n", realbusname); |
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free(bus); |
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free(hmdio); |
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return -1; |
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} |
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bus->priv = hmdio; |
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return mdio_register(bus); |
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} |
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/*
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* Given the following ... |
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* |
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* 1) A pointer to an Fman Ethernet node (as identified by the 'compat' |
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* compatible string and 'addr' physical address) |
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* |
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* 2) An Fman port |
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* |
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* ... update the phy-handle property of the Ethernet node to point to the |
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* right PHY. This assumes that we already know the PHY for each port. That |
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* information is stored in mdio_mux[]. |
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* |
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* The offset of the Fman Ethernet node is also passed in for convenience, but |
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* it is not used. |
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* |
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* Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. |
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* Inside the Fman, "ports" are things that connect to MACs. We only call them |
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* ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs |
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* and ports are the same thing. |
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*/ |
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void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, |
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enum fm_port port, int offset) |
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{ |
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enum srds_prtcl device; |
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int lane, slot, phy; |
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char alias[32]; |
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/* RGMII and XGMII are already mapped correctly in the DTS */ |
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if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { |
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device = serdes_device_from_fm_port(port); |
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lane = serdes_get_first_lane(device); |
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slot = lane_to_slot[lane]; |
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phy = fm_info_get_phy_address(port); |
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sprintf(alias, "phy_sgmii_slot%u_%x", slot, phy); |
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fdt_set_phy_handle(fdt, compat, addr, alias); |
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} |
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} |
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#define PIXIS_SW2_LANE_23_SEL 0x80 |
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#define PIXIS_SW2_LANE_45_SEL 0x40 |
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#define PIXIS_SW2_LANE_67_SEL_MASK 0x30 |
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#define PIXIS_SW2_LANE_67_SEL_5 0x00 |
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#define PIXIS_SW2_LANE_67_SEL_6 0x20 |
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#define PIXIS_SW2_LANE_67_SEL_7 0x10 |
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#define PIXIS_SW2_LANE_8_SEL 0x08 |
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#define PIXIS_SW2_LANE_1617_SEL 0x04 |
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#define PIXIS_SW11_LANE_9_SEL 0x04 |
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/*
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* Initialize the lane_to_slot[] array. |
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* |
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* On the P4080DS "Expedition" board, the mapping of SERDES lanes to board |
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* slots is hard-coded. On the Hydra board, however, the mapping is controlled |
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* by board switch SW2, so the lane_to_slot[] array needs to be dynamically |
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* initialized. |
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*/ |
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static void initialize_lane_to_slot(void) |
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{ |
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u8 sw2 = in_8(&PIXIS_SW(2)); |
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/* SW11 appears in the programming model as SW9 */ |
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u8 sw11 = in_8(&PIXIS_SW(9)); |
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lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4; |
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lane_to_slot[3] = lane_to_slot[2]; |
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lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6; |
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lane_to_slot[5] = lane_to_slot[4]; |
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switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) { |
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case PIXIS_SW2_LANE_67_SEL_5: |
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lane_to_slot[6] = 5; |
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break; |
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case PIXIS_SW2_LANE_67_SEL_6: |
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lane_to_slot[6] = 6; |
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break; |
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case PIXIS_SW2_LANE_67_SEL_7: |
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lane_to_slot[6] = 7; |
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break; |
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} |
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lane_to_slot[7] = lane_to_slot[6]; |
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lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0; |
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lane_to_slot[9] = (sw11 & PIXIS_SW11_LANE_9_SEL) ? 0 : 3; |
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lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0; |
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lane_to_slot[17] = lane_to_slot[16]; |
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} |
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#endif /* #ifdef CONFIG_FMAN_ENET */ |
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/*
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* Configure the status for the virtual MDIO nodes |
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* |
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* Rather than create the virtual MDIO nodes from scratch for each active |
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* virtual MDIO, we expect the DTS to have the nodes defined already, and we |
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* only enable the ones that are actually active. |
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* |
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* We assume that the DTS already hard-codes the status for all the |
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* virtual MDIO nodes to "disabled", so all we need to do is enable the |
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* active ones. |
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*/ |
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void fdt_fixup_board_enet(void *fdt) |
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{ |
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#ifdef CONFIG_FMAN_ENET |
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enum fm_port i; |
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int lane, slot; |
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for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { |
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int idx = i - FM1_DTSEC1; |
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switch (fm_info_get_enet_if(i)) { |
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case PHY_INTERFACE_MODE_SGMII: |
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lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); |
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if (lane >= 0) { |
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char alias[32]; |
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slot = lane_to_slot[lane]; |
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sprintf(alias, "hydra_sg_slot%u", slot); |
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fdt_status_okay_by_alias(fdt, alias); |
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debug("Enabled MDIO node %s (slot %i)\n", |
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alias, slot); |
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} |
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break; |
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case PHY_INTERFACE_MODE_RGMII: |
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fdt_status_okay_by_alias(fdt, "hydra_rg"); |
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debug("Enabled MDIO node hydra_rg\n"); |
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break; |
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default: |
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break; |
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} |
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} |
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lane = serdes_get_first_lane(XAUI_FM1); |
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if (lane >= 0) { |
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char alias[32]; |
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slot = lane_to_slot[lane]; |
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sprintf(alias, "hydra_xg_slot%u", slot); |
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fdt_status_okay_by_alias(fdt, alias); |
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debug("Enabled MDIO node %s (slot %i)\n", alias, slot); |
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} |
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#if CONFIG_SYS_NUM_FMAN == 2 |
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for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { |
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int idx = i - FM2_DTSEC1; |
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switch (fm_info_get_enet_if(i)) { |
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case PHY_INTERFACE_MODE_SGMII: |
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lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); |
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if (lane >= 0) { |
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char alias[32]; |
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slot = lane_to_slot[lane]; |
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sprintf(alias, "hydra_sg_slot%u", slot); |
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fdt_status_okay_by_alias(fdt, alias); |
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debug("Enabled MDIO node %s (slot %i)\n", |
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alias, slot); |
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} |
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break; |
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case PHY_INTERFACE_MODE_RGMII: |
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fdt_status_okay_by_alias(fdt, "hydra_rg"); |
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debug("Enabled MDIO node hydra_rg\n"); |
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break; |
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default: |
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break; |
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} |
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} |
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lane = serdes_get_first_lane(XAUI_FM2); |
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if (lane >= 0) { |
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char alias[32]; |
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slot = lane_to_slot[lane]; |
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sprintf(alias, "hydra_xg_slot%u", slot); |
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fdt_status_okay_by_alias(fdt, alias); |
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debug("Enabled MDIO node %s (slot %i)\n", alias, slot); |
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} |
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#endif /* CONFIG_SYS_NUM_FMAN == 2 */ |
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#endif /* CONFIG_FMAN_ENET */ |
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} |
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|
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/*
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* Mapping of SerDes Protocol to MDIO MUX value and PHY address. |
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* |
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* Fman 1: |
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* DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4 |
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* Mux Phy | Mux Phy | Mux Phy | Mux Phy |
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* Value Addr | Value Addr | Value Addr | Value Addr |
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* 0x00 2 1c | 2 1d | 2 1e | 2 1f |
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* 0x01 | | 6 1c | |
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* 0x02 | | 3 1c | 3 1d |
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* 0x03 2 1c | 2 1d | 2 1e | 2 1f |
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* 0x04 2 1c | 2 1d | 2 1e | 2 1f |
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* 0x05 | | 3 1c | 3 1d |
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* 0x06 2 1c | 2 1d | 2 1e | 2 1f |
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* 0x07 | | 6 1c | |
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* 0x11 2 1c | 2 1d | 2 1e | 2 1f |
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* 0x2a 2 | | 2 1e | 2 1f |
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* 0x34 6 1c | 6 1d | 4 1e | 4 1f |
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* 0x35 | | 3 1c | 3 1d |
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* 0x36 6 1c | 6 1d | 4 1e | 4 1f |
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* | | | |
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* Fman 2: | | | |
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* DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4 |
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* EMI1 | EMI1 | EMI1 | EMI1 |
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* Mux Phy | Mux Phy | Mux Phy | Mux Phy |
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* Value Addr | Value Addr | Value Addr | Value Addr |
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* 0x00 | | 6 1c | 6 1d |
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* 0x01 | | | |
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* 0x02 | | 6 1c | 6 1d |
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* 0x03 3 1c | 3 1d | 6 1c | 6 1d |
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* 0x04 3 1c | 3 1d | 6 1c | 6 1d |
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* 0x05 | | 6 1c | 6 1d |
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* 0x06 | | 6 1c | 6 1d |
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* 0x07 | | | |
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* 0x11 | | | |
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* 0x2a | | | |
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* 0x34 | | | |
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* 0x35 | | | |
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* 0x36 | | | |
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*/ |
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int board_eth_init(bd_t *bis) |
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{ |
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#ifdef CONFIG_FMAN_ENET |
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struct fsl_pq_mdio_info dtsec_mdio_info; |
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struct tgec_mdio_info tgec_mdio_info; |
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unsigned int i, slot; |
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int lane; |
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
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int srds_prtcl = (in_be32(&gur->rcwsr[4]) & |
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FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; |
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printf("Initializing Fman\n"); |
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initialize_lane_to_slot(); |
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|
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/* We want to use the PIXIS to configure MUX routing, not GPIOs. */ |
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setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); |
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|
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memset(mdio_mux, 0, sizeof(mdio_mux)); |
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|
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dtsec_mdio_info.regs = |
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(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; |
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dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; |
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|
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/* Register the real 1G MDIO bus */ |
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fsl_pq_mdio_init(bis, &dtsec_mdio_info); |
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|
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tgec_mdio_info.regs = |
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(struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; |
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tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; |
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|
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/* Register the real 10G MDIO bus */ |
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fm_tgec_mdio_init(bis, &tgec_mdio_info); |
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|
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/* Register the three virtual MDIO front-ends */ |
||||
super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, |
||||
"SUPER_HYDRA_RGMII_MDIO"); |
||||
super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, |
||||
"SUPER_HYDRA_FM1_SGMII_MDIO"); |
||||
super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, |
||||
"SUPER_HYDRA_FM2_SGMII_MDIO"); |
||||
super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, |
||||
"SUPER_HYDRA_FM1_TGEC_MDIO"); |
||||
super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, |
||||
"SUPER_HYDRA_FM2_TGEC_MDIO"); |
||||
|
||||
/*
|
||||
* Program the DTSEC PHY addresses assuming that they are all SGMII. |
||||
* For any DTSEC that's RGMII, we'll override its PHY address later. |
||||
* We assume that DTSEC5 is only used for RGMII. |
||||
*/ |
||||
fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR); |
||||
|
||||
#if (CONFIG_SYS_NUM_FMAN == 2) |
||||
fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); |
||||
#endif |
||||
|
||||
switch (srds_prtcl) { |
||||
case 0: |
||||
case 3: |
||||
case 4: |
||||
case 6: |
||||
case 0x11: |
||||
case 0x2a: |
||||
case 0x34: |
||||
case 0x36: |
||||
fm_info_set_phy_address(FM1_DTSEC3, |
||||
CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC4, |
||||
CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); |
||||
break; |
||||
case 1: |
||||
case 2: |
||||
case 5: |
||||
case 7: |
||||
case 0x35: |
||||
fm_info_set_phy_address(FM1_DTSEC3, |
||||
CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC4, |
||||
CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); |
||||
break; |
||||
default: |
||||
printf("Fman: Unsupport SerDes Protocol 0x%02x\n", srds_prtcl); |
||||
break; |
||||
} |
||||
|
||||
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { |
||||
int idx = i - FM1_DTSEC1; |
||||
|
||||
switch (fm_info_get_enet_if(i)) { |
||||
case PHY_INTERFACE_MODE_SGMII: |
||||
lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); |
||||
if (lane < 0) |
||||
break; |
||||
slot = lane_to_slot[lane]; |
||||
mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; |
||||
debug("FM1@DTSEC%u expects SGMII in slot %u\n", |
||||
idx + 1, slot); |
||||
switch (slot) { |
||||
case 1: |
||||
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | |
||||
BRDCFG1_EMI1_EN; |
||||
break; |
||||
case 2: |
||||
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | |
||||
BRDCFG1_EMI1_EN; |
||||
break; |
||||
case 3: |
||||
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 | |
||||
BRDCFG1_EMI1_EN; |
||||
break; |
||||
case 5: |
||||
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | |
||||
BRDCFG1_EMI1_EN; |
||||
break; |
||||
case 6: |
||||
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | |
||||
BRDCFG1_EMI1_EN; |
||||
break; |
||||
case 7: |
||||
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | |
||||
BRDCFG1_EMI1_EN; |
||||
break; |
||||
}; |
||||
|
||||
super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_SGMII_MDIO", |
||||
mdio_mux[i].mask, mdio_mux[i].val); |
||||
fm_info_set_mdio(i, |
||||
miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO")); |
||||
break; |
||||
case PHY_INTERFACE_MODE_RGMII: |
||||
/*
|
||||
* FM1 DTSEC5 is routed via EC1 to the first on-board |
||||
* RGMII port. FM2 DTSEC5 is routed via EC2 to the |
||||
* second on-board RGMII port. The other DTSECs cannot |
||||
* be routed to RGMII. |
||||
*/ |
||||
debug("FM1@DTSEC%u is RGMII at address %u\n", |
||||
idx + 1, 0); |
||||
fm_info_set_phy_address(i, 0); |
||||
mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; |
||||
mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | |
||||
BRDCFG1_EMI1_EN; |
||||
super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO", |
||||
mdio_mux[i].mask, mdio_mux[i].val); |
||||
fm_info_set_mdio(i, |
||||
miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO")); |
||||
break; |
||||
case PHY_INTERFACE_MODE_NONE: |
||||
fm_info_set_phy_address(i, 0); |
||||
break; |
||||
default: |
||||
printf("Fman1: DTSEC%u set to unknown interface %i\n", |
||||
idx + 1, fm_info_get_enet_if(i)); |
||||
fm_info_set_phy_address(i, 0); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
/*
|
||||
* For 10G, we only support one XAUI card per Fman. If present, then we |
||||
* force its routing and never touch those bits again, which removes the |
||||
* need for Linux to do any muxing. This works because of the way |
||||
* BRDCFG1 is defined, but it's a bit hackish. |
||||
* |
||||
* The PHY address for the XAUI card depends on which slot it's in. The |
||||
* macros we use imply that the PHY address is based on which FM, but |
||||
* that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, |
||||
* and FM2 could only use a XAUI in slot 4. On the Hydra board, we |
||||
* check the actual slot and just use the macros as-is, even though |
||||
* the P3041 and P5020 only have one Fman. |
||||
*/ |
||||
lane = serdes_get_first_lane(XAUI_FM1); |
||||
if (lane >= 0) { |
||||
debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); |
||||
mdio_mux[FM1_10GEC1].mask = BRDCFG1_EMI2_SEL_MASK; |
||||
mdio_mux[FM1_10GEC1].val = BRDCFG1_EMI2_SEL_SLOT2; |
||||
super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO", |
||||
mdio_mux[i].mask, mdio_mux[i].val); |
||||
} |
||||
|
||||
fm_info_set_mdio(FM1_10GEC1, |
||||
miiphy_get_dev_by_name("SUPER_HYDRA_FM1_TGEC_MDIO")); |
||||
|
||||
#if (CONFIG_SYS_NUM_FMAN == 2) |
||||
for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { |
||||
int idx = i - FM2_DTSEC1; |
||||
|
||||
switch (fm_info_get_enet_if(i)) { |
||||
case PHY_INTERFACE_MODE_SGMII: |
||||
lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); |
||||
if (lane < 0) |
||||
break; |
||||
slot = lane_to_slot[lane]; |
||||
mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; |
||||
debug("FM2@DTSEC%u expects SGMII in slot %u\n", |
||||
idx + 1, slot); |
||||
switch (slot) { |
||||
case 1: |
||||
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | |
||||
BRDCFG1_EMI1_EN; |
||||
break; |
||||
case 2: |
||||
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | |
||||
BRDCFG1_EMI1_EN; |
||||
break; |
||||
case 3: |
||||
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 | |
||||
BRDCFG1_EMI1_EN; |
||||
break; |
||||
case 5: |
||||
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | |
||||
BRDCFG1_EMI1_EN; |
||||
break; |
||||
case 6: |
||||
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | |
||||
BRDCFG1_EMI1_EN; |
||||
break; |
||||
case 7: |
||||
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | |
||||
BRDCFG1_EMI1_EN; |
||||
break; |
||||
}; |
||||
|
||||
super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_SGMII_MDIO", |
||||
mdio_mux[i].mask, mdio_mux[i].val); |
||||
fm_info_set_mdio(i, |
||||
miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO")); |
||||
break; |
||||
case PHY_INTERFACE_MODE_RGMII: |
||||
/*
|
||||
* FM1 DTSEC5 is routed via EC1 to the first on-board |
||||
* RGMII port. FM2 DTSEC5 is routed via EC2 to the |
||||
* second on-board RGMII port. The other DTSECs cannot |
||||
* be routed to RGMII. |
||||
*/ |
||||
debug("FM2@DTSEC%u is RGMII at address %u\n", |
||||
idx + 1, 1); |
||||
fm_info_set_phy_address(i, 1); |
||||
mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; |
||||
mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | |
||||
BRDCFG1_EMI1_EN; |
||||
super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO", |
||||
mdio_mux[i].mask, mdio_mux[i].val); |
||||
fm_info_set_mdio(i, |
||||
miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO")); |
||||
break; |
||||
case PHY_INTERFACE_MODE_NONE: |
||||
fm_info_set_phy_address(i, 0); |
||||
break; |
||||
default: |
||||
printf("Fman2: DTSEC%u set to unknown interface %i\n", |
||||
idx + 1, fm_info_get_enet_if(i)); |
||||
fm_info_set_phy_address(i, 0); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
/*
|
||||
* For 10G, we only support one XAUI card per Fman. If present, then we |
||||
* force its routing and never touch those bits again, which removes the |
||||
* need for Linux to do any muxing. This works because of the way |
||||
* BRDCFG1 is defined, but it's a bit hackish. |
||||
* |
||||
* The PHY address for the XAUI card depends on which slot it's in. The |
||||
* macros we use imply that the PHY address is based on which FM, but |
||||
* that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, |
||||
* and FM2 could only use a XAUI in slot 4. On the Hydra board, we |
||||
* check the actual slot and just use the macros as-is, even though |
||||
* the P3041 and P5020 only have one Fman. |
||||
*/ |
||||
lane = serdes_get_first_lane(XAUI_FM2); |
||||
if (lane >= 0) { |
||||
debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); |
||||
mdio_mux[FM2_10GEC1].mask = BRDCFG1_EMI2_SEL_MASK; |
||||
mdio_mux[FM2_10GEC1].val = BRDCFG1_EMI2_SEL_SLOT1; |
||||
super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO", |
||||
mdio_mux[i].mask, mdio_mux[i].val); |
||||
} |
||||
|
||||
fm_info_set_mdio(FM2_10GEC1, |
||||
miiphy_get_dev_by_name("SUPER_HYDRA_FM2_TGEC_MDIO")); |
||||
|
||||
#endif |
||||
|
||||
cpu_eth_init(bis); |
||||
#endif |
||||
|
||||
return pci_eth_init(bis); |
||||
} |
||||
@ -0,0 +1,18 @@ |
||||
/*
|
||||
* Copyright 2009-2010 Freescale Semiconductor, Inc. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License |
||||
* Version 2 as published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_ddr_sdram.h> |
||||
|
||||
fixed_ddr_parm_t fixed_ddr_parm_0[] = { |
||||
{0, 0, NULL} |
||||
}; |
||||
|
||||
fixed_ddr_parm_t fixed_ddr_parm_1[] = { |
||||
{0, 0, NULL} |
||||
}; |
||||
@ -0,0 +1,113 @@ |
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
#include <common.h> |
||||
#include <phy.h> |
||||
#include <fm_eth.h> |
||||
#include <asm/io.h> |
||||
#include <asm/immap_85xx.h> |
||||
#include <asm/fsl_serdes.h> |
||||
|
||||
u32 port_to_devdisr[] = { |
||||
[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, |
||||
[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, |
||||
[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, |
||||
[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, |
||||
[FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5, |
||||
[FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1, |
||||
[FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1, |
||||
[FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2, |
||||
[FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3, |
||||
[FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4, |
||||
[FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5, |
||||
[FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2, |
||||
}; |
||||
|
||||
static int is_device_disabled(enum fm_port port) |
||||
{ |
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
u32 devdisr2 = in_be32(&gur->devdisr2); |
||||
|
||||
return port_to_devdisr[port] & devdisr2; |
||||
} |
||||
|
||||
void fman_disable_port(enum fm_port port) |
||||
{ |
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
|
||||
/* don't allow disabling of DTSEC1 as its needed for MDIO */ |
||||
if (port == FM1_DTSEC1) |
||||
return; |
||||
|
||||
setbits_be32(&gur->devdisr2, port_to_devdisr[port]); |
||||
} |
||||
|
||||
phy_interface_t fman_port_enet_if(enum fm_port port) |
||||
{ |
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
u32 rcwsr11 = in_be32(&gur->rcwsr[11]); |
||||
|
||||
if (is_device_disabled(port)) |
||||
return PHY_INTERFACE_MODE_NONE; |
||||
|
||||
if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1))) |
||||
return PHY_INTERFACE_MODE_XGMII; |
||||
|
||||
if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2))) |
||||
return PHY_INTERFACE_MODE_XGMII; |
||||
|
||||
/* handle RGMII first */ |
||||
if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == |
||||
FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII)) |
||||
return PHY_INTERFACE_MODE_RGMII; |
||||
|
||||
if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == |
||||
FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII)) |
||||
return PHY_INTERFACE_MODE_MII; |
||||
|
||||
if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == |
||||
FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII)) |
||||
return PHY_INTERFACE_MODE_RGMII; |
||||
|
||||
if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == |
||||
FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII)) |
||||
return PHY_INTERFACE_MODE_MII; |
||||
|
||||
switch (port) { |
||||
case FM1_DTSEC1: |
||||
case FM1_DTSEC2: |
||||
case FM1_DTSEC3: |
||||
case FM1_DTSEC4: |
||||
case FM1_DTSEC5: |
||||
if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) |
||||
return PHY_INTERFACE_MODE_SGMII; |
||||
break; |
||||
case FM2_DTSEC1: |
||||
case FM2_DTSEC2: |
||||
case FM2_DTSEC3: |
||||
case FM2_DTSEC4: |
||||
case FM2_DTSEC5: |
||||
if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1)) |
||||
return PHY_INTERFACE_MODE_SGMII; |
||||
break; |
||||
default: |
||||
return PHY_INTERFACE_MODE_NONE; |
||||
} |
||||
|
||||
return PHY_INTERFACE_MODE_NONE; |
||||
} |
||||
@ -0,0 +1,40 @@ |
||||
/*
|
||||
* Copyright 2009-2011 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* P5040 DS board configuration file |
||||
* |
||||
*/ |
||||
#define CONFIG_P5040DS |
||||
#define CONFIG_PHYS_64BIT |
||||
#define CONFIG_PPC_P5040 |
||||
|
||||
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ |
||||
|
||||
#define CONFIG_MMC |
||||
#define CONFIG_NAND_FSL_ELBC |
||||
#define CONFIG_PCIE3 |
||||
#define CONFIG_SYS_FSL_RAID_ENGINE |
||||
|
||||
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ |
||||
|
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#include "corenet_ds.h" |
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