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Add command for handling DDR ECC registers on MPC8349EE MDS board.

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master
Marian Balakowicz 18 years ago
parent 97f98001a3
commit d326f4a242
4 changed files with 465 additions and 0 deletions
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  1. 2
      CHANGELOG
  2. 327
      board/mpc8349emds/mpc8349emds.c
  3. 135
      doc/README.mpc8349emds.ddrecc
  4. 1
      include/configs/MPC8349EMDS.h

2
CHANGELOG
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@ -2,6 +2,8 @@
Changes since U-Boot 1.1.4:
======================================================================
* Add command for handling DDR ECC registers on MPC8349EE MDS board.
* Fix DDR ECC bit definitions for MPC83xx.
* Add initial support for MPC8349E MDS board.

327
board/mpc8349emds/mpc8349emds.c
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@ -29,6 +29,7 @@
#include <i2c.h>
#include <spd.h>
#include <miiphy.h>
#include <command.h>
#if defined(CONFIG_PCI)
#include <pci.h>
#endif
@ -277,3 +278,329 @@ void sdram_init(void)
put("SDRAM on Local Bus is NOT available!\n");
}
#endif
#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
/*
* ECC user commands
*/
void ecc_print_status(void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
volatile ddr8349_t *ddr = &immap->ddr;
printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
/* Interrupts */
printf("Memory Error Interrupt Enable:\n");
printf(" Multiple-Bit Error Interrupt Enable: %d\n",
(ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
printf(" Single-Bit Error Interrupt Enable: %d\n",
(ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
printf(" Memory Select Error Interrupt Enable: %d\n\n",
(ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
/* Error disable */
printf("Memory Error Disable:\n");
printf(" Multiple-Bit Error Disable: %d\n",
(ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
printf(" Sinle-Bit Error Disable: %d\n",
(ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
printf(" Memory Select Error Disable: %d\n\n",
(ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
/* Error injection */
printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
ddr->data_err_inject_hi, ddr->data_err_inject_lo);
printf("Memory Data Path Error Injection Mask ECC:\n");
printf(" ECC Mirror Byte: %d\n",
(ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
printf(" ECC Injection Enable: %d\n",
(ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
printf(" ECC Error Injection Mask: 0x%02x\n\n",
ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
/* SBE counter/threshold */
printf("Memory Single-Bit Error Management (0..255):\n");
printf(" Single-Bit Error Threshold: %d\n",
(ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
printf(" Single-Bit Error Counter: %d\n\n",
(ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
/* Error detect */
printf("Memory Error Detect:\n");
printf(" Multiple Memory Errors: %d\n",
(ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
printf(" Multiple-Bit Error: %d\n",
(ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
printf(" Single-Bit Error: %d\n",
(ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
printf(" Memory Select Error: %d\n\n",
(ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
/* Capture data */
printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
ddr->capture_data_hi, ddr->capture_data_lo);
printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
ddr->capture_ecc & CAPTURE_ECC_ECE);
printf("Memory Error Attributes Capture:\n");
printf(" Data Beat Number: %d\n",
(ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT);
printf(" Transaction Size: %d\n",
(ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT);
printf(" Transaction Source: %d\n",
(ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT);
printf(" Transaction Type: %d\n",
(ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT);
printf(" Error Information Valid: %d\n\n",
ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
}
int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
volatile ddr8349_t *ddr = &immap->ddr;
volatile u32 val;
u64 *addr, count, val64;
register u64 *i;
if (argc > 4) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
if (argc == 2) {
if (strcmp(argv[1], "status") == 0) {
ecc_print_status();
return 0;
} else if (strcmp(argv[1], "captureclear") == 0) {
ddr->capture_address = 0;
ddr->capture_data_hi = 0;
ddr->capture_data_lo = 0;
ddr->capture_ecc = 0;
ddr->capture_attributes = 0;
return 0;
}
}
if (argc == 3) {
if (strcmp(argv[1], "sbecnt") == 0) {
val = simple_strtoul(argv[2], NULL, 10);
if (val > 255) {
printf("Incorrect Counter value, should be 0..255\n");
return 1;
}
val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
ddr->err_sbe = val;
return 0;
} else if (strcmp(argv[1], "sbethr") == 0) {
val = simple_strtoul(argv[2], NULL, 10);
if (val > 255) {
printf("Incorrect Counter value, should be 0..255\n");
return 1;
}
val = (val << ECC_ERROR_MAN_SBET_SHIFT);
val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
ddr->err_sbe = val;
return 0;
} else if (strcmp(argv[1], "errdisable") == 0) {
val = ddr->err_disable;
if (strcmp(argv[2], "+sbe") == 0) {
val |= ECC_ERROR_DISABLE_SBED;
} else if (strcmp(argv[2], "+mbe") == 0) {
val |= ECC_ERROR_DISABLE_MBED;
} else if (strcmp(argv[2], "+mse") == 0) {
val |= ECC_ERROR_DISABLE_MSED;
} else if (strcmp(argv[2], "+all") == 0) {
val |= (ECC_ERROR_DISABLE_SBED |
ECC_ERROR_DISABLE_MBED |
ECC_ERROR_DISABLE_MSED);
} else if (strcmp(argv[2], "-sbe") == 0) {
val &= ~ECC_ERROR_DISABLE_SBED;
} else if (strcmp(argv[2], "-mbe") == 0) {
val &= ~ECC_ERROR_DISABLE_MBED;
} else if (strcmp(argv[2], "-mse") == 0) {
val &= ~ECC_ERROR_DISABLE_MSED;
} else if (strcmp(argv[2], "-all") == 0) {
val &= ~(ECC_ERROR_DISABLE_SBED |
ECC_ERROR_DISABLE_MBED |
ECC_ERROR_DISABLE_MSED);
} else {
printf("Incorrect err_disable field\n");
return 1;
}
ddr->err_disable = val;
__asm__ __volatile__ ("sync");
__asm__ __volatile__ ("isync");
return 0;
} else if (strcmp(argv[1], "errdetectclr") == 0) {
val = ddr->err_detect;
if (strcmp(argv[2], "mme") == 0) {
val |= ECC_ERROR_DETECT_MME;
} else if (strcmp(argv[2], "sbe") == 0) {
val |= ECC_ERROR_DETECT_SBE;
} else if (strcmp(argv[2], "mbe") == 0) {
val |= ECC_ERROR_DETECT_MBE;
} else if (strcmp(argv[2], "mse") == 0) {
val |= ECC_ERROR_DETECT_MSE;
} else if (strcmp(argv[2], "all") == 0) {
val |= (ECC_ERROR_DETECT_MME |
ECC_ERROR_DETECT_MBE |
ECC_ERROR_DETECT_SBE |
ECC_ERROR_DETECT_MSE);
} else {
printf("Incorrect err_detect field\n");
return 1;
}
ddr->err_detect = val;
return 0;
} else if (strcmp(argv[1], "injectdatahi") == 0) {
val = simple_strtoul(argv[2], NULL, 16);
ddr->data_err_inject_hi = val;
return 0;
} else if (strcmp(argv[1], "injectdatalo") == 0) {
val = simple_strtoul(argv[2], NULL, 16);
ddr->data_err_inject_lo = val;
return 0;
} else if (strcmp(argv[1], "injectecc") == 0) {
val = simple_strtoul(argv[2], NULL, 16);
if (val > 0xff) {
printf("Incorrect ECC inject mask, should be 0x00..0xff\n");
return 1;
}
val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
ddr->ecc_err_inject = val;
return 0;
} else if (strcmp(argv[1], "inject") == 0) {
val = ddr->ecc_err_inject;
if (strcmp(argv[2], "en") == 0)
val |= ECC_ERR_INJECT_EIEN;
else if (strcmp(argv[2], "dis") == 0)
val &= ~ECC_ERR_INJECT_EIEN;
else
printf("Incorrect command\n");
ddr->ecc_err_inject = val;
__asm__ __volatile__ ("sync");
__asm__ __volatile__ ("isync");
return 0;
} else if (strcmp(argv[1], "mirror") == 0) {
val = ddr->ecc_err_inject;
if (strcmp(argv[2], "en") == 0)
val |= ECC_ERR_INJECT_EMB;
else if (strcmp(argv[2], "dis") == 0)
val &= ~ECC_ERR_INJECT_EMB;
else
printf("Incorrect command\n");
ddr->ecc_err_inject = val;
return 0;
}
}
if (argc == 4) {
if (strcmp(argv[1], "test") == 0) {
addr = (u64 *)simple_strtoul(argv[2], NULL, 16);
count = simple_strtoul(argv[3], NULL, 16);
if ((u32)addr % 8) {
printf("Address not alligned on double word boundary\n");
return 1;
}
disable_interrupts();
icache_disable();
for (i = addr; i < addr + count; i++) {
/* enable injects */
ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
__asm__ __volatile__ ("sync");
__asm__ __volatile__ ("isync");
/* write memory location injecting errors */
*i = 0x1122334455667788ULL;
__asm__ __volatile__ ("sync");
/* disable injects */
ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
__asm__ __volatile__ ("sync");
__asm__ __volatile__ ("isync");
/* read data, this generates ECC error */
val64 = *i;
__asm__ __volatile__ ("sync");
/* disable errors for ECC */
ddr->err_disable |= ~ECC_ERROR_ENABLE;
__asm__ __volatile__ ("sync");
__asm__ __volatile__ ("isync");
/* re-initialize memory, write the location again
* NOT injecting errors this time */
*i = 0xcafecafecafecafeULL;
__asm__ __volatile__ ("sync");
/* enable errors for ECC */
ddr->err_disable &= ECC_ERROR_ENABLE;
__asm__ __volatile__ ("sync");
__asm__ __volatile__ ("isync");
}
icache_enable();
enable_interrupts();
return 0;
}
}
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
U_BOOT_CMD(
ecc, 4, 0, do_ecc,
"ecc - support for DDR ECC features\n",
"status - print out status info\n"
"ecc captureclear - clear capture regs data\n"
"ecc sbecnt <val> - set Single-Bit Error counter\n"
"ecc sbethr <val> - set Single-Bit Threshold\n"
"ecc errdisable <flag> - clear/set disable Memory Error Disable, flag:\n"
" [-|+]sbe - Single-Bit Error\n"
" [-|+]mbe - Multiple-Bit Error\n"
" [-|+]mse - Memory Select Error\n"
" [-|+]all - all errors\n"
"ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
" mme - Multiple Memory Errors\n"
" sbe - Single-Bit Error\n"
" mbe - Multiple-Bit Error\n"
" mse - Memory Select Error\n"
" all - all errors\n"
"ecc injectdatahi <hi> - set Memory Data Path Error Injection Mask High\n"
"ecc injectdatalo <lo> - set Memory Data Path Error Injection Mask Low\n"
"ecc injectecc <ecc> - set ECC Error Injection Mask\n"
"ecc inject <en|dis> - enable/disable error injection\n"
"ecc mirror <en|dis> - enable/disable mirror byte\n"
"ecc test <addr> <cnt> - test mem region:\n"
" - enables injects\n"
" - writes pattern injecting errors\n"
" - disables injects\n"
" - reads pattern back, generates error\n"
" - re-inits memory"
);
#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */

135
doc/README.mpc8349emds.ddrecc
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@ -0,0 +1,135 @@
Use cases for DDR 'ecc' command:
================================
Before executing particular tests reset target board or clear status registers:
=> ecc captureclear
=> ecc errdetectclr all
=> ecc sbecnt 0
Injecting Single-Bit Errors
---------------------------
1. Set 1 bit in Data Path Error Inject Mask
=> ecc injectdatahi 1
2. Run test over some memory region
=> ecc test 200000 10
3. Check ECC status
=> ecc status
...
Memory Data Path Error Injection Mask High/Low: 00000001 00000000
...
Memory Single-Bit Error Management (0..255):
Single-Bit Error Threshold: 255
Single Bit Error Counter: 16
...
Memory Error Detect:
Multiple Memory Errors: 0
Multiple-Bit Error: 0
Single-Bit Error: 0
...
16 errors were generated, Single-Bit Error flag was not set as Single Bit Error
Counter did not reach Single-Bit Error Threshold.
4. Make sure used memory region got re-initialized with 0xcafecafe pattern
=> md 200000
00200000: cafecafe cafecafe cafecafe cafecafe ................
00200010: cafecafe cafecafe cafecafe cafecafe ................
00200020: cafecafe cafecafe cafecafe cafecafe ................
00200030: cafecafe cafecafe cafecafe cafecafe ................
00200040: cafecafe cafecafe cafecafe cafecafe ................
00200050: cafecafe cafecafe cafecafe cafecafe ................
00200060: cafecafe cafecafe cafecafe cafecafe ................
00200070: cafecafe cafecafe cafecafe cafecafe ................
00200080: deadbeef deadbeef deadbeef deadbeef ................
00200090: deadbeef deadbeef deadbeef deadbeef ................
Injecting Multiple-Bit Errors
-----------------------------
1. Set more than 1 bit in Data Path Error Inject Mask
=> ecc injectdatahi 5
2. Run test over some memory region
=> ecc test 200000 10
3. Check ECC status
=> ecc status
...
Memory Data Path Error Injection Mask High/Low: 00000005 00000000
...
Memory Error Detect:
Multiple Memory Errors: 1
Multiple-Bit Error: 1
Single-Bit Error: 0
...
Observe that both Multiple Memory Errors and Multiple-Bit Error flags are set.
4. Make sure used memory region got re-initialized with 0xcafecafe pattern
=> md 200000
00200000: cafecafe cafecafe cafecafe cafecafe ................
00200010: cafecafe cafecafe cafecafe cafecafe ................
00200020: cafecafe cafecafe cafecafe cafecafe ................
00200030: cafecafe cafecafe cafecafe cafecafe ................
00200040: cafecafe cafecafe cafecafe cafecafe ................
00200050: cafecafe cafecafe cafecafe cafecafe ................
00200060: cafecafe cafecafe cafecafe cafecafe ................
00200070: cafecafe cafecafe cafecafe cafecafe ................
00200080: deadbeef deadbeef deadbeef deadbeef ................
00200090: deadbeef deadbeef deadbeef deadbeef ................
Test Single-Bit Error Counter and Threshold
-------------------------------------------
1. Set 1 bit in Data Path Error Inject Mask
=> ecc injectdatahi 1
2. Enable error injection
=> ecc inject en
3. Let u-boot run for a with Single-Bit error injection enabled
4. Disable error injection
=> ecc inject dis
4. Check status
=> ecc status
...
Memory Single-Bit Error Management (0..255):
Single-Bit Error Threshold: 255
Single Bit Error Counter: 60
Memory Error Detect:
Multiple Memory Errors: 1
Multiple-Bit Error: 0
Single-Bit Error: 1
...
Observe that Single-Bit Error is 'on' which means that Single-Bit Error Counter
reached Single-Bit Error Threshold. Multiple Memory Errors bit is also 'on', that
is Counter reached Threshold more than one time (it wraps back after reaching
Threshold).

1
include/configs/MPC8349EMDS.h
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@ -70,6 +70,7 @@
* DDR Setup
*/
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/

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