x86: ivybridge: Do the SATA init before relocation

The SATA device needs to set itself up so that it appears correctly on the
PCI bus. The easiest way to do this is to set it up to probe before
relocation. This can do the early setup.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

arch/x86/cpu/ivybridge/bd82x6x.c

@@ -69,8 +69,6 @@ int bd82x6x_init_extra(void)
 		return -EINVAL;
 	}
 
-	bd82x6x_sata_enable(PCH_SATA_DEV, blob, sata_node);
-
 	return 0;
 }
 

arch/x86/cpu/ivybridge/cpu.c

@@ -251,6 +251,9 @@ int print_cpuinfo(void)
 	if (!dev)
 		return -ENODEV;
 
+	/* Cause the SATA device to do its early init */
+	uclass_first_device(UCLASS_DISK, &dev);
+
 	/* Check PM1_STS[15] to see if we are waking from Sx */
 	pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
 

arch/x86/cpu/ivybridge/sata.c

@@ -6,12 +6,15 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <fdtdec.h>
 #include <asm/io.h>
 #include <asm/pci.h>
 #include <asm/arch/pch.h>
 #include <asm/arch/bd82x6x.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static inline u32 sir_read(pci_dev_t dev, int idx)
 {
 	x86_pci_write_config32(dev, SATA_SIRI, idx);
@@ -206,7 +209,7 @@ void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node)
 	pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);
 }
 
-void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node)
+static void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node)
 {
 	unsigned port_map;
 	const char *mode;
@@ -224,3 +227,23 @@ void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node)
 	map |= (port_map ^ 0x3f) << 8;
 	x86_pci_write_config16(dev, 0x90, map);
 }
+
+static int bd82x6x_sata_probe(struct udevice *dev)
+{
+	if (!(gd->flags & GD_FLG_RELOC))
+		bd82x6x_sata_enable(PCH_SATA_DEV, gd->fdt_blob, dev->of_offset);
+
+	return 0;
+}
+
+static const struct udevice_id bd82x6x_ahci_ids[] = {
+	{ .compatible = "intel,pantherpoint-ahci" },
+	{ }
+};
+
+U_BOOT_DRIVER(ahci_ivybridge_drv) = {
+	.name		= "ahci_ivybridge",
+	.id		= UCLASS_DISK,
+	.of_match	= bd82x6x_ahci_ids,
+	.probe		= bd82x6x_sata_probe,
+};

arch/x86/dts/chromebook_link.dts

@@ -207,13 +207,6 @@
 			u-boot,dm-pre-reloc;
 		};
 
-		sata {
-			compatible = "intel,pantherpoint-ahci";
-			intel,sata-mode = "ahci";
-			intel,sata-port-map = <1>;
-			intel,sata-port0-gen3-tx = <0x00880a7f>;
-		};
-
 		gma {
 			compatible = "intel,gma";
 			intel,dp_hotplug = <0 0 0x06>;
@@ -281,6 +274,15 @@
 				};
 			};
 		};
+
+		sata@1f,2 {
+			compatible = "intel,pantherpoint-ahci";
+			reg = <0x0000fa00 0 0 0 0>;
+			u-boot,dm-pre-reloc;
+			intel,sata-mode = "ahci";
+			intel,sata-port-map = <1>;
+			intel,sata-port0-gen3-tx = <0x00880a7f>;
+		};
 	};
 
 	tpm {

arch/x86/include/asm/arch-ivybridge/bd82x6x.h

@@ -8,7 +8,6 @@
 #define _ASM_ARCH_BD82X6X_H
 
 void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node);
-void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node);
 void bd82x6x_usb_ehci_init(pci_dev_t dev);
 void bd82x6x_usb_xhci_init(pci_dev_t dev);
 int gma_func0_init(struct udevice *dev, const void *blob, int node);