Andy Fleming
18 years ago
committed by
Andrew Fleming-AFLEMING
commit
d4d1e9bee7
@ -0,0 +1,51 @@ |
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS := conxs.o eeprom.o
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SOBJS := lowlevel_init.o pxavoltage.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,3 @@ |
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TEXT_BASE =0xa1f00000
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# 0xa1700000
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#TEXT_BASE = 0
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@ -0,0 +1,146 @@ |
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/*
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* (C) Copyright 2007 |
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* Stefano Babic, DENX Gmbh, sbabic@denx.de |
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* |
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* (C) Copyright 2004 |
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* Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net |
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* |
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* (C) Copyright 2002 |
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
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* |
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Marius Groeger <mgroeger@sysgo.de> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/arch/pxa-regs.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define RH_A_PSM (1 << 8) /* power switching mode */ |
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#define RH_A_NPS (1 << 9) /* no power switching */ |
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extern struct serial_device serial_ffuart_device; |
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extern struct serial_device serial_btuart_device; |
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extern struct serial_device serial_stuart_device; |
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/* ------------------------------------------------------------------------- */ |
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/*
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* Miscelaneous platform dependent initialisations |
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*/ |
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void usb_board_init(void) |
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{ |
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UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & |
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~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE); |
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UHCHR |= UHCHR_FSBIR; |
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while (UHCHR & UHCHR_FSBIR); |
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UHCHR &= ~UHCHR_SSE; |
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UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE); |
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/* Clear any OTG Pin Hold */ |
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if (PSSR & PSSR_OTGPH) |
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PSSR |= PSSR_OTGPH; |
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UHCRHDA &= ~(RH_A_NPS); |
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UHCRHDA |= RH_A_PSM; |
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/* Set port power control mask bits, only 3 ports. */ |
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UHCRHDB |= (0x7<<17); |
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} |
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void usb_board_init_fail(void) |
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{ |
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return; |
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} |
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void usb_board_stop(void) |
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{ |
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UHCHR |= UHCHR_FHR; |
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udelay(11); |
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UHCHR &= ~UHCHR_FHR; |
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UHCCOMS |= 1; |
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udelay(10); |
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CKEN &= ~CKEN10_USBHOST; |
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puts("Called USB STOP\n"); |
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return; |
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} |
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int board_init (void) |
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{ |
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/* memory and cpu-speed are setup before relocation */ |
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/* so we do _nothing_ here */ |
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/* arch number of ConXS Board */ |
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gd->bd->bi_arch_number = 776; |
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = 0xa000003c; |
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return 0; |
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} |
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int board_late_init(void) |
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{ |
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#if defined(CONFIG_SERIAL_MULTI) |
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char *console=getenv("boot_console"); |
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if ((strcmp(console,"serial_btuart") == 0) || |
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(strcmp(console,"serial_stuart") == 0) || |
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(strcmp(console,"serial_ffuart") == 0)) { |
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setenv("stdout",console); |
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setenv("stdin", console); |
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setenv("stderr",console); |
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} else { |
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setenv("stdout", "serial"); |
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setenv("stdin", "serial"); |
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setenv("stderr", "serial"); |
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} |
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#endif |
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return 0; |
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} |
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struct serial_device *default_serial_console (void) |
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{ |
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return &serial_ffuart_device; |
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} |
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int dram_init (void) |
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{ |
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2; |
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; |
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gd->bd->bi_dram[2].start = PHYS_SDRAM_3; |
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gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; |
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gd->bd->bi_dram[3].start = PHYS_SDRAM_4; |
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gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; |
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return 0; |
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} |
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@ -0,0 +1,85 @@ |
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/*
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* (C) Copyright 2007 |
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <command.h> |
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static unsigned char srom[128]; |
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extern u16 read_srom_word(int); |
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extern void write_srom_word(int offset, u16 val); |
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static int do_read_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { |
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int i; |
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for (i=0; i < 0x40; i++) { |
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if (!(i % 0x10)) |
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printf("\n%08lx:", i); |
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printf(" %04x", read_srom_word(i)); |
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} |
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printf ("\n"); |
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return (0); |
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} |
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static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { |
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int offset,value; |
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if (argc < 4) { |
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printf ("Usage:\n%s\n", cmdtp->usage); |
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return 1; |
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} |
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offset=simple_strtoul(argv[2],NULL,16); |
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value=simple_strtoul(argv[3],NULL,16); |
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if (offset > 0x40) { |
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printf("Wrong offset : 0x%x\n",offset); |
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printf ("Usage:\n%s\n", cmdtp->usage); |
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return 1; |
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} |
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write_srom_word(offset, value); |
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return (0); |
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} |
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int do_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { |
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if (argc < 2) { |
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printf ("Usage:\n%s\n", cmdtp->usage); |
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return 1; |
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} |
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if (strcmp (argv[1],"read") == 0) { |
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return (do_read_dm9000_eeprom(cmdtp,flag,argc,argv)); |
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} else if (strcmp (argv[1],"write") == 0) { |
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return (do_write_dm9000_eeprom(cmdtp,flag,argc,argv)); |
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} else { |
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printf ("Usage:\n%s\n", cmdtp->usage); |
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return 1; |
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} |
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} |
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U_BOOT_CMD( |
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dm9000ee,4,1,do_dm9000_eeprom, |
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"dm9000ee- Read/Write eeprom connected to Ethernet Controller\n", |
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"\ndm9000ee write <word offset> <value> \n" |
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"\tdm9000ee read \n" |
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"\tword:\t\t00-02 : MAC Address\n" |
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"\t\t\t03-07 : DM9000 Configuration\n" |
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"\t\t\t08-63 : User data\n"); |
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@ -0,0 +1,503 @@ |
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/* |
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* This was originally from the Lubbock u-boot port. |
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* |
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* Most of this taken from Redboot hal_platform_setup.h with cleanup |
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* |
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* NOTE: I haven't clean this up considerably, just enough to get it |
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* running. See hal_platform_setup.h for the source. See |
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* board/cradle/lowlevel_init.S for another PXA250 setup that is |
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* much cleaner. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <config.h> |
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#include <version.h> |
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#include <asm/arch/pxa-regs.h> |
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/* wait for coprocessor write complete */ |
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.macro CPWAIT reg |
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mrc p15,0,\reg,c2,c0,0 |
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mov \reg,\reg |
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sub pc,pc,#4 |
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.endm |
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/* |
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* Memory setup |
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*/ |
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.globl lowlevel_init
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lowlevel_init: |
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/* Set up GPIO pins first ----------------------------------------- */ |
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ldr r0, =GPSR0 |
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ldr r1, =CFG_GPSR0_VAL |
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str r1, [r0] |
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ldr r0, =GPSR1 |
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ldr r1, =CFG_GPSR1_VAL |
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str r1, [r0] |
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ldr r0, =GPSR2 |
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ldr r1, =CFG_GPSR2_VAL |
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str r1, [r0] |
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ldr r0, =GPSR3 |
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ldr r1, =CFG_GPSR3_VAL |
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str r1, [r0] |
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ldr r0, =GPCR0 |
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ldr r1, =CFG_GPCR0_VAL |
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str r1, [r0] |
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ldr r0, =GPCR1 |
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ldr r1, =CFG_GPCR1_VAL |
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str r1, [r0] |
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ldr r0, =GPCR2 |
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ldr r1, =CFG_GPCR2_VAL |
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str r1, [r0] |
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ldr r0, =GPCR3 |
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ldr r1, =CFG_GPCR3_VAL |
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str r1, [r0] |
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ldr r0, =GRER0 |
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ldr r1, =CFG_GRER0_VAL |
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str r1, [r0] |
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ldr r0, =GRER1 |
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ldr r1, =CFG_GRER1_VAL |
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str r1, [r0] |
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ldr r0, =GRER2 |
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ldr r1, =CFG_GRER2_VAL |
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str r1, [r0] |
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ldr r0, =GRER3 |
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ldr r1, =CFG_GRER3_VAL |
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str r1, [r0] |
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ldr r0, =GFER0 |
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ldr r1, =CFG_GFER0_VAL |
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str r1, [r0] |
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ldr r0, =GFER1 |
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ldr r1, =CFG_GFER1_VAL |
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str r1, [r0] |
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ldr r0, =GFER2 |
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ldr r1, =CFG_GFER2_VAL |
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str r1, [r0] |
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ldr r0, =GFER3 |
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ldr r1, =CFG_GFER3_VAL |
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str r1, [r0] |
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ldr r0, =GPDR0 |
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ldr r1, =CFG_GPDR0_VAL |
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str r1, [r0] |
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ldr r0, =GPDR1 |
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ldr r1, =CFG_GPDR1_VAL |
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str r1, [r0] |
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ldr r0, =GPDR2 |
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ldr r1, =CFG_GPDR2_VAL |
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str r1, [r0] |
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|
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ldr r0, =GPDR3 |
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ldr r1, =CFG_GPDR3_VAL |
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str r1, [r0] |
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|
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ldr r0, =GAFR0_L |
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ldr r1, =CFG_GAFR0_L_VAL |
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str r1, [r0] |
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|
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ldr r0, =GAFR0_U |
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ldr r1, =CFG_GAFR0_U_VAL |
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str r1, [r0] |
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|
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ldr r0, =GAFR1_L |
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ldr r1, =CFG_GAFR1_L_VAL |
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str r1, [r0] |
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|
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ldr r0, =GAFR1_U |
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ldr r1, =CFG_GAFR1_U_VAL |
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str r1, [r0] |
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|
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ldr r0, =GAFR2_L |
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ldr r1, =CFG_GAFR2_L_VAL |
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str r1, [r0] |
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|
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ldr r0, =GAFR2_U |
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ldr r1, =CFG_GAFR2_U_VAL |
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str r1, [r0] |
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|
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ldr r0, =GAFR3_L |
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ldr r1, =CFG_GAFR3_L_VAL |
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str r1, [r0] |
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|
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ldr r0, =GAFR3_U |
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ldr r1, =CFG_GAFR3_U_VAL |
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str r1, [r0] |
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|
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ldr r0, =PSSR /* enable GPIO pins */ |
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ldr r1, =CFG_PSSR_VAL |
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str r1, [r0] |
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|
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/* ---------------------------------------------------------------- */ |
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/* Enable memory interface */ |
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/* */ |
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/* The sequence below is based on the recommended init steps */ |
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/* detailed in the Intel PXA250 Operating Systems Developers Guide, */ |
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/* Chapter 10. */ |
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/* ---------------------------------------------------------------- */ |
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|
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/* ---------------------------------------------------------------- */ |
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/* Step 1: Wait for at least 200 microsedonds to allow internal */ |
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/* clocks to settle. Only necessary after hard reset... */ |
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/* FIXME: can be optimized later */ |
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/* ---------------------------------------------------------------- */ |
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|
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ldr r3, =OSCR /* reset the OS Timer Count to zero */ |
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mov r2, #0 |
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str r2, [r3] |
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ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ |
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/* so 0x300 should be plenty */ |
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1: |
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ldr r2, [r3] |
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cmp r4, r2 |
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bgt 1b |
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|
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mem_init: |
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|
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ldr r1, =MEMC_BASE /* get memory controller base addr. */ |
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|
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/* ---------------------------------------------------------------- */ |
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/* Step 2a: Initialize Asynchronous static memory controller */ |
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/* ---------------------------------------------------------------- */ |
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|
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/* MSC registers: timing, bus width, mem type */ |
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|
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/* MSC0: nCS(0,1) */ |
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ldr r2, =CFG_MSC0_VAL |
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str r2, [r1, #MSC0_OFFSET] |
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ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ |
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/* that data latches */ |
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/* MSC1: nCS(2,3) */ |
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ldr r2, =CFG_MSC1_VAL |
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str r2, [r1, #MSC1_OFFSET] |
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ldr r2, [r1, #MSC1_OFFSET] |
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|
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/* MSC2: nCS(4,5) */ |
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ldr r2, =CFG_MSC2_VAL |
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str r2, [r1, #MSC2_OFFSET] |
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ldr r2, [r1, #MSC2_OFFSET] |
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|
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/* ---------------------------------------------------------------- */ |
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/* Step 2b: Initialize Card Interface */ |
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/* ---------------------------------------------------------------- */ |
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|
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/* MECR: Memory Expansion Card Register */ |
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ldr r2, =CFG_MECR_VAL |
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str r2, [r1, #MECR_OFFSET] |
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ldr r2, [r1, #MECR_OFFSET] |
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|
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/* MCMEM0: Card Interface slot 0 timing */ |
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ldr r2, =CFG_MCMEM0_VAL |
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str r2, [r1, #MCMEM0_OFFSET] |
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ldr r2, [r1, #MCMEM0_OFFSET] |
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|
||||
/* MCMEM1: Card Interface slot 1 timing */ |
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ldr r2, =CFG_MCMEM1_VAL |
||||
str r2, [r1, #MCMEM1_OFFSET] |
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ldr r2, [r1, #MCMEM1_OFFSET] |
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|
||||
/* MCATT0: Card Interface Attribute Space Timing, slot 0 */ |
||||
ldr r2, =CFG_MCATT0_VAL |
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str r2, [r1, #MCATT0_OFFSET] |
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ldr r2, [r1, #MCATT0_OFFSET] |
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|
||||
/* MCATT1: Card Interface Attribute Space Timing, slot 1 */ |
||||
ldr r2, =CFG_MCATT1_VAL |
||||
str r2, [r1, #MCATT1_OFFSET] |
||||
ldr r2, [r1, #MCATT1_OFFSET] |
||||
|
||||
/* MCIO0: Card Interface I/O Space Timing, slot 0 */ |
||||
ldr r2, =CFG_MCIO0_VAL |
||||
str r2, [r1, #MCIO0_OFFSET] |
||||
ldr r2, [r1, #MCIO0_OFFSET] |
||||
|
||||
/* MCIO1: Card Interface I/O Space Timing, slot 1 */ |
||||
ldr r2, =CFG_MCIO1_VAL |
||||
str r2, [r1, #MCIO1_OFFSET] |
||||
ldr r2, [r1, #MCIO1_OFFSET] |
||||
|
||||
/* ---------------------------------------------------------------- */ |
||||
/* Step 2c: Write FLYCNFG FIXME: what's that??? */ |
||||
/* ---------------------------------------------------------------- */ |
||||
ldr r2, =CFG_FLYCNFG_VAL |
||||
str r2, [r1, #FLYCNFG_OFFSET] |
||||
str r2, [r1, #FLYCNFG_OFFSET] |
||||
|
||||
/* ---------------------------------------------------------------- */ |
||||
/* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ |
||||
/* ---------------------------------------------------------------- */ |
||||
|
||||
/* Before accessing MDREFR we need a valid DRI field, so we set */ |
||||
/* this to power on defaults + DRI field. */ |
||||
|
||||
ldr r4, [r1, #MDREFR_OFFSET] |
||||
ldr r2, =0xFFF |
||||
bic r4, r4, r2 |
||||
|
||||
ldr r3, =CFG_MDREFR_VAL |
||||
and r3, r3, r2 |
||||
|
||||
orr r4, r4, r3 |
||||
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ |
||||
|
||||
orr r4, r4, #MDREFR_K0RUN |
||||
orr r4, r4, #MDREFR_K0DB4 |
||||
orr r4, r4, #MDREFR_K0FREE |
||||
orr r4, r4, #MDREFR_K0DB2 |
||||
orr r4, r4, #MDREFR_K1DB2 |
||||
bic r4, r4, #MDREFR_K1FREE |
||||
bic r4, r4, #MDREFR_K2FREE |
||||
|
||||
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ |
||||
ldr r4, [r1, #MDREFR_OFFSET] |
||||
|
||||
/* Note: preserve the mdrefr value in r4 */ |
||||
|
||||
|
||||
/* ---------------------------------------------------------------- */ |
||||
/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ |
||||
/* ---------------------------------------------------------------- */ |
||||
|
||||
/* Initialize SXCNFG register. Assert the enable bits */ |
||||
|
||||
/* Write SXMRS to cause an MRS command to all enabled banks of */ |
||||
/* synchronous static memory. Note that SXLCR need not be written */ |
||||
/* at this time. */ |
||||
|
||||
ldr r2, =CFG_SXCNFG_VAL |
||||
str r2, [r1, #SXCNFG_OFFSET] |
||||
|
||||
/* ---------------------------------------------------------------- */ |
||||
/* Step 4: Initialize SDRAM */ |
||||
/* ---------------------------------------------------------------- */ |
||||
|
||||
bic r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE) |
||||
|
||||
orr r4, r4, #MDREFR_K1RUN |
||||
bic r4, r4, #MDREFR_K2DB2 |
||||
str r4, [r1, #MDREFR_OFFSET] |
||||
ldr r4, [r1, #MDREFR_OFFSET] |
||||
|
||||
bic r4, r4, #MDREFR_SLFRSH |
||||
str r4, [r1, #MDREFR_OFFSET] |
||||
ldr r4, [r1, #MDREFR_OFFSET] |
||||
|
||||
orr r4, r4, #MDREFR_E1PIN |
||||
str r4, [r1, #MDREFR_OFFSET] |
||||
ldr r4, [r1, #MDREFR_OFFSET] |
||||
|
||||
nop |
||||
nop |
||||
|
||||
|
||||
/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ |
||||
/* configure but not enable each SDRAM partition pair. */ |
||||
|
||||
ldr r4, =CFG_MDCNFG_VAL |
||||
bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) |
||||
bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) |
||||
|
||||
str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ |
||||
ldr r4, [r1, #MDCNFG_OFFSET] |
||||
|
||||
|
||||
/* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ |
||||
/* 100..200 µsec. */ |
||||
|
||||
ldr r3, =OSCR /* reset the OS Timer Count to zero */ |
||||
mov r2, #0 |
||||
str r2, [r3] |
||||
ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ |
||||
/* so 0x300 should be plenty */ |
||||
1: |
||||
ldr r2, [r3] |
||||
cmp r4, r2 |
||||
bgt 1b |
||||
|
||||
|
||||
/* Step 4f: Trigger a number (usually 8) refresh cycles by */ |
||||
/* attempting non-burst read or write accesses to disabled */ |
||||
/* SDRAM, as commonly specified in the power up sequence */ |
||||
/* documented in SDRAM data sheets. The address(es) used */ |
||||
/* for this purpose must not be cacheable. */ |
||||
|
||||
ldr r3, =CFG_DRAM_BASE |
||||
str r2, [r3] |
||||
str r2, [r3] |
||||
str r2, [r3] |
||||
str r2, [r3] |
||||
str r2, [r3] |
||||
str r2, [r3] |
||||
str r2, [r3] |
||||
str r2, [r3] |
||||
|
||||
|
||||
/* Step 4g: Write MDCNFG with enable bits asserted */ |
||||
/* (MDCNFG:DEx set to 1). */ |
||||
|
||||
ldr r3, [r1, #MDCNFG_OFFSET] |
||||
mov r4, r3 |
||||
orr r3, r3, #MDCNFG_DE0 |
||||
str r3, [r1, #MDCNFG_OFFSET] |
||||
mov r0, r3 |
||||
|
||||
/* Step 4h: Write MDMRS. */ |
||||
|
||||
ldr r2, =CFG_MDMRS_VAL |
||||
str r2, [r1, #MDMRS_OFFSET] |
||||
|
||||
/* enable APD */ |
||||
ldr r3, [r1, #MDREFR_OFFSET] |
||||
orr r3, r3, #MDREFR_APD |
||||
str r3, [r1, #MDREFR_OFFSET] |
||||
|
||||
/* We are finished with Intel's memory controller initialisation */ |
||||
|
||||
|
||||
setvoltage: |
||||
|
||||
mov r10, lr |
||||
bl initPXAvoltage /* In case the board is rebooting with a */ |
||||
mov lr, r10 /* low voltage raise it up to a good one. */ |
||||
|
||||
#if 1 |
||||
b initirqs |
||||
#endif |
||||
|
||||
wakeup: |
||||
/* Are we waking from sleep? */ |
||||
ldr r0, =RCSR |
||||
ldr r1, [r0] |
||||
and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR) |
||||
str r1, [r0] |
||||
teq r1, #RCSR_SMR |
||||
|
||||
bne initirqs |
||||
|
||||
ldr r0, =PSSR |
||||
mov r1, #PSSR_PH |
||||
str r1, [r0] |
||||
|
||||
/* if so, resume at PSPR */ |
||||
ldr r0, =PSPR |
||||
ldr r1, [r0] |
||||
mov pc, r1 |
||||
|
||||
/* ---------------------------------------------------------------- */ |
||||
/* Disable (mask) all interrupts at interrupt controller */ |
||||
/* ---------------------------------------------------------------- */ |
||||
|
||||
initirqs: |
||||
|
||||
mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ |
||||
ldr r2, =ICLR |
||||
str r1, [r2] |
||||
|
||||
ldr r2, =ICMR /* mask all interrupts at the controller */ |
||||
str r1, [r2] |
||||
|
||||
/* ---------------------------------------------------------------- */ |
||||
/* Clock initialisation */ |
||||
/* ---------------------------------------------------------------- */ |
||||
|
||||
initclks: |
||||
|
||||
/* Disable the peripheral clocks, and set the core clock frequency */ |
||||
|
||||
/* Turn Off on-chip peripheral clocks (except for memory) */ |
||||
/* for re-configuration. */ |
||||
ldr r1, =CKEN |
||||
ldr r2, =CFG_CKEN |
||||
str r2, [r1] |
||||
|
||||
/* ... and write the core clock config register */ |
||||
ldr r2, =CFG_CCCR |
||||
ldr r1, =CCCR |
||||
str r2, [r1] |
||||
|
||||
/* Turn on turbo mode */ |
||||
mrc p14, 0, r2, c6, c0, 0 |
||||
orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/ |
||||
mcr p14, 0, r2, c6, c0, 0 |
||||
|
||||
/* Re-write MDREFR */ |
||||
ldr r1, =MEMC_BASE |
||||
ldr r2, [r1, #MDREFR_OFFSET] |
||||
str r2, [r1, #MDREFR_OFFSET] |
||||
#ifdef RTC |
||||
/* enable the 32Khz oscillator for RTC and PowerManager */ |
||||
ldr r1, =OSCC |
||||
mov r2, #OSCC_OON |
||||
str r2, [r1] |
||||
|
||||
/* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ |
||||
/* has settled. */ |
||||
60: |
||||
ldr r2, [r1] |
||||
ands r2, r2, #1 |
||||
beq 60b |
||||
#else |
||||
#error "RTC not defined" |
||||
#endif |
||||
|
||||
/* Interrupt init: Mask all interrupts */ |
||||
ldr r0, =ICMR /* enable no sources */ |
||||
mov r1, #0 |
||||
str r1, [r0] |
||||
/* FIXME */ |
||||
|
||||
#ifdef NODEBUG |
||||
/*Disable software and data breakpoints */ |
||||
mov r0,#0 |
||||
mcr p15,0,r0,c14,c8,0 /* ibcr0 */ |
||||
mcr p15,0,r0,c14,c9,0 /* ibcr1 */ |
||||
mcr p15,0,r0,c14,c4,0 /* dbcon */ |
||||
|
||||
/*Enable all debug functionality */ |
||||
mov r0,#0x80000000 |
||||
mcr p14,0,r0,c10,c0,0 /* dcsr */ |
||||
#endif |
||||
|
||||
/* ---------------------------------------------------------------- */ |
||||
/* End lowlevel_init */ |
||||
/* ---------------------------------------------------------------- */ |
||||
|
||||
endlowlevel_init: |
||||
|
||||
mov pc, lr |
||||
@ -0,0 +1,56 @@ |
||||
/* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
|
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
cpu/pxa/start.o (.text) |
||||
*(.text) |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
.rodata : { *(.rodata) } |
||||
|
||||
. = ALIGN(4); |
||||
.data : { *(.data) } |
||||
|
||||
. = ALIGN(4); |
||||
.got : { *(.got) } |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
. = ALIGN(4); |
||||
__bss_start = .; |
||||
.bss : { *(.bss) } |
||||
_end = .; |
||||
} |
||||
@ -0,0 +1,155 @@ |
||||
/*
|
||||
* U-Boot command for OneNAND support |
||||
* |
||||
* Copyright (C) 2005-2007 Samsung Electronics |
||||
* Kyungmin Park <kyungmin.park@samsung.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
|
||||
#ifdef CONFIG_CMD_ONENAND |
||||
|
||||
#include <linux/mtd/compat.h> |
||||
#include <linux/mtd/mtd.h> |
||||
#include <linux/mtd/onenand.h> |
||||
|
||||
#include <asm/io.h> |
||||
|
||||
extern struct mtd_info onenand_mtd; |
||||
extern struct onenand_chip onenand_chip; |
||||
|
||||
int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
int ret = 0; |
||||
|
||||
switch (argc) { |
||||
case 0: |
||||
case 1: |
||||
printf("Usage:\n%s\n", cmdtp->usage); |
||||
return 1; |
||||
|
||||
case 2: |
||||
if (strncmp(argv[1], "open", 4) == 0) { |
||||
onenand_init(); |
||||
return 0; |
||||
} |
||||
onenand_print_device_info(onenand_chip.device_id, 1); |
||||
return 0; |
||||
|
||||
default: |
||||
/* At least 4 args */ |
||||
if (strncmp(argv[1], "erase", 5) == 0) { |
||||
struct erase_info instr; |
||||
ulong start, end; |
||||
ulong block; |
||||
|
||||
start = simple_strtoul(argv[2], NULL, 10); |
||||
end = simple_strtoul(argv[3], NULL, 10); |
||||
start -= (unsigned long)onenand_chip.base; |
||||
end -= (unsigned long)onenand_chip.base; |
||||
|
||||
if (!end || end < 0) |
||||
end = start; |
||||
|
||||
printf("Erase block from %d to %d\n", start, end); |
||||
|
||||
for (block = start; block <= end; block++) { |
||||
instr.addr = block << onenand_chip.erase_shift; |
||||
instr.len = 1 << onenand_chip.erase_shift; |
||||
ret = onenand_erase(&onenand_mtd, &instr); |
||||
if (ret) { |
||||
printf("erase failed %d\n", block); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
if (strncmp(argv[1], "read", 4) == 0) { |
||||
ulong addr = simple_strtoul(argv[2], NULL, 16); |
||||
ulong ofs = simple_strtoul(argv[3], NULL, 16); |
||||
size_t len = simple_strtoul(argv[4], NULL, 16); |
||||
size_t retlen = 0; |
||||
int oob = strncmp(argv[1], "read.oob", 8) ? 0 : 1; |
||||
|
||||
ofs -= (unsigned long)onenand_chip.base; |
||||
|
||||
if (oob) |
||||
onenand_read_oob(&onenand_mtd, ofs, len, |
||||
&retlen, (u_char *) addr); |
||||
else |
||||
onenand_read(&onenand_mtd, ofs, len, &retlen, |
||||
(u_char *) addr); |
||||
printf("Done\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
if (strncmp(argv[1], "write", 5) == 0) { |
||||
ulong addr = simple_strtoul(argv[2], NULL, 16); |
||||
ulong ofs = simple_strtoul(argv[3], NULL, 16); |
||||
size_t len = simple_strtoul(argv[4], NULL, 16); |
||||
size_t retlen = 0; |
||||
|
||||
ofs -= (unsigned long)onenand_chip.base; |
||||
|
||||
onenand_write(&onenand_mtd, ofs, len, &retlen, |
||||
(u_char *) addr); |
||||
printf("Done\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
if (strncmp(argv[1], "block", 5) == 0) { |
||||
ulong addr = simple_strtoul(argv[2], NULL, 16); |
||||
ulong block = simple_strtoul(argv[3], NULL, 10); |
||||
ulong page = simple_strtoul(argv[4], NULL, 10); |
||||
size_t len = simple_strtol(argv[5], NULL, 10); |
||||
size_t retlen = 0; |
||||
ulong ofs; |
||||
int oob = strncmp(argv[1], "block.oob", 9) ? 0 : 1; |
||||
|
||||
ofs = block << onenand_chip.erase_shift; |
||||
if (page) |
||||
ofs += page << onenand_chip.page_shift; |
||||
|
||||
if (!len) { |
||||
if (oob) |
||||
len = 64; |
||||
else |
||||
len = 512; |
||||
} |
||||
|
||||
if (oob) |
||||
onenand_read_oob(&onenand_mtd, ofs, len, |
||||
&retlen, (u_char *) addr); |
||||
else |
||||
onenand_read(&onenand_mtd, ofs, len, &retlen, |
||||
(u_char *) addr); |
||||
return 0; |
||||
} |
||||
|
||||
break; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
U_BOOT_CMD( |
||||
onenand, 6, 1, do_onenand, |
||||
"onenand - OneNAND sub-system\n", |
||||
"info - show available OneNAND devices\n" |
||||
"onenand read[.oob] addr ofs len - read data at ofs with len to addr\n" |
||||
"onenand write addr ofs len - write data at ofs with len from addr\n" |
||||
"onenand erase saddr eaddr - erase block start addr to end addr\n" |
||||
"onenand block[.oob] addr block [page] [len] - " |
||||
"read data with (block [, page]) to addr" |
||||
); |
||||
|
||||
#endif /* CONFIG_CMD_ONENAND */ |
||||
@ -0,0 +1,134 @@ |
||||
/*
|
||||
* (C) Copyright 2005-2007 Samsung Electronics |
||||
* Kyungmin Park <kyungmin.park@samsung.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#if defined(CFG_ENV_IS_IN_ONENAND) /* Environment is in OneNAND */ |
||||
|
||||
#include <command.h> |
||||
#include <environment.h> |
||||
#include <linux/stddef.h> |
||||
#include <malloc.h> |
||||
|
||||
#include <linux/mtd/compat.h> |
||||
#include <linux/mtd/mtd.h> |
||||
#include <linux/mtd/onenand.h> |
||||
|
||||
extern struct mtd_info onenand_mtd; |
||||
extern struct onenand_chip onenand_chip; |
||||
|
||||
/* References to names in env_common.c */ |
||||
extern uchar default_environment[]; |
||||
|
||||
#define ONENAND_ENV_SIZE(mtd) (mtd.oobblock - ENV_HEADER_SIZE) |
||||
|
||||
char *env_name_spec = "OneNAND"; |
||||
|
||||
#ifdef ENV_IS_EMBEDDED |
||||
extern uchar environment[]; |
||||
env_t *env_ptr = (env_t *) (&environment[0]); |
||||
#else /* ! ENV_IS_EMBEDDED */ |
||||
static unsigned char onenand_env[MAX_ONENAND_PAGESIZE]; |
||||
env_t *env_ptr = (env_t *) onenand_env; |
||||
#endif /* ENV_IS_EMBEDDED */ |
||||
|
||||
uchar env_get_char_spec(int index) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
return (*((uchar *) (gd->env_addr + index))); |
||||
} |
||||
|
||||
void env_relocate_spec(void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
unsigned long env_addr; |
||||
int use_default = 0; |
||||
int retlen; |
||||
|
||||
env_addr = CFG_ENV_ADDR; |
||||
env_addr -= (unsigned long)onenand_chip.base; |
||||
|
||||
/* Check OneNAND exist */ |
||||
if (onenand_mtd.oobblock) |
||||
/* Ignore read fail */ |
||||
onenand_read(&onenand_mtd, env_addr, onenand_mtd.oobblock, |
||||
&retlen, (u_char *) env_ptr); |
||||
else |
||||
onenand_mtd.oobblock = MAX_ONENAND_PAGESIZE; |
||||
|
||||
if (crc32(0, env_ptr->data, ONENAND_ENV_SIZE(onenand_mtd)) != |
||||
env_ptr->crc) |
||||
use_default = 1; |
||||
|
||||
if (use_default) { |
||||
memcpy(env_ptr->data, default_environment, |
||||
ONENAND_ENV_SIZE(onenand_mtd)); |
||||
env_ptr->crc = |
||||
crc32(0, env_ptr->data, ONENAND_ENV_SIZE(onenand_mtd)); |
||||
} |
||||
|
||||
gd->env_addr = (ulong) & env_ptr->data; |
||||
gd->env_valid = 1; |
||||
} |
||||
|
||||
int saveenv(void) |
||||
{ |
||||
unsigned long env_addr = CFG_ENV_ADDR; |
||||
struct erase_info instr; |
||||
int retlen; |
||||
|
||||
instr.len = CFG_ENV_SIZE; |
||||
instr.addr = env_addr; |
||||
instr.addr -= (unsigned long)onenand_chip.base; |
||||
if (onenand_erase(&onenand_mtd, &instr)) { |
||||
printf("OneNAND: erase failed at 0x%08x\n", env_addr); |
||||
return 1; |
||||
} |
||||
|
||||
/* update crc */ |
||||
env_ptr->crc = |
||||
crc32(0, env_ptr->data, onenand_mtd.oobblock - ENV_HEADER_SIZE); |
||||
|
||||
env_addr -= (unsigned long)onenand_chip.base; |
||||
if (onenand_write(&onenand_mtd, env_addr, onenand_mtd.oobblock, &retlen, |
||||
(u_char *) env_ptr)) { |
||||
printf("OneNAND: write failed at 0x%08x\n", instr.addr); |
||||
return 2; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int env_init(void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/* use default */ |
||||
gd->env_addr = (ulong) & default_environment[0]; |
||||
gd->env_valid = 1; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#endif /* CFG_ENV_IS_IN_ONENAND */ |
||||
@ -0,0 +1,44 @@ |
||||
#
|
||||
# Copyright (C) 2005-2007 Samsung Electronics.
|
||||
# Kyungmin Park <kyungmin.park@samsung.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB := $(obj)libonenand.a
|
||||
|
||||
COBJS := onenand_base.o onenand_bbt.o
|
||||
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
all: $(LIB) |
||||
|
||||
$(LIB): $(obj).depend $(OBJS) |
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
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Reference in new issue